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https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002_string.v] - Diff between revs 32 and 38
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| Rev 32 |
Rev 38 |
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Line 1... |
// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \\__/ o\ (C) 2013,2014 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// ============================================================================
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// ============================================================================
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//
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//
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`ifdef SUPPORT_STRING
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`ifdef SUPPORT_STRING
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MVN3:
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MVN3:
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begin
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begin
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state <= IFETCH;
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next_state(IFETCH);
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res <= alu_out;
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res <= alu_out;
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if (acc==32'hFFFFFFFF)
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if (&acc)
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pc <= pc + 32'd1;
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pc <= pc + pc_inc;
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end
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end
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CMPS1:
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CMPS1:
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begin
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begin
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state <= IFETCH;
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next_state(IFETCH);
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res <= alu_out;
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res <= alu_out;
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if (a!=b || acc==32'hFFFFFFFF) begin
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if (a!=b || &acc) begin
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cf <= !(ltu|eq);
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cf <= !(ltu|eq);
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nf <= lt;
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nf <= lt;
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vf <= 1'b0;
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vf <= 1'b0;
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zf <= eq;
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zf <= eq;
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pc <= pc + 32'd1;
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pc <= pc + pc_inc;
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end
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end
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`endif
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`ifdef SUPPORT_816
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MVN816:
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begin
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next_state(BYTE_IFETCH);
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if (&acc[15:0]) begin
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pc <= pc + pc_inc8;
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dbr <= ir[15:8];
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end
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end
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end
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end
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`endif
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`endif
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No newline at end of file
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No newline at end of file
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