| Line 1... |
Line 1... |
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`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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// rtf65002.v
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// - 32 bit CPU
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// 9000 LUT's / 850 ff's / 56 MHz
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// 15 Block RAMs
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// ============================================================================
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//
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`define TRUE 1'b1
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`define TRUE 1'b1
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`define FALSE 1'b0
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`define FALSE 1'b0
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`define RST_VECT 34'h3FFFFFFF8
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`define RST_VECT 34'h3FFFFFFF8
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`define NMI_VECT 34'h3FFFFFFF4
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`define NMI_VECT 34'h3FFFFFFF4
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| Line 330... |
Line 358... |
`define TRB_ABS 8'h1C
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`define TRB_ABS 8'h1C
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`define TSB_ZP 8'h04
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`define TSB_ZP 8'h04
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`define TSB_ZPX 8'h04
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`define TSB_ZPX 8'h04
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`define TSB_ABS 8'h0C
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`define TSB_ABS 8'h0C
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`define BAZ 8'hC1
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`define BXZ 8'hD1
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`define BEQ_RR 8'hE2
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module icachemem(wclk, wr, adr, dat, rclk, pc, insn);
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module icachemem(wclk, wr, adr, dat, rclk, pc, insn);
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input wclk;
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input wclk;
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input wr;
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input wr;
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input [33:0] adr;
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input [33:0] adr;
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input [31:0] dat;
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input [31:0] dat;
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| Line 348... |
Line 380... |
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always @(posedge rclk)
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always @(posedge rclk)
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rpc <= pc;
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rpc <= pc;
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// memL and memH combined allow a 64 bit read
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// memL and memH combined allow a 64 bit read
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syncRam1kx32_1rw1r ramL0
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syncRam2kx32_1rw1r ramL0
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(
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(
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.wrst(1'b0),
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.wrst(1'b0),
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.wclk(wclk),
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.wclk(wclk),
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.wce(~adr[2]),
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.wce(~adr[2]),
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.we(wr),
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.we(wr),
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.wsel(4'hF),
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.wsel(4'hF),
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.wadr(adr[12:3]),
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.wadr(adr[13:3]),
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.i(dat),
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.i(dat),
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.wo(),
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.wo(),
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.rrst(1'b0),
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.rrst(1'b0),
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.rclk(rclk),
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.rclk(rclk),
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.rce(1'b1),
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.rce(1'b1),
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.radr(pc[12:3]),
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.radr(pc[13:3]),
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.o(insn0[31:0])
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.o(insn0[31:0])
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);
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);
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syncRam1kx32_1rw1r ramH0
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syncRam2kx32_1rw1r ramH0
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(
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(
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.wrst(1'b0),
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.wrst(1'b0),
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.wclk(wclk),
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.wclk(wclk),
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.wce(adr[2]),
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.wce(adr[2]),
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.we(wr),
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.we(wr),
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.wsel(4'hF),
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.wsel(4'hF),
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.wadr(adr[12:3]),
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.wadr(adr[13:3]),
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.i(dat),
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.i(dat),
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.wo(),
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.wo(),
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.rrst(1'b0),
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.rrst(1'b0),
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.rclk(rclk),
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.rclk(rclk),
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.rce(1'b1),
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.rce(1'b1),
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.radr(pc[12:3]),
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.radr(pc[13:3]),
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.o(insn0[63:32])
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.o(insn0[63:32])
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);
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);
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syncRam1kx32_1rw1r ramL1
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syncRam2kx32_1rw1r ramL1
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(
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(
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.wrst(1'b0),
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.wrst(1'b0),
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.wclk(wclk),
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.wclk(wclk),
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.wce(~adr[2]),
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.wce(~adr[2]),
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.we(wr),
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.we(wr),
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.wsel(4'hF),
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.wsel(4'hF),
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.wadr(adr[12:3]),
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.wadr(adr[13:3]),
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.i(dat),
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.i(dat),
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.wo(),
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.wo(),
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.rrst(1'b0),
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.rrst(1'b0),
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.rclk(rclk),
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.rclk(rclk),
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.rce(1'b1),
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.rce(1'b1),
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.radr(pcp8[12:3]),
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.radr(pcp8[13:3]),
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.o(insn1[31:0])
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.o(insn1[31:0])
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);
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);
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syncRam1kx32_1rw1r ramH1
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syncRam2kx32_1rw1r ramH1
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(
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(
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.wrst(1'b0),
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.wrst(1'b0),
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.wclk(wclk),
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.wclk(wclk),
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.wce(adr[2]),
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.wce(adr[2]),
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.we(wr),
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.we(wr),
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.wsel(4'hF),
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.wsel(4'hF),
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.wadr(adr[12:3]),
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.wadr(adr[13:3]),
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.i(dat),
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.i(dat),
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.wo(),
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.wo(),
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.rrst(1'b0),
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.rrst(1'b0),
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.rclk(rclk),
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.rclk(rclk),
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.rce(1'b1),
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.rce(1'b1),
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.radr(pcp8[12:3]),
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.radr(pcp8[13:3]),
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.o(insn1[63:32])
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.o(insn1[63:32])
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);
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);
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always @(rpc or insn0 or insn1)
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always @(rpc or insn0 or insn1)
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case(rpc[2:0])
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case(rpc[2:0])
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| Line 449... |
Line 481... |
always @(posedge rclk)
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always @(posedge rclk)
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rpc <= pc;
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rpc <= pc;
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always @(posedge rclk)
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always @(posedge rclk)
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rpcp8 <= pcp8;
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rpcp8 <= pcp8;
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syncRam512x32_1rw2r ram0 (
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syncRam1kx32_1rw1r ram0 (
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.wrst(1'b0),
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.wrst(1'b0),
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.wclk(wclk),
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.wclk(wclk),
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.wce(adr[3:2]==2'b11),
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.wce(adr[3:2]==2'b11),
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.we(wr),
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.we(wr),
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.wadr(adr[12:4]),
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.wsel(4'hF),
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.wadr(adr[13:4]),
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.i(adr[31:0]),
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.i(adr[31:0]),
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.wo(),
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.wo(),
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.rrsta(1'b0),
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.rrst(1'b0),
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.rclka(rclk),
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.rclk(rclk),
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.rcea(1'b1),
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.rce(1'b1),
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.radra(pc[12:4]),
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.radr(pc[13:4]),
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.roa(tag0),
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.o(tag0)
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.rrstb(1'b0),
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.rclkb(rclk),
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.rceb(1'b1),
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.radrb(pcp8[12:4]),
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.rob(tag1)
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);
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);
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assign hit0 = tag0[31:13]==rpc[31:13];
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syncRam1kx32_1rw1r ram1 (
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assign hit1 = tag1[31:13]==rpcp8[31:13];
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.wrst(1'b0),
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.wclk(wclk),
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.wce(adr[3:2]==2'b11),
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.we(wr),
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.wsel(4'hF),
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.wadr(adr[13:4]),
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.i(adr[31:0]),
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.wo(),
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.rrst(1'b0),
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.rclk(rclk),
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.rce(1'b1),
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.radr(pcp8[13:4]),
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.o(tag1)
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);
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assign hit0 = tag0[31:14]==rpc[31:14] && tag0[0];
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assign hit1 = tag1[31:14]==rpcp8[31:14] && tag1[0];
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endmodule
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endmodule
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module dcachemem(wclk, wr, sel, wadr, wdat, rclk, radr, rdat);
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module dcachemem(wclk, wr, sel, wadr, wdat, rclk, radr, rdat);
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input wclk;
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input wclk;
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| Line 563... |
Line 607... |
parameter LOAD_DCACHE = 3'd1;
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parameter LOAD_DCACHE = 3'd1;
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parameter LOAD_ICACHE = 3'd2;
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parameter LOAD_ICACHE = 3'd2;
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parameter LOAD_IBUF1 = 3'd3;
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parameter LOAD_IBUF1 = 3'd3;
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parameter LOAD_IBUF2 = 3'd4;
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parameter LOAD_IBUF2 = 3'd4;
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parameter LOAD_IBUF3 = 3'd5;
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parameter LOAD_IBUF3 = 3'd5;
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parameter RESET = 7'd0;
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parameter RESET1 = 7'd0;
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parameter IFETCH = 7'd1;
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parameter IFETCH = 7'd1;
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parameter JMP_IND1 = 7'd2;
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parameter JMP_IND1 = 7'd2;
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parameter JMP_IND2 = 7'd3;
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parameter JMP_IND2 = 7'd3;
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parameter DECODE = 7'd4;
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parameter DECODE = 7'd4;
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parameter STORE1 = 7'd5;
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parameter STORE1 = 7'd5;
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| Line 660... |
Line 704... |
parameter BYTE_JSL7 = 7'd94;
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parameter BYTE_JSL7 = 7'd94;
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parameter BYTE_PLP1 = 7'd95;
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parameter BYTE_PLP1 = 7'd95;
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parameter BYTE_PLP2 = 7'd96;
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parameter BYTE_PLP2 = 7'd96;
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parameter BYTE_PLA1 = 7'd97;
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parameter BYTE_PLA1 = 7'd97;
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parameter BYTE_PLA2 = 7'd98;
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parameter BYTE_PLA2 = 7'd98;
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parameter WAIT_DHIT = 7'd99;
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parameter RESET2 = 7'd100;
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input rst_i;
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input rst_i;
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input clk_i;
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input clk_i;
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input nmi_i;
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input nmi_i;
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input irq_i;
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input irq_i;
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| Line 679... |
Line 725... |
output reg [33:0] adr_o;
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output reg [33:0] adr_o;
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input [31:0] dat_i;
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input [31:0] dat_i;
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output reg [31:0] dat_o;
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output reg [31:0] dat_o;
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reg [6:0] state;
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reg [6:0] state;
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reg [6:0] retstate;
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reg [2:0] cstate;
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reg [2:0] cstate;
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wire [55:0] insn;
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wire [55:0] insn;
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reg [55:0] ibuf;
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reg [55:0] ibuf;
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reg [31:0] bufadr;
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reg [31:0] bufadr;
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reg cf,nf,zf,vf,bf,im,df,em;
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reg cf,nf,zf,vf,bf,im,df,em;
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reg em1;
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reg em1;
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reg gie;
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reg nmoi; // native mode on interrupt
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reg nmoi; // native mode on interrupt
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wire [31:0] sr = {nf,vf,em,24'b0,bf,df,im,zf,cf};
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wire [31:0] sr = {nf,vf,em,24'b0,bf,df,im,zf,cf};
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wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};
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wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};
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reg nmi1,nmi_edge;
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reg nmi1,nmi_edge;
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reg wai;
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reg wai;
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| Line 758... |
Line 806... |
reg [31:0] vect;
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reg [31:0] vect;
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reg [31:0] ia; // temporary reg to hold indirect address
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reg [31:0] ia; // temporary reg to hold indirect address
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wire [31:0] iapy8 = ia + y[7:0];
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wire [31:0] iapy8 = ia + y[7:0];
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reg isInsnCacheLoad;
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reg isInsnCacheLoad;
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reg isDataCacheLoad;
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reg isDataCacheLoad;
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reg isCacheReset;
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wire hit0,hit1;
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wire hit0,hit1;
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wire dhit;
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wire dhit;
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reg write_allocate;
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reg wr;
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reg wr;
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reg [3:0] wrsel;
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reg [3:0] wrsel;
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reg [31:0] radr;
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reg [31:0] radr;
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reg [1:0] radr2LSB;
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reg [1:0] radr2LSB;
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wire [33:0] radr34 = {radr,radr2LSB};
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wire [33:0] radr34 = {radr,radr2LSB};
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| Line 811... |
Line 861... |
.insn(insn)
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.insn(insn)
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);
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);
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tagmem tgm0 (
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tagmem tgm0 (
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.wclk(clk_i),
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.wclk(clk_i),
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.wr(ack_i & isInsnCacheLoad),
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.wr((ack_i & isInsnCacheLoad)|isCacheReset),
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.adr(adr_o),
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.adr({adr_o[31:1],!isCacheReset}),
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.rclk(~clk_i),
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.rclk(~clk_i),
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.pc(pc),
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.pc(pc),
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.hit0(hit0),
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.hit0(hit0),
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.hit1(hit1)
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.hit1(hit1)
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);
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);
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| Line 898... |
Line 948... |
`BCC: takb <= !cf;
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`BCC: takb <= !cf;
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`BVS: takb <= vf;
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`BVS: takb <= vf;
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`BVC: takb <= !vf;
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`BVC: takb <= !vf;
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`BRA: takb <= 1'b1;
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`BRA: takb <= 1'b1;
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`BRL: takb <= 1'b1;
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`BRL: takb <= 1'b1;
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//`BAZ: takb <= acc8==8'h00;
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//`BXZ: takb <= x8==8'h00;
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default: takb <= 1'b0;
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default: takb <= 1'b0;
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endcase
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endcase
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wire [31:0] zpx_address = dp + ir[15:8] + x8;
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wire [31:0] zpx_address = dp + ir[15:8] + x8;
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wire [31:0] zpy_address = dp + ir[15:8] + y8;
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wire [31:0] zpy_address = dp + ir[15:8] + y8;
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wire [31:0] zp_address = dp + ir[15:8];
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wire [31:0] zp_address = dp + ir[15:8];
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wire [31:0] abs_address = {16'h0,ir[23:8]};
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wire [31:0] absx_address = {16'h0,ir[23:8] + {8'h0,x8}};
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wire [31:0] absx_address = {16'h0,ir[23:8] + {8'h0,x8}};
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wire [31:0] absy_address = {16'h0,ir[23:8] + {8'h0,y8}};
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wire [31:0] absy_address = {16'h0,ir[23:8] + {8'h0,y8}};
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wire [31:0] zpx32xy_address = dp + ir[23:12] + rfoa;
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wire [31:0] zpx32xy_address = dp + ir[23:12] + rfoa;
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wire [31:0] absx32xy_address = ir[47:16] + rfob;
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wire [31:0] absx32xy_address = ir[47:16] + rfob;
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wire [31:0] zpx32_address = dp + ir[31:20] + rfob;
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wire [31:0] zpx32_address = dp + ir[31:20] + rfob;
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| Line 957... |
Line 1010... |
ir <= 56'hEAEAEAEAEAEAEA;
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ir <= 56'hEAEAEAEAEAEAEA;
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imiss <= `FALSE;
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imiss <= `FALSE;
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dmiss <= `FALSE;
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dmiss <= `FALSE;
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dcacheOn <= 1'b0;
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dcacheOn <= 1'b0;
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icacheOn <= 1'b1;
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icacheOn <= 1'b1;
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write_allocate <= 1'b0;
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nmoi <= 1'b1;
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nmoi <= 1'b1;
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state <= RESET;
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state <= RESET1;
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cstate <= IDLE;
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cstate <= IDLE;
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vect <= `RST_VECT;
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vect <= `RST_VECT;
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pc <= 32'hFFFFFFF0;
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pc <= 32'hFFFFFFF0;
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bufadr <= 32'd0;
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bufadr <= 32'd0;
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dp <= 32'd0;
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dp <= 32'd0;
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clk_en <= 1'b1;
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clk_en <= 1'b1;
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isCacheReset <= `TRUE;
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gie <= 1'b0;
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end
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end
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else begin
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else begin
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wr <= 1'b0;
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wr <= 1'b0;
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if (nmi_i & !nmi1)
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if (nmi_i & !nmi1)
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nmi_edge <= 1'b1;
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nmi_edge <= 1'b1;
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if (nmi_i|nmi1)
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if (nmi_i|nmi1)
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clk_en <= 1'b1;
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clk_en <= 1'b1;
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case(state)
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case(state)
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RESET:
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RESET1:
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begin
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adr_o <= adr_o + 32'd4;
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if (adr_o[13:4]==10'h3FF) begin
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state <= RESET2;
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isCacheReset <= `FALSE;
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end
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end
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RESET2:
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begin
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begin
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vect <= `RST_VECT;
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vect <= `RST_VECT;
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radr <= vect[31:2];
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radr <= vect[31:2];
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state <= JMP_IND1;
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state <= JMP_IND1;
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end
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end
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IFETCH:
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IFETCH:
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begin
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begin
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if (nmi_edge & !imiss) begin // imiss indicates cache controller is active and this state is in a waiting loop
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if (nmi_edge & !imiss & gie) begin // imiss indicates cache controller is active and this state is in a waiting loop
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nmi_edge <= 1'b0;
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nmi_edge <= 1'b0;
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wai <= 1'b0;
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wai <= 1'b0;
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bf <= 1'b0;
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bf <= 1'b0;
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if (em & !nmoi) begin
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if (em & !nmoi) begin
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radr <= {24'h1,sp[7:2]};
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radr <= {24'h1,sp[7:2]};
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| Line 1020... |
Line 1084... |
dat_o <= pc;
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dat_o <= pc;
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vect <= `NMI_VECT;
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vect <= `NMI_VECT;
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state <= IRQ1;
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state <= IRQ1;
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end
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end
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end
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end
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else if (irq_i && !imiss) begin
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else if (irq_i && !imiss & gie) begin
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if (im) begin
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if (im) begin
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wai <= 1'b0;
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wai <= 1'b0;
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if (unCachedInsn) begin
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if (unCachedInsn) begin
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if (bhit) begin
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if (bhit) begin
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ir <= ibuf;
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ir <= ibuf;
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| Line 1105... |
Line 1169... |
case(ir[7:0])
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case(ir[7:0])
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`NAT: em <= 1'b0;
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`NAT: em <= 1'b0;
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`TAY,`TXY,`DEY,`INY: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`TAY,`TXY,`DEY,`INY: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`TAX,`TYX,`TSX,`DEX,`INX: begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`TAX,`TYX,`TSX,`DEX,`INX: begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
|
`TSA,`TYA,`TXA,`INA,`DEA: begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
|
`TSA,`TYA,`TXA,`INA,`DEA: begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
|
`TAS,`TXS: sp <= res8[7:0];
|
`TAS,`TXS: begin sp <= res8[7:0]; end
|
`ADC_IMM:
|
`ADC_IMM:
|
begin
|
begin
|
acc[7:0] <= df ? bcaio : res8;
|
acc[7:0] <= df ? bcaio : res8;
|
cf <= df ? bcaico : resc8;
|
cf <= df ? bcaico : resc8;
|
vf <= resv;
|
vf <= resv;
|
| Line 1181... |
Line 1245... |
case(ir[7:0])
|
case(ir[7:0])
|
// `XCE: begin cf <= em; em <= cf; end
|
// `XCE: begin cf <= em; em <= cf; end
|
`EMM: em <= 1'b1;
|
`EMM: em <= 1'b1;
|
`TAY,`TXY,`DEY,`INY: begin y <= res; nf <= resn32; zf <= resz32; end
|
`TAY,`TXY,`DEY,`INY: begin y <= res; nf <= resn32; zf <= resz32; end
|
`TAX,`TYX,`TSX,`DEX,`INX: begin x <= res; nf <= resn32; zf <= resz32; end
|
`TAX,`TYX,`TSX,`DEX,`INX: begin x <= res; nf <= resn32; zf <= resz32; end
|
`TAS,`TXS: isp <= res;
|
`TAS,`TXS: begin isp <= res; gie <= 1'b1; end
|
`TSA,`TYA,`TXA,`INA,`DEA: begin acc <= res; nf <= resn32; zf <= resz32; end
|
`TSA,`TYA,`TXA,`INA,`DEA: begin acc <= res; nf <= resn32; zf <= resz32; end
|
`TRS:
|
`TRS:
|
begin
|
begin
|
case(ir[15:12])
|
case(ir[15:12])
|
4'h0: begin
|
4'h0: begin
|
$display("res=%h",res);
|
$display("res=%h",res);
|
icacheOn <= res[0];
|
icacheOn <= res[0];
|
dcacheOn <= res[1];
|
dcacheOn <= res[1];
|
|
write_allocate <= res[2];
|
end
|
end
|
4'h1: dp <= res;
|
4'h1: dp <= res;
|
4'hE: sp <= res[7:0];
|
4'hE: begin sp <= res[7:0]; end
|
4'hF: isp <= res;
|
4'hF: begin isp <= res; gie <= 1'b1; end
|
endcase
|
endcase
|
end
|
end
|
|
`RR:
|
|
case(ir[23:20])
|
|
`ADD_RR: begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
|
|
`SUB_RR:
|
|
if (Rt==4'h0) // CMP doesn't set overflow
|
|
begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
|
|
else
|
|
begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
|
|
`AND_RR:
|
|
if (Rt==4'h0) // BIT sets overflow
|
|
begin nf <= resn32; vf <= res[30]; zf <= resz32; end
|
|
else
|
|
begin nf <= resn32; zf <= resz32; end
|
|
`OR_RR: begin nf <= resn32; zf <= resz32; end
|
|
`EOR_RR: begin nf <= resn32; zf <= resz32; end
|
|
`MUL_RR: begin nf <= resn32; zf <= resz32; end
|
|
endcase
|
`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR: begin cf <= resc32; nf <= resn32; zf <= resz32; end
|
`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR: begin cf <= resc32; nf <= resn32; zf <= resz32; end
|
`ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
|
`ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
|
begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
|
begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
|
`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
|
`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
|
if (Rt==4'h0) // CMP doesn't set overflow
|
if (Rt==4'h0) // CMP doesn't set overflow
|
| Line 1242... |
Line 1324... |
first_ifetch <= `TRUE;
|
first_ifetch <= `TRUE;
|
Rt <= 4'h0; // Default
|
Rt <= 4'h0; // Default
|
if (em) begin
|
if (em) begin
|
state <= IFETCH;
|
state <= IFETCH;
|
case(ir[7:0])
|
case(ir[7:0])
|
// `XCE: begin pc <= pc + 32'd1; state <= IFETCH; end
|
|
`STP: begin clk_en <= 1'b0; pc <= pc + 32'd1; end
|
`STP: begin clk_en <= 1'b0; pc <= pc + 32'd1; end
|
`NAT: pc <= pc + 32'd1;
|
`NAT: pc <= pc + 32'd1;
|
`NOP: pc <= pc + 32'd1;
|
`NOP: pc <= pc + 32'd1;
|
`CLC: begin cf <= 1'b0; pc <= pc + 32'd1; end
|
`CLC: begin cf <= 1'b0; pc <= pc + 32'd1; end
|
`SEC: begin cf <= 1'b1; pc <= pc + 32'd1; end
|
`SEC: begin cf <= 1'b1; pc <= pc + 32'd1; end
|
| Line 1443... |
Line 1524... |
`LDX_ABS,`LDY_ABS,
|
`LDX_ABS,`LDY_ABS,
|
`CPX_ABS,`CPY_ABS,
|
`CPX_ABS,`CPY_ABS,
|
`BIT_ABS:
|
`BIT_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
radr <= ir[23:10];
|
radr <= abs_address[31:2];
|
radr2LSB <= ir[9:8];
|
radr2LSB <= abs_address[1:0];
|
state <= LOAD1;
|
state <= LOAD1;
|
end
|
end
|
`STA_ABS:
|
`STA_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
wadr <= ir[23:10];
|
wadr <= abs_address[31:2];
|
wadr2LSB <= ir[9:8];
|
wadr2LSB <= abs_address[1:0];
|
wdat <= {4{acc8}};
|
wdat <= {4{acc8}};
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STX_ABS:
|
`STX_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
wadr <= ir[23:10];
|
wadr <= abs_address[31:2];
|
wadr2LSB <= ir[9:8];
|
wadr2LSB <= abs_address[1:0];
|
wdat <= {4{x8}};
|
wdat <= {4{x8}};
|
state <= STORE1;
|
state <= STORE1;
|
end // Handle abs,x
|
end // Handle abs,x
|
`STY_ABS:
|
`STY_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
wadr <= ir[23:10];
|
wadr <= abs_address[31:2];
|
wadr2LSB <= ir[9:8];
|
wadr2LSB <= abs_address[1:0];
|
wdat <= {4{y8}};
|
wdat <= {4{y8}};
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STZ_ABS:
|
`STZ_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
wadr <= ir[23:10];
|
wadr <= abs_address[31:2];
|
wadr2LSB <= ir[9:8];
|
wadr2LSB <= abs_address[1:0];
|
wdat <= {4{8'h00}};
|
wdat <= {4{8'h00}};
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,`LDA_ABSX,
|
`ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,`LDA_ABSX,
|
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX,
|
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX,
|
| Line 1554... |
Line 1635... |
state <= BYTE_IRQ1;
|
state <= BYTE_IRQ1;
|
bf <= 1'b1;
|
bf <= 1'b1;
|
end
|
end
|
`JMP:
|
`JMP:
|
begin
|
begin
|
pc[15:0] <= ir[23:8];
|
pc[15:0] <= abs_address[15:0];
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
`JML:
|
`JML:
|
begin
|
begin
|
pc <= ir[39:8];
|
pc <= ir[39:8];
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
`JMP_IND:
|
`JMP_IND:
|
begin
|
begin
|
radr <= ir[23:10];
|
radr <= abs_address[31:2];
|
radr2LSB <= ir[9:8];
|
radr2LSB <= abs_address[1:0];
|
state <= BYTE_JMP_IND1;
|
state <= BYTE_JMP_IND1;
|
end
|
end
|
`JMP_INDX:
|
`JMP_INDX:
|
begin
|
begin
|
radr <= absx_address[15:2];
|
radr <= absx_address[31:2];
|
radr2LSB <= absx_address[1:0];
|
radr2LSB <= absx_address[1:0];
|
state <= BYTE_JMP_IND1;
|
state <= BYTE_JMP_IND1;
|
end
|
end
|
`JSR:
|
`JSR:
|
begin
|
begin
|
| Line 1816... |
Line 1897... |
`TSX: begin res <= isp; pc <= pc + 32'd1; end
|
`TSX: begin res <= isp; pc <= pc + 32'd1; end
|
`TXS,`TXA,`TXY: begin res <= x; pc <= pc + 32'd1; end
|
`TXS,`TXA,`TXY: begin res <= x; pc <= pc + 32'd1; end
|
`TAX,`TAY,`TAS: begin res <= acc; pc <= pc + 32'd1; end
|
`TAX,`TAY,`TAS: begin res <= acc; pc <= pc + 32'd1; end
|
`TYA,`TYX: begin res <= y; pc <= pc + 32'd1; end
|
`TYA,`TYX: begin res <= y; pc <= pc + 32'd1; end
|
`TRS: begin
|
`TRS: begin
|
$display("Ra=%h,set res=%h", Ra, rfoa);
|
|
res <= rfoa; pc <= pc + 32'd2; end
|
res <= rfoa; pc <= pc + 32'd2; end
|
`TSR: begin
|
`TSR: begin
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
case(ir[11:8])
|
case(ir[11:8])
|
4'h0: res <= {dcacheOn,icacheOn};
|
4'h0: res <= {write_allocate,dcacheOn,icacheOn};
|
4'h1: res <= dp;
|
4'h1: res <= dp;
|
4'h2: res <= prod[31:0];
|
4'h2: res <= prod[31:0];
|
4'h3: res <= prod[63:32];
|
4'h3: res <= prod[63:32];
|
4'hE: res <= sp;
|
4'hE: res <= sp;
|
4'hF: res <= isp;
|
4'hF: res <= isp;
|
| Line 1837... |
Line 1917... |
`LSR_ACC: begin res <= {acc[0],1'b0,acc[31:1]}; pc <= pc + 32'd1; end
|
`LSR_ACC: begin res <= {acc[0],1'b0,acc[31:1]}; pc <= pc + 32'd1; end
|
`ROR_ACC: begin res <= {acc[0],cf,acc[31:1]}; pc <= pc + 32'd1; end
|
`ROR_ACC: begin res <= {acc[0],cf,acc[31:1]}; pc <= pc + 32'd1; end
|
|
|
`RR:
|
`RR:
|
begin
|
begin
|
a <= rfoa;
|
case(ir[23:20])
|
b <= rfob;
|
`ADD_RR: res <= rfoa + rfob;
|
|
`SUB_RR: res <= rfoa - rfob;
|
|
`AND_RR: res <= rfoa & rfob;
|
|
`OR_RR: res <= rfoa | rfob;
|
|
`EOR_RR: res <= rfoa ^ rfob;
|
|
`MUL_RR: begin res <= rfoa * rfob; prod <= rfoa * rfob; end
|
|
endcase
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
state <= CALC;
|
|
end
|
|
`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR:
|
|
begin
|
|
a <= rfoa;
|
|
Rt <= ir[15:12];
|
|
pc <= pc + 32'd2;
|
|
state <= CALC;
|
|
end
|
|
`ADD_IMM8:
|
|
begin
|
|
res <= rfoa + {{24{ir[23]}},ir[23:16]};
|
|
Rt <= ir[15:12];
|
|
pc <= pc + 32'd3;
|
|
state <= IFETCH;
|
|
end
|
|
`SUB_IMM8,`OR_IMM8,`AND_IMM8,`EOR_IMM8:
|
|
begin
|
|
a <= rfoa;
|
|
b <= {{24{ir[23]}},ir[23:16]};
|
|
Rt <= ir[15:12];
|
|
pc <= pc + 32'd3;
|
|
state <= CALC;
|
|
end
|
|
`ADD_IMM16,`SUB_IMM16,`OR_IMM16,`AND_IMM16,`EOR_IMM16:
|
|
begin
|
|
a <= rfoa;
|
|
b <= {{16{ir[31]}},ir[31:16]};
|
|
Rt <= ir[15:12];
|
|
pc <= pc + 32'd4;
|
|
state <= CALC;
|
|
end
|
|
`ADD_IMM32,`SUB_IMM32,`OR_IMM32,`AND_IMM32,`EOR_IMM32,`CMP_IMM32:
|
|
begin
|
|
a <= rfoa;
|
|
b <= ir[47:16];
|
|
Rt <= ir[15:12];
|
|
pc <= pc + 32'd6;
|
|
state <= CALC;
|
|
end
|
|
`LDX_IMM32,`LDY_IMM32,`LDA_IMM32:
|
|
begin
|
|
res <= ir[39:8];
|
|
pc <= pc + 32'd5;
|
|
state <= IFETCH;
|
|
end
|
|
`LDX_IMM16,`LDA_IMM16:
|
|
begin
|
|
res <= {{16{ir[23]}},ir[23:8]};
|
|
pc <= pc + 32'd3;
|
|
state <= IFETCH;
|
|
end
|
|
`LDX_IMM8,`LDA_IMM8:
|
|
begin
|
|
res <= {{24{ir[15]}},ir[15:8]};
|
|
$display("set res=%h",{{24{ir[15]}},ir[15:8]});
|
|
pc <= pc + 32'd2;
|
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
|
|
|
`ASL_RR: begin res <= {rfoa,1'b0}; pc <= pc + 32'd2; Rt <= ir[15:12]; end
|
|
`ROL_RR: begin res <= {rfoa,cf}; pc <= pc + 32'd2; Rt <= ir[15:12]; end
|
|
`LSR_RR: begin res <= {rfoa[0],1'b0,rfoa[31:1]}; pc <= pc + 32'd2; Rt <= ir[15:12]; end
|
|
`ROR_RR: begin res <= {rfoa[0],cf,rfoa[31:1]}; pc <= pc + 32'd2; Rt <= ir[15:12]; end
|
|
|
|
`ADD_IMM8: begin res <= rfoa + {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; end
|
|
`SUB_IMM8: begin res <= rfoa - {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; end
|
|
`OR_IMM8: begin res <= rfoa | {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; end
|
|
`AND_IMM8: begin res <= rfoa & {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; end
|
|
`EOR_IMM8: begin res <= rfoa ^ {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; end
|
|
|
|
`ADD_IMM16: begin res <= rfoa + {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; end
|
|
`SUB_IMM16: begin res <= rfoa - {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; end
|
|
`OR_IMM16: begin res <= rfoa | {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; end
|
|
`AND_IMM16: begin res <= rfoa & {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; end
|
|
`EOR_IMM16: begin res <= rfoa ^ {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; end
|
|
|
|
`ADD_IMM32: begin res <= rfoa + ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; end
|
|
`SUB_IMM32: begin res <= rfoa - ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; end
|
|
`OR_IMM32: begin res <= rfoa | ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; end
|
|
`AND_IMM32: begin res <= rfoa & ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; end
|
|
`EOR_IMM32: begin res <= rfoa ^ ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; end
|
|
|
|
`LDX_IMM32,`LDY_IMM32,`LDA_IMM32: begin res <= ir[39:8]; pc <= pc + 32'd5; end
|
|
`LDX_IMM16,`LDA_IMM16: begin res <= {{16{ir[23]}},ir[23:8]}; pc <= pc + 32'd3; end
|
|
`LDX_IMM8,`LDA_IMM8: begin res <= {{24{ir[15]}},ir[15:8]}; pc <= pc + 32'd2; end
|
|
|
`LDX_ZPX,`LDY_ZPX:
|
`LDX_ZPX,`LDY_ZPX:
|
begin
|
begin
|
radr <= zpx32xy_address;
|
radr <= zpx32xy_address;
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
state <= LOAD1;
|
state <= LOAD1;
|
| Line 2044... |
Line 2101... |
radr <= dp + ir[31:20] + rfob;
|
radr <= dp + ir[31:20] + rfob;
|
state <= IX1;
|
state <= IX1;
|
end
|
end
|
`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND,`ST_RIND:
|
`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND,`ST_RIND:
|
begin
|
begin
|
|
radr <= rfob;
|
|
wadr <= rfob; // for store
|
|
wdat <= rfoa;
|
a <= rfoa;
|
a <= rfoa;
|
if (ir[7:0]==`ST_RIND) begin
|
if (ir[7:0]==`ST_RIND) begin
|
res <= rfoa; // for ST_IX, Rt=0
|
res <= rfoa; // for ST_IX, Rt=0
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
|
state <= STORE1;
|
end
|
end
|
else begin
|
else begin
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
|
state <= LOAD1;
|
end
|
end
|
radr <= rfob;
|
|
state <= IX1;
|
|
end
|
end
|
`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY:
|
`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY:
|
begin
|
begin
|
a <= rfoa;
|
a <= rfoa;
|
if (ir[7:0]==`ST_IY)
|
if (ir[7:0]==`ST_IY)
|
| Line 2294... |
Line 2354... |
pc <= pc + {{24{ir[15]}},ir[15:8]};
|
pc <= pc + {{24{ir[15]}},ir[15:8]};
|
else
|
else
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
end
|
end
|
end
|
end
|
|
/* `BEQ_RR:
|
|
begin
|
|
state <= IFETCH;
|
|
if (ir[23:16]==8'h00) begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= pc + 32'd2;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= pc + 32'd2;
|
|
vect <= `SLP_VECT;
|
|
state <= IRQ1;
|
|
end
|
|
else if (ir[23:16]==8'h1) begin
|
|
if (rfoa==rfob)
|
|
pc <= pc + {{16{ir[39]}},ir[39:24]};
|
|
else
|
|
pc <= pc + 32'd5;
|
|
end
|
|
else begin
|
|
if (takb)
|
|
pc <= pc + {{24{ir[23]}},ir[23:16]};
|
|
else
|
|
pc <= pc + 32'd3;
|
|
end
|
|
end*/
|
`BRL:
|
`BRL:
|
begin
|
begin
|
if (ir[23:8]==16'h0000) begin
|
if (ir[23:8]==16'h0000) begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
| Line 2438... |
Line 2527... |
|
|
// Terminal state for stores. Update the data cache if there was a cache hit.
|
// Terminal state for stores. Update the data cache if there was a cache hit.
|
// Clear any previously set lock status
|
// Clear any previously set lock status
|
STORE2:
|
STORE2:
|
if (ack_i) begin
|
if (ack_i) begin
|
|
state <= IFETCH;
|
lock_o <= 1'b0;
|
lock_o <= 1'b0;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
| Line 2449... |
Line 2539... |
dat_o <= 32'h0;
|
dat_o <= 32'h0;
|
if (dhit) begin
|
if (dhit) begin
|
wrsel <= sel_o;
|
wrsel <= sel_o;
|
wr <= 1'b1;
|
wr <= 1'b1;
|
end
|
end
|
state <= IFETCH;
|
else if (write_allocate) begin
|
|
dmiss <= `TRUE;
|
|
state <= WAIT_DHIT;
|
|
retstate <= IFETCH;
|
|
end
|
end
|
end
|
|
WAIT_DHIT:
|
|
if (dhit)
|
|
state <= retstate;
|
|
|
`include "byte_ix.v"
|
`include "byte_ix.v"
|
`include "byte_iy.v"
|
`include "byte_iy.v"
|
|
|
// Indirect and indirect X addressing mode eg. LDA ($12,x) : (zp)
|
// Indirect and indirect X addressing mode eg. LDA ($12,x) : (zp)
|
| Line 2578... |
Line 2675... |
|
|
`include "calc.v"
|
`include "calc.v"
|
|
|
JSR1:
|
JSR1:
|
if (ack_i) begin
|
if (ack_i) begin
|
|
state <= IFETCH;
|
|
retstate <= IFETCH;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
adr_o <= 34'd0;
|
adr_o <= 34'd0;
|
| Line 2590... |
Line 2689... |
isp <= isp_dec;
|
isp <= isp_dec;
|
if (dhit) begin
|
if (dhit) begin
|
wrsel <= sel_o;
|
wrsel <= sel_o;
|
wr <= 1'b1;
|
wr <= 1'b1;
|
end
|
end
|
state <= IFETCH;
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
end
|
end
|
|
|
`include "byte_jsr.v"
|
`include "byte_jsr.v"
|
|
`include "byte_jsl.v"
|
|
|
JSR_INDX1:
|
JSR_INDX1:
|
if (ack_i) begin
|
if (ack_i) begin
|
|
state <= JMP_IND1;
|
|
retstate <= JMP_IND1;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
adr_o <= 34'd0;
|
adr_o <= 34'd0;
|
| Line 2609... |
Line 2714... |
isp <= isp_dec;
|
isp <= isp_dec;
|
if (dhit) begin
|
if (dhit) begin
|
wrsel <= sel_o;
|
wrsel <= sel_o;
|
wr <= 1'b1;
|
wr <= 1'b1;
|
end
|
end
|
state <= JMP_IND1;
|
else if (write_allocate) begin
|
|
dmiss <= `TRUE;
|
|
state <= WAIT_DHIT;
|
|
end
|
end
|
end
|
BYTE_JSR_INDX1:
|
BYTE_JSR_INDX1:
|
if (ack_i) begin
|
if (ack_i) begin
|
|
state <= BYTE_JSR_INDX2;
|
|
retstate <= BYTE_JSR_INDX2;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
if (dhit) begin
|
if (dhit) begin
|
wrsel <= sel_o;
|
wrsel <= sel_o;
|
wr <= 1'b1;
|
wr <= 1'b1;
|
end
|
end
|
state <= BYTE_JSR_INDX2;
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
end
|
end
|
BYTE_JSR_INDX2:
|
BYTE_JSR_INDX2:
|
begin
|
begin
|
radr <= {24'h1,sp[7:2]};
|
radr <= {24'h1,sp[7:2]};
|
wadr <= {24'h1,sp[7:2]};
|
wadr <= {24'h1,sp[7:2]};
|
| Line 2646... |
Line 2759... |
sp <= sp_dec;
|
sp <= sp_dec;
|
state <= BYTE_JSR_INDX3;
|
state <= BYTE_JSR_INDX3;
|
end
|
end
|
BYTE_JSR_INDX3:
|
BYTE_JSR_INDX3:
|
if (ack_i) begin
|
if (ack_i) begin
|
|
state <= BYTE_JMP_IND1;
|
|
retstate <= BYTE_JMP_IND1;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
adr_o <= 34'd0;
|
adr_o <= 34'd0;
|
| Line 2658... |
Line 2773... |
radr2LSB <= absx_address[1:0];
|
radr2LSB <= absx_address[1:0];
|
if (dhit) begin
|
if (dhit) begin
|
wrsel <= sel_o;
|
wrsel <= sel_o;
|
wr <= 1'b1;
|
wr <= 1'b1;
|
end
|
end
|
state <= BYTE_JMP_IND1;
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
end
|
end
|
JSR161:
|
JSR161:
|
if (ack_i) begin
|
if (ack_i) begin
|
|
state <= IFETCH;
|
|
retstate <= IFETCH;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
pc <= {{16{ir[23]}},ir[23:8]};
|
pc <= {{16{ir[23]}},ir[23:8]};
|
isp <= isp_dec;
|
isp <= isp_dec;
|
if (dhit) begin
|
if (dhit) begin
|
wrsel <= sel_o;
|
wrsel <= sel_o;
|
wr <= 1'b1;
|
wr <= 1'b1;
|
end
|
end
|
state <= IFETCH;
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
end
|
end
|
|
|
`include "byte_plp.v"
|
`include "byte_plp.v"
|
`include "byte_rts.v"
|
`include "byte_rts.v"
|
`include "byte_rti.v"
|
`include "byte_rti.v"
|
`include "rti.v"
|
`include "rti.v"
|
`include "rts.v"
|
`include "rts.v"
|
|
|
PHP1:
|
PHP1:
|
if (ack_i) begin
|
if (ack_i) begin
|
|
state <= IFETCH;
|
|
retstate <= IFETCH;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
adr_o <= 34'd0;
|
adr_o <= 34'd0;
|
| Line 2694... |
Line 2819... |
pc <= pc + 32'd1;
|
pc <= pc + 32'd1;
|
if (dhit) begin
|
if (dhit) begin
|
wr <= 1'b1;
|
wr <= 1'b1;
|
wrsel <= sel_o;
|
wrsel <= sel_o;
|
end
|
end
|
state <= IFETCH;
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
end
|
end
|
`include "plp.v"
|
`include "plp.v"
|
`include "pla.v"
|
`include "pla.v"
|
|
|
`include "byte_irq.v"
|
`include "byte_irq.v"
|
`include "byte_jmp_ind.v"
|
`include "byte_jmp_ind.v"
|
|
|
IRQ1:
|
IRQ1:
|
if (ack_i) begin
|
if (ack_i) begin
|
|
state <= IRQ2;
|
|
retstate <= IRQ2;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
if (dhit) begin
|
if (dhit) begin
|
wrsel <= sel_o;
|
wrsel <= sel_o;
|
wr <= 1'b1;
|
wr <= 1'b1;
|
end
|
end
|
state <= IRQ2;
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
end
|
end
|
IRQ2:
|
IRQ2:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
| Line 2730... |
Line 2863... |
dat_o <= sr;
|
dat_o <= sr;
|
state <= IRQ3;
|
state <= IRQ3;
|
end
|
end
|
IRQ3:
|
IRQ3:
|
if (ack_i) begin
|
if (ack_i) begin
|
|
state <= JMP_IND1;
|
|
retstate <= JMP_IND1;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
if (dhit) begin
|
if (dhit) begin
|
wrsel <= sel_o;
|
wrsel <= sel_o;
|
wr <= 1'b1;
|
wr <= 1'b1;
|
end
|
end
|
|
else if (write_allocate) begin
|
|
dmiss <= `TRUE;
|
|
state <= WAIT_DHIT;
|
|
end
|
radr <= vect[31:2];
|
radr <= vect[31:2];
|
state <= JMP_IND1;
|
|
if (!bf)
|
if (!bf)
|
im <= 1'b1;
|
im <= 1'b1;
|
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
|
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
|
end
|
end
|
JMP_IND1:
|
JMP_IND1:
|
