| Line 20... |
Line 20... |
// GNU General Public License for more details.
|
// GNU General Public License for more details.
|
//
|
//
|
// You should have received a copy of the GNU General Public License
|
// You should have received a copy of the GNU General Public License
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
//
|
//
|
// 9000 LUT's / 850 ff's / 56 MHz
|
|
// 15 Block RAMs
|
|
// ============================================================================
|
// ============================================================================
|
//
|
//
|
`define TRUE 1'b1
|
`define TRUE 1'b1
|
`define FALSE 1'b0
|
`define FALSE 1'b0
|
|
|
| Line 295... |
Line 293... |
`define BMI 8'h30
|
`define BMI 8'h30
|
`define BVS 8'h70
|
`define BVS 8'h70
|
`define BCS 8'hB0
|
`define BCS 8'hB0
|
`define BEQ 8'hF0
|
`define BEQ 8'hF0
|
`define BRL 8'h82
|
`define BRL 8'h82
|
|
`define BRA 8'h80
|
|
|
`define JML 8'h5C
|
`define JML 8'h5C
|
`define JMP 8'h4C
|
`define JMP 8'h4C
|
`define JMP_IND 8'h6C
|
`define JMP_IND 8'h6C
|
`define JMP_INDX 8'h7C
|
`define JMP_INDX 8'h7C
|
| Line 315... |
Line 314... |
`define BRK 8'h00
|
`define BRK 8'h00
|
`define PLX 8'hFA
|
`define PLX 8'hFA
|
`define PLY 8'h7A
|
`define PLY 8'h7A
|
`define PHX 8'hDA
|
`define PHX 8'hDA
|
`define PHY 8'h5A
|
`define PHY 8'h5A
|
`define BRA 8'h80
|
|
`define WAI 8'hCB
|
`define WAI 8'hCB
|
`define PUSH 8'h0B
|
`define PUSH 8'h0B
|
`define POP 8'h2B
|
`define POP 8'h2B
|
|
|
`define LDX_IMM 8'hA2
|
`define LDX_IMM 8'hA2
|
| Line 721... |
Line 719... |
parameter BYTE_PLA2 = 7'd98;
|
parameter BYTE_PLA2 = 7'd98;
|
parameter WAIT_DHIT = 7'd99;
|
parameter WAIT_DHIT = 7'd99;
|
parameter RESET2 = 7'd100;
|
parameter RESET2 = 7'd100;
|
parameter MULDIV1 = 7'd101;
|
parameter MULDIV1 = 7'd101;
|
parameter MULDIV2 = 7'd102;
|
parameter MULDIV2 = 7'd102;
|
|
parameter BYTE_DECODE = 7'd103;
|
|
parameter BYTE_CALC = 7'd104;
|
|
|
input rst_i;
|
input rst_i;
|
input clk_i;
|
input clk_i;
|
input nmi_i;
|
input nmi_i;
|
input irq_i;
|
input irq_i;
|
| Line 830... |
Line 830... |
wire resc = em ? res8[8] : res[32];
|
wire resc = em ? res8[8] : res[32];
|
wire resv = em ? resv8 : resv32;
|
wire resv = em ? resv8 : resv32;
|
|
|
reg [31:0] vect;
|
reg [31:0] vect;
|
reg [31:0] ia; // temporary reg to hold indirect address
|
reg [31:0] ia; // temporary reg to hold indirect address
|
wire [31:0] iapy8 = ia + y[7:0];
|
wire [31:0] iapy8 = abs8 + ia + y[7:0];
|
reg isInsnCacheLoad;
|
reg isInsnCacheLoad;
|
reg isDataCacheLoad;
|
reg isDataCacheLoad;
|
reg isCacheReset;
|
reg isCacheReset;
|
wire hit0,hit1;
|
wire hit0,hit1;
|
wire dhit;
|
wire dhit;
|
| Line 850... |
Line 850... |
reg [31:0] wdat;
|
reg [31:0] wdat;
|
wire [31:0] rdat;
|
wire [31:0] rdat;
|
reg imiss;
|
reg imiss;
|
reg dmiss;
|
reg dmiss;
|
reg icacheOn,dcacheOn;
|
reg icacheOn,dcacheOn;
|
wire unCachedData = radr[31:28]==4'hD || !dcacheOn;
|
wire unCachedData = radr[31:20]==12'hFFD || !dcacheOn; // I/O area is uncached
|
wire unCachedInsn =/* pc[31:28]==4'hF || */!icacheOn;
|
wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn; // The lowest 8kB is uncached.
|
|
|
wire isSub = ir[7:0]==`SUB_ZPX || ir[7:0]==`SUB_IX || ir[7:0]==`SUB_IY ||
|
wire isSub = ir[7:0]==`SUB_ZPX || ir[7:0]==`SUB_IX || ir[7:0]==`SUB_IY ||
|
ir[7:0]==`SUB_ABS || ir[7:0]==`SUB_ABSX || ir[7:0]==`SUB_IMM8 || ir[7:0]==`SUB_IMM16 || ir[7:0]==`SUB_IMM32;
|
ir[7:0]==`SUB_ABS || ir[7:0]==`SUB_ABSX || ir[7:0]==`SUB_IMM8 || ir[7:0]==`SUB_IMM16 || ir[7:0]==`SUB_IMM32;
|
wire isSub8 = ir[7:0]==`SBC_ZP || ir[7:0]==`SBC_ZPX || ir[7:0]==`SBC_IX || ir[7:0]==`SBC_IY || ir[7:0]==`SBC_I ||
|
wire isSub8 = ir[7:0]==`SBC_ZP || ir[7:0]==`SBC_ZPX || ir[7:0]==`SBC_IX || ir[7:0]==`SBC_IY || ir[7:0]==`SBC_I ||
|
ir[7:0]==`SBC_ABS || ir[7:0]==`SBC_ABSX || ir[7:0]==`SBC_ABSY || ir[7:0]==`SBC_IMM;
|
ir[7:0]==`SBC_ABS || ir[7:0]==`SBC_ABSX || ir[7:0]==`SBC_ABSY || ir[7:0]==`SBC_IMM;
|
| Line 1092... |
Line 1092... |
begin
|
begin
|
vect <= `RST_VECT;
|
vect <= `RST_VECT;
|
radr <= vect[31:2];
|
radr <= vect[31:2];
|
state <= JMP_IND1;
|
state <= JMP_IND1;
|
end
|
end
|
IFETCH:
|
|
begin
|
`include "ifetch.v"
|
if (nmi_edge & !imiss & gie) begin // imiss indicates cache controller is active and this state is in a waiting loop
|
`include "decode.v"
|
nmi_edge <= 1'b0;
|
`include "byte_decode.v"
|
wai <= 1'b0;
|
|
bf <= 1'b0;
|
`include "load.v"
|
if (em & !nmoi) begin
|
`include "store.v"
|
radr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
WAIT_DHIT:
|
wadr <= {spage[31:8],sp[7:2]};
|
if (dhit)
|
wadr2LSB <= sp[1:0];
|
state <= retstate;
|
wdat <= {4{pc[31:24]}};
|
|
cyc_o <= 1'b1;
|
`include "byte_ix.v"
|
stb_o <= 1'b1;
|
`include "byte_iy.v"
|
we_o <= 1'b1;
|
|
case(sp[1:0])
|
// Indirect and indirect X addressing mode eg. LDA ($12,x) : (zp)
|
2'd0: sel_o <= 4'b0001;
|
IX1:
|
2'd1: sel_o <= 4'b0010;
|
if (unCachedData) begin
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{pc[31:24]}};
|
|
sp <= sp_dec;
|
|
vect <= `BYTE_NMI_VECT;
|
|
state <= BYTE_IRQ1;
|
|
end
|
|
else begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= pc;
|
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= 4'hf;
|
sel_o <= 4'hF;
|
adr_o <= {radr,2'b00};
|
adr_o <= {isp_dec,2'b00};
|
state <= IX2;
|
dat_o <= pc;
|
|
vect <= `NMI_VECT;
|
|
state <= IRQ1;
|
|
end
|
|
end
|
|
else if (irq_i && !imiss & gie) begin
|
|
if (im) begin
|
|
wai <= 1'b0;
|
|
if (unCachedInsn) begin
|
|
if (bhit) begin
|
|
ir <= ibuf;
|
|
state <= DECODE;
|
|
end
|
end
|
|
else if (dhit) begin
|
|
radr <= rdat;
|
|
wadr <= rdat;
|
|
wdat <= a;
|
|
if (ir[7:0]==`ST_IX)
|
|
state <= STORE1;
|
else
|
else
|
imiss <= `TRUE;
|
state <= LOAD1;
|
end
|
|
else begin
|
|
if (ihit) begin
|
|
ir <= insn;
|
|
state <= DECODE;
|
|
end
|
end
|
else
|
else
|
imiss <= `TRUE;
|
dmiss <= `TRUE;
|
end
|
IX2:
|
end
|
if (ack_i) begin
|
else begin
|
cyc_o <= 1'b0;
|
bf <= 1'b0;
|
stb_o <= 1'b0;
|
wai <= 1'b0;
|
sel_o <= 4'h0;
|
if (em & !nmoi) begin
|
adr_o <= 34'h0;
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= dat_i;
|
radr2LSB <= sp[1:0];
|
wadr <= dat_i; // for stores
|
wadr <= {spage[31:8],sp[7:2]};
|
wdat <= a;
|
wadr2LSB <= sp[1:0];
|
if (ir[7:0]==`ST_IX)
|
wdat <= {4{pc[31:24]}};
|
state <= STORE1;
|
cyc_o <= 1'b1;
|
else
|
stb_o <= 1'b1;
|
state <= LOAD1;
|
we_o <= 1'b1;
|
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{pc[31:24]}};
|
|
sp <= sp_dec;
|
|
vect <= `BYTE_IRQ_VECT;
|
|
state <= BYTE_IRQ1;
|
|
end
|
end
|
else begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
// Indirect Y addressing mode eg. LDA ($12),y
|
wdat <= pc;
|
IY1:
|
|
if (unCachedData) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= 4'hf;
|
sel_o <= 4'hF;
|
adr_o <= {radr,2'b00};
|
adr_o <= {isp_dec,2'b00};
|
state <= IY2;
|
dat_o <= pc;
|
|
vect <= {vbr[31:9],irq_vect,2'b00};
|
|
state <= IRQ1;
|
|
end
|
|
end
|
|
end
|
|
else if (!wai) begin
|
|
if (unCachedInsn) begin
|
|
if (bhit) begin
|
|
ir <= ibuf;
|
|
state <= DECODE;
|
|
end
|
|
else
|
|
imiss <= `TRUE;
|
|
end
|
end
|
else begin
|
else if (dhit) begin
|
if (ihit) begin
|
radr <= rdat;
|
ir <= insn;
|
state <= IY3;
|
state <= DECODE;
|
|
end
|
end
|
else
|
else
|
imiss <= `TRUE;
|
dmiss <= `TRUE;
|
end
|
IY2:
|
end
|
if (ack_i) begin
|
if (first_ifetch) begin
|
cyc_o <= 1'b0;
|
first_ifetch <= `FALSE;
|
stb_o <= 1'b0;
|
if (em) begin
|
sel_o <= 4'h0;
|
case(ir[7:0])
|
adr_o <= 34'h0;
|
`NAT: em <= 1'b0;
|
radr <= dat_i;
|
`TAY,`TXY,`DEY,`INY: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
|
state <= IY3;
|
`TAX,`TYX,`TSX,`DEX,`INX: begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
|
|
`TSA,`TYA,`TXA,`INA,`DEA: begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
|
|
`TAS,`TXS: begin sp <= res8[7:0]; end
|
|
`ADC_IMM:
|
|
begin
|
|
acc[7:0] <= df ? bcaio : res8;
|
|
cf <= df ? bcaico : resc8;
|
|
// vf <= resv8;
|
|
vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);
|
|
nf <= df ? bcaio[7] : resn8;
|
|
zf <= df ? bcaio==8'h00 : resz8;
|
|
end
|
|
`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_I:
|
|
begin
|
|
acc[7:0] <= df ? bcao : res8;
|
|
cf <= df ? bcaco : resc8;
|
|
vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);
|
|
nf <= df ? bcao[7] : resn8;
|
|
zf <= df ? bcao==8'h00 : resz8;
|
|
end
|
|
`SBC_IMM:
|
|
begin
|
|
acc[7:0] <= df ? bcsio : res8;
|
|
cf <= ~(df ? bcsico : resc8);
|
|
vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);
|
|
nf <= df ? bcsio[7] : resn8;
|
|
zf <= df ? bcsio==8'h00 : resz8;
|
|
end
|
|
`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_I:
|
|
begin
|
|
acc[7:0] <= df ? bcso : res8;
|
|
vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);
|
|
cf <= ~(df ? bcsco : resc8);
|
|
nf <= df ? bcso[7] : resn8;
|
|
zf <= df ? bcso==8'h00 : resz8;
|
|
end
|
|
`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_I,
|
|
`CPX_IMM,`CPX_ZP,`CPX_ABS,
|
|
`CPY_IMM,`CPY_ZP,`CPY_ABS:
|
|
begin cf <= ~resc8; nf <= resn8; zf <= resz8; end
|
|
`BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX:
|
|
begin nf <= b8[7]; vf <= b8[6]; zf <= resz8; end
|
|
`TRB_ZP,`TRB_ABS,`TSB_ZP,`TSB_ABS:
|
|
begin zf <= resz8; end
|
|
`LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_I,
|
|
`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_I,
|
|
`ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_I,
|
|
`EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_I:
|
|
begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
|
|
`ASL_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
|
|
`ROL_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
|
|
`LSR_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
|
|
`ROR_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
|
|
`ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
|
|
`ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
|
|
`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
|
|
`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
|
|
`INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn8; zf <= resz8; end
|
|
`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn8; zf <= resz8; end
|
|
`PLA: begin acc[7:0] <= res8; zf <= resz8; nf <= resn8; end
|
|
`PLX: begin x[7:0] <= res8; zf <= resz8; nf <= resn8; end
|
|
`PLY: begin y[7:0] <= res8; zf <= resz8; nf <= resn8; end
|
|
`LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY: begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
|
|
`LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
|
|
endcase
|
|
end
|
end
|
else begin
|
IY3:
|
regfile[Rt] <= res;
|
|
case(Rt)
|
|
4'h1: acc <= res;
|
|
4'h2: x <= res;
|
|
4'h3: y <= res;
|
|
default: ;
|
|
endcase
|
|
case(ir[7:0])
|
|
`EMM: em <= 1'b1;
|
|
`TAY,`TXY,`DEY,`INY: begin y <= res; nf <= resn32; zf <= resz32; end
|
|
`TAX,`TYX,`TSX,`DEX,`INX: begin x <= res; nf <= resn32; zf <= resz32; end
|
|
`TAS,`TXS: begin isp <= res; gie <= 1'b1; end
|
|
`TSA,`TYA,`TXA,`INA,`DEA: begin acc <= res; nf <= resn32; zf <= resz32; end
|
|
`TRS:
|
|
begin
|
begin
|
case(ir[15:12])
|
radr <= radr + y;
|
4'h0: begin
|
wadr <= radr + y;
|
$display("res=%h",res);
|
wdat <= a;
|
icacheOn <= res[0];
|
if (ir[7:0]==`ST_IY)
|
dcacheOn <= res[1];
|
state <= STORE1;
|
write_allocate <= res[2];
|
|
end
|
|
4'h1: dp <= res;
|
|
4'h5: lfsr <= res;
|
|
4'h6: dp8 <= res;
|
|
4'h7: abs8 <= res;
|
|
4'h8: begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end
|
|
4'hE: begin sp <= res[7:0]; spage[31:8] <= res[31:8]; end
|
|
4'hF: begin isp <= res; gie <= 1'b1; end
|
|
endcase
|
|
end
|
|
`RR:
|
|
case(ir[23:20])
|
|
`ADD_RR: begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
|
|
`SUB_RR:
|
|
if (Rt==4'h0) // CMP doesn't set overflow
|
|
begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
|
|
else
|
|
begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
|
|
`AND_RR:
|
|
if (Rt==4'h0) // BIT sets overflow
|
|
begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
|
|
else
|
|
begin nf <= resn32; zf <= resz32; end
|
|
`OR_RR: begin nf <= resn32; zf <= resz32; end
|
|
`EOR_RR: begin nf <= resn32; zf <= resz32; end
|
|
`MUL_RR: begin nf <= resn32; zf <= resz32; end
|
|
`MULS_RR: begin nf <= resn32; zf <= resz32; end
|
|
`DIV_RR: begin nf <= resn32; zf <= resz32; end
|
|
`DIVS_RR: begin nf <= resn32; zf <= resz32; end
|
|
`MOD_RR: begin nf <= resn32; zf <= resz32; end
|
|
`MODS_RR: begin nf <= resn32; zf <= resz32; end
|
|
`ASL_RRR: begin nf <= resn32; zf <= resz32; end
|
|
`LSR_RRR: begin nf <= resn32; zf <= resz32; end
|
|
endcase
|
|
`LD_RR: begin zf <= resz32; nf <= resn32; end
|
|
`DEC_RR,`INC_RR: begin zf <= resz32; nf <= resn32; end
|
|
`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR: begin cf <= resc32; nf <= resn32; zf <= resz32; end
|
|
`ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
|
|
begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
|
|
`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
|
|
if (Rt==4'h0) // CMP doesn't set overflow
|
|
begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
|
|
else
|
|
begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
|
|
`AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:
|
|
if (Rt==4'h0) // BIT sets overflow
|
|
begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
|
|
else
|
else
|
begin nf <= resn32; zf <= resz32; end
|
state <= LOAD1;
|
`ORB_ZPX,`ORB_ABS,`ORB_ABSX,
|
|
`OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
|
|
`EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
|
|
begin nf <= resn32; zf <= resz32; end
|
|
`ASL_ACC: begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
|
|
`ROL_ACC: begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
|
|
`LSR_ACC: begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
|
|
`ROR_ACC: begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
|
|
`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin cf <= resc32; nf <= resn32; zf <= resz32; end
|
|
`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin cf <= resc32; nf <= resn32; zf <= resz32; end
|
|
`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin cf <= resc32; nf <= resn32; zf <= resz32; end
|
|
`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin cf <= resc32; nf <= resn32; zf <= resz32; end
|
|
`ASL_IMM8: begin nf <= resn32; zf <= resz32; end
|
|
`LSR_IMM8: begin nf <= resn32; zf <= resz32; end
|
|
`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn32; zf <= resz32; end
|
|
`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn32; zf <= resz32; end
|
|
`PLA: begin acc <= res; zf <= resz32; nf <= resn32; end
|
|
`PLX: begin x <= res; zf <= resz32; nf <= resn32; end
|
|
`PLY: begin y <= res; zf <= resz32; nf <= resn32; end
|
|
`LDX_IMM32,`LDX_IMM16,`LDX_IMM8,`LDX_ZPY,`LDX_ABS,`LDX_ABSY: begin x <= res; nf <= resn32; zf <= resz32; end
|
|
`LDY_IMM32,`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin y <= res; nf <= resn32; zf <= resz32; end
|
|
`CPX_IMM32,`CPX_ZPX,`CPX_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
|
|
`CPY_IMM32,`CPY_ZPX,`CPY_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
|
|
`CMP_IMM8: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
|
|
`LDA_IMM32,`LDA_IMM16,`LDA_IMM8: begin acc <= res; nf <= resn32; zf <= resz32; end
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
DECODE:
|
|
begin
|
|
first_ifetch <= `TRUE;
|
|
Rt <= 4'h0; // Default
|
|
if (em) begin
|
|
state <= IFETCH;
|
|
case(ir[7:0])
|
|
`STP: begin clk_en <= 1'b0; pc <= pc + 32'd1; end
|
|
`NAT: pc <= pc + 32'd1;
|
|
`NOP: pc <= pc + 32'd1;
|
|
`CLC: begin cf <= 1'b0; pc <= pc + 32'd1; end
|
|
`SEC: begin cf <= 1'b1; pc <= pc + 32'd1; end
|
|
`CLV: begin vf <= 1'b0; pc <= pc + 32'd1; end
|
|
`CLI: begin im <= 1'b0; pc <= pc + 32'd1; end
|
|
`SEI: begin im <= 1'b1; pc <= pc + 32'd1; end
|
|
`CLD: begin df <= 1'b0; pc <= pc + 32'd1; end
|
|
`SED: begin df <= 1'b1; pc <= pc + 32'd1; end
|
|
`WAI: begin wai <= 1'b1; pc <= pc + 32'd1; end
|
|
`DEX: begin res8 <= x[7:0] - 8'd1; pc <= pc + 32'd1; end
|
|
`INX: begin res8 <= x[7:0] + 8'd1; pc <= pc + 32'd1; end
|
|
`DEY: begin res8 <= y[7:0] - 8'd1; pc <= pc + 32'd1; end
|
|
`INY: begin res8 <= y[7:0] + 8'd1; pc <= pc + 32'd1; end
|
|
`DEA: begin res8 <= acc[7:0] - 8'd1; pc <= pc + 32'd1; end
|
|
`INA: begin res8 <= acc[7:0] + 8'd1; pc <= pc + 32'd1; end
|
|
`TSX,`TSA: begin res8 <= sp[7:0]; pc <= pc + 32'd1; end
|
|
`TXS,`TXA,`TXY: begin res8 <= x[7:0]; pc <= pc + 32'd1; end
|
|
`TAX,`TAY,`TAS: begin res8 <= acc[7:0]; pc <= pc + 32'd1; end
|
|
`TYA,`TYX: begin res8 <= y[7:0]; pc <= pc + 32'd1; end
|
|
`ASL_ACC: begin res8 <= {acc8,1'b0}; pc <= pc + 32'd1; end
|
|
`ROL_ACC: begin res8 <= {acc8,cf}; pc <= pc + 32'd1; end
|
|
`LSR_ACC: begin res8 <= {acc8[0],1'b0,acc8[7:1]}; pc <= pc + 32'd1; end
|
|
`ROR_ACC: begin res8 <= {acc8[0],cf,acc8[7:1]}; pc <= pc + 32'd1; end
|
|
// Handle # mode
|
|
`LDA_IMM,`LDX_IMM,`LDY_IMM:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
res8 <= ir[15:8];
|
|
state <= IFETCH;
|
|
end
|
|
`ADC_IMM:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
res8 <= acc8 + ir[15:8] + {7'b0,cf};
|
|
b8 <= ir[15:8]; // for overflow calc
|
|
state <= IFETCH;
|
|
end
|
end
|
`SBC_IMM:
|
|
begin
|
`include "byte_calc.v"
|
pc <= pc + 32'd2;
|
`include "calc.v"
|
// res8 <= acc8 - ir[15:8] - ~cf;
|
`include "byte_jsr.v"
|
res8 <= acc8 - ir[15:8] - {7'b0,~cf};
|
`include "byte_jsl.v"
|
$display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);
|
|
b8 <= ir[15:8]; // for overflow calc
|
JSR1:
|
|
if (ack_i) begin
|
state <= IFETCH;
|
state <= IFETCH;
|
|
retstate <= IFETCH;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'd0;
|
|
dat_o <= 32'd0;
|
|
pc <= vect;
|
|
isp <= isp_dec;
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
end
|
end
|
`AND_IMM,`BIT_IMM:
|
else if (write_allocate) begin
|
begin
|
state <= WAIT_DHIT;
|
pc <= pc + 32'd2;
|
dmiss <= `TRUE;
|
res8 <= acc8 & ir[15:8];
|
|
b8 <= ir[15:8]; // for bit flags
|
|
state <= IFETCH;
|
|
end
|
end
|
`ORA_IMM:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
res8 <= acc8 | ir[15:8];
|
|
state <= IFETCH;
|
|
end
|
end
|
`EOR_IMM:
|
|
begin
|
JSR_INDX1:
|
pc <= pc + 32'd2;
|
if (ack_i) begin
|
res8 <= acc8 ^ ir[15:8];
|
state <= JMP_IND1;
|
state <= IFETCH;
|
retstate <= JMP_IND1;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'd0;
|
|
dat_o <= 32'd0;
|
|
radr <= ir[39:8] + x;
|
|
isp <= isp_dec;
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
end
|
end
|
`CMP_IMM:
|
else if (write_allocate) begin
|
begin
|
dmiss <= `TRUE;
|
pc <= pc + 32'd2;
|
state <= WAIT_DHIT;
|
res8 <= acc8 - ir[15:8];
|
|
state <= IFETCH;
|
|
end
|
end
|
`CPX_IMM:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
res8 <= x8 - ir[15:8];
|
|
state <= IFETCH;
|
|
end
|
end
|
`CPY_IMM:
|
|
begin
|
JSR161:
|
pc <= pc + 32'd2;
|
if (ack_i) begin
|
res8 <= y8 - ir[15:8];
|
|
state <= IFETCH;
|
state <= IFETCH;
|
|
retstate <= IFETCH;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
pc <= {{16{ir[23]}},ir[23:8]};
|
|
isp <= isp_dec;
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
end
|
end
|
// Handle zp mode
|
else if (write_allocate) begin
|
`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,`LDA_ZP,
|
state <= WAIT_DHIT;
|
`LDX_ZP,`LDY_ZP,`BIT_ZP,`CPX_ZP,`CPY_ZP,
|
dmiss <= `TRUE;
|
`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
radr <= zp_address[31:2];
|
|
radr2LSB <= zp_address[1:0];
|
|
state <= LOAD1;
|
|
end
|
|
`STA_ZP:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
wadr <= zp_address[31:2];
|
|
wadr2LSB <= zp_address[1:0];
|
|
wdat <= {4{acc8}};
|
|
state <= STORE1;
|
|
end
|
|
`STX_ZP:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
wadr <= zp_address[31:2];
|
|
wadr2LSB <= zp_address[1:0];
|
|
wdat <= {4{x8}};
|
|
state <= STORE1;
|
|
end
|
|
`STY_ZP:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
wadr <= zp_address[31:2];
|
|
wadr2LSB <= zp_address[1:0];
|
|
wdat <= {4{y8}};
|
|
state <= STORE1;
|
|
end
|
|
`STZ_ZP:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
wadr <= zp_address[31:2];
|
|
wadr2LSB <= zp_address[1:0];
|
|
wdat <= {4{8'h00}};
|
|
state <= STORE1;
|
|
end
|
|
// Handle zp,x mode
|
|
`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,`LDA_ZPX,
|
|
`LDY_ZPX,`BIT_ZPX,
|
|
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
radr <= zpx_address[31:2];
|
|
radr2LSB <= zpx_address[1:0];
|
|
state <= LOAD1;
|
|
end
|
|
`STA_ZPX:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
wadr <= zpx_address[31:2];
|
|
wadr2LSB <= zpx_address[1:0];
|
|
wdat <= {4{acc8}};
|
|
state <= STORE1;
|
|
end
|
|
`STY_ZPX:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
wadr <= zpx_address[31:2];
|
|
wadr2LSB <= zpx_address[1:0];
|
|
wdat <= {4{y8}};
|
|
state <= STORE1;
|
|
end
|
|
`STZ_ZPX:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
wadr <= zpx_address[31:2];
|
|
wadr2LSB <= zpx_address[1:0];
|
|
wdat <= {4{8'h00}};
|
|
state <= STORE1;
|
|
end
|
|
// Handle zp,y
|
|
`LDX_ZPY:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
radr <= zpy_address[31:2];
|
|
radr2LSB <= zpy_address[1:0];
|
|
state <= LOAD1;
|
|
end
|
|
`STX_ZPY:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
wadr <= zpy_address[31:2];
|
|
wadr2LSB <= zpy_address[1:0];
|
|
wdat <= {4{x8}};
|
|
state <= STORE1;
|
|
end
|
|
// Handle (zp,x)
|
|
`ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
radr <= zpx_address[31:2];
|
|
radr2LSB <= zpx_address[1:0];
|
|
state <= BYTE_IX1;
|
|
end
|
|
// Handle (zp),y
|
|
`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
radr <= zp_address[31:2];
|
|
radr2LSB <= zp_address[1:0];
|
|
state <= BYTE_IY1;
|
|
end
|
|
// Handle abs
|
|
`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,`LDA_ABS,
|
|
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
|
|
`LDX_ABS,`LDY_ABS,
|
|
`CPX_ABS,`CPY_ABS,
|
|
`BIT_ABS:
|
|
begin
|
|
pc <= pc + 32'd3;
|
|
radr <= abs_address[31:2];
|
|
radr2LSB <= abs_address[1:0];
|
|
state <= LOAD1;
|
|
end
|
|
`STA_ABS:
|
|
begin
|
|
pc <= pc + 32'd3;
|
|
wadr <= abs_address[31:2];
|
|
wadr2LSB <= abs_address[1:0];
|
|
wdat <= {4{acc8}};
|
|
state <= STORE1;
|
|
end
|
|
`STX_ABS:
|
|
begin
|
|
pc <= pc + 32'd3;
|
|
wadr <= abs_address[31:2];
|
|
wadr2LSB <= abs_address[1:0];
|
|
wdat <= {4{x8}};
|
|
state <= STORE1;
|
|
end
|
|
`STY_ABS:
|
|
begin
|
|
pc <= pc + 32'd3;
|
|
wadr <= abs_address[31:2];
|
|
wadr2LSB <= abs_address[1:0];
|
|
wdat <= {4{y8}};
|
|
state <= STORE1;
|
|
end
|
|
`STZ_ABS:
|
|
begin
|
|
pc <= pc + 32'd3;
|
|
wadr <= abs_address[31:2];
|
|
wadr2LSB <= abs_address[1:0];
|
|
wdat <= {4{8'h00}};
|
|
state <= STORE1;
|
|
end
|
|
// Handle abs,x
|
|
`ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,`LDA_ABSX,
|
|
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX,
|
|
`LDY_ABSX:
|
|
begin
|
|
pc <= pc + 32'd3;
|
|
radr <= absx_address[31:2];
|
|
radr2LSB <= absx_address[1:0];
|
|
state <= LOAD1;
|
|
end
|
|
`STA_ABSX:
|
|
begin
|
|
pc <= pc + 32'd3;
|
|
wadr <= absx_address[31:2];
|
|
wadr2LSB <= absx_address[1:0];
|
|
wdat <= {4{acc8}};
|
|
state <= STORE1;
|
|
end
|
|
`STZ_ABSX:
|
|
begin
|
|
pc <= pc + 32'd3;
|
|
wadr <= absx_address[31:2];
|
|
wadr2LSB <= absx_address[1:0];
|
|
wdat <= {4{8'h00}};
|
|
state <= STORE1;
|
|
end
|
|
// Handle abs,y
|
|
`ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY,`LDA_ABSY,
|
|
`LDX_ABSY:
|
|
begin
|
|
pc <= pc + 32'd3;
|
|
radr <= absy_address[31:2];
|
|
radr2LSB <= absy_address[1:0];
|
|
state <= LOAD1;
|
|
end
|
|
`STA_ABSY:
|
|
begin
|
|
pc <= pc + 32'd3;
|
|
wadr <= absy_address[31:2];
|
|
wadr2LSB <= absy_address[1:0];
|
|
wdat <= {4{acc8}};
|
|
state <= STORE1;
|
|
end
|
|
// Handle (zp)
|
|
`ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
radr <= zp_address[31:2];
|
|
radr2LSB <= zp_address[1:0];
|
|
state <= BYTE_IX1;
|
|
end
|
|
`BRK:
|
|
begin
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
wadr2LSB <= sp[1:0];
|
|
wdat <= {4{pcp1[31:24]}};
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{pcp1[31:24]}};
|
|
sp <= sp_dec;
|
|
vect <= `BYTE_IRQ_VECT;
|
|
state <= BYTE_IRQ1;
|
|
bf <= 1'b1;
|
|
end
|
|
`JMP:
|
|
begin
|
|
pc[15:0] <= abs_address[15:0];
|
|
state <= IFETCH;
|
|
end
|
|
`JML:
|
|
begin
|
|
pc <= ir[39:8];
|
|
state <= IFETCH;
|
|
end
|
|
`JMP_IND:
|
|
begin
|
|
radr <= abs_address[31:2];
|
|
radr2LSB <= abs_address[1:0];
|
|
state <= BYTE_JMP_IND1;
|
|
end
|
|
`JMP_INDX:
|
|
begin
|
|
radr <= absx_address[31:2];
|
|
radr2LSB <= absx_address[1:0];
|
|
state <= BYTE_JMP_IND1;
|
|
end
|
|
`JSR:
|
|
begin
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
wdat <= {4{pcp2[15:8]}};
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{pcp2[15:8]}};
|
|
sp <= sp_dec;
|
|
state <= BYTE_JSR1;
|
|
end
|
|
`JSL:
|
|
begin
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
wdat <= {4{pcp4[31:24]}};
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{pcp4[31:24]}};
|
|
sp <= sp_dec;
|
|
state <= BYTE_JSL1;
|
|
end
|
|
`JSR_INDX:
|
|
begin
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
wdat <= {4{pcp2[15:8]}};
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
case(sp_dec[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{pcp2[15:8]}};
|
|
sp <= sp_dec;
|
|
state <= BYTE_JSR_INDX1;
|
|
end
|
|
`RTS,`RTL:
|
|
begin
|
|
radr <= {spage[31:8],sp_inc[7:2]};
|
|
radr2LSB <= sp_inc[1:0];
|
|
sp <= sp_inc;
|
|
state <= BYTE_RTS1;
|
|
end
|
|
`RTI: begin
|
|
radr <= {spage[31:8],sp_inc[7:2]};
|
|
radr2LSB <= sp_inc[1:0];
|
|
sp <= sp_inc;
|
|
state <= BYTE_RTI9;
|
|
end
|
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
|
|
begin
|
|
state <= IFETCH;
|
|
// if (ir[15:8]==8'hFE) begin
|
|
// radr <= {24'h1,sp[7:2]};
|
|
// radr2LSB <= sp[1:0];
|
|
// wadr <= {24'h1,sp[7:2]};
|
|
// wadr2LSB <= sp[1:0];
|
|
// case(sp[1:0])
|
|
// 2'd0: sel_o <= 4'b0001;
|
|
// 2'd1: sel_o <= 4'b0010;
|
|
// 2'd2: sel_o <= 4'b0100;
|
|
// 2'd3: sel_o <= 4'b1000;
|
|
// endcase
|
|
// wdat <= {4{pcp2[31:24]}};
|
|
// cyc_o <= 1'b1;
|
|
// stb_o <= 1'b1;
|
|
// we_o <= 1'b1;
|
|
// adr_o <= {24'h1,sp[7:2],2'b00};
|
|
// dat_o <= {4{pcp2[31:24]}};
|
|
// vect <= `SLP_VECT;
|
|
// state <= BYTE_IRQ1;
|
|
// end
|
|
// else
|
|
if (ir[15:8]==8'hFF) begin
|
|
if (takb)
|
|
pc <= pc + {{16{ir[31]}},ir[31:16]};
|
|
else
|
|
pc <= pc + 32'd4;
|
|
end
|
|
else begin
|
|
if (takb)
|
|
pc <= pc + {{24{ir[15]}},ir[15:8]} + 32'd2;
|
|
else
|
|
pc <= pc + 32'd2;
|
|
end
|
|
end
|
|
`PHP:
|
|
begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
wadr2LSB <= sp[1:0];
|
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{sr8}};
|
|
wdat <= {4{sr8}};
|
|
sp <= sp_dec;
|
|
state <= PHP1;
|
|
end
|
|
`PHA:
|
|
begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
wadr2LSB <= sp[1:0];
|
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{acc8}};
|
|
wdat <= {4{acc8}};
|
|
sp <= sp_dec;
|
|
state <= PHP1;
|
|
end
|
|
`PHX:
|
|
begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
wadr2LSB <= sp[1:0];
|
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{x8}};
|
|
wdat <= {4{x8}};
|
|
sp <= sp_dec;
|
|
state <= PHP1;
|
|
end
|
|
`PHY:
|
|
begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
wadr2LSB <= sp[1:0];
|
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{y8}};
|
|
wdat <= {4{y8}};
|
|
sp <= sp_dec;
|
|
state <= PHP1;
|
|
end
|
|
`PLP:
|
|
begin
|
|
radr <= {spage[31:8],sp_inc[7:2]};
|
|
radr2LSB <= sp_inc[1:0];
|
|
sp <= sp_inc;
|
|
state <= BYTE_PLP1;
|
|
pc <= pc + 32'd1;
|
|
end
|
|
`PLA,`PLX,`PLY:
|
|
begin
|
|
radr <= {spage[31:8],sp_inc[7:2]};
|
|
radr2LSB <= sp_inc[1:0];
|
|
sp <= sp_inc;
|
|
state <= PLA1;
|
|
pc <= pc + 32'd1;
|
|
end
|
|
default: // unimplemented opcode
|
|
pc <= pc + 32'd1;
|
|
endcase
|
|
end
|
|
else begin
|
|
state <= IFETCH;
|
|
case(ir[7:0])
|
|
`STP: begin clk_en <= 1'b0; pc <= pc + 32'd1; end
|
|
`NOP: begin pc <= pc + 32'd1; end
|
|
`CLC: begin cf <= 1'b0; pc <= pc + 32'd1; end
|
|
`SEC: begin cf <= 1'b1; pc <= pc + 32'd1; end
|
|
`CLV: begin vf <= 1'b0; pc <= pc + 32'd1; end
|
|
`CLI: begin im <= 1'b0; pc <= pc + 32'd1; end
|
|
`CLD: begin df <= 1'b0; pc <= pc + 32'd1; end
|
|
`SED: begin df <= 1'b1; pc <= pc + 32'd1; end
|
|
`SEI: begin im <= 1'b1; pc <= pc + 32'd1; end
|
|
`WAI: begin wai <= 1'b1; pc <= pc + 32'd1; end
|
|
`EMM: begin pc <= pc + 32'd1; end
|
|
`DEX: begin res <= x - 32'd1; pc <= pc + 32'd1; end
|
|
`INX: begin res <= x + 32'd1; pc <= pc + 32'd1; end
|
|
`DEY: begin res <= y - 32'd1; pc <= pc + 32'd1; end
|
|
`INY: begin res <= y + 32'd1; pc <= pc + 32'd1; end
|
|
`DEA: begin res <= acc - 32'd1; pc <= pc + 32'd1; end
|
|
`INA: begin res <= acc + 32'd1; pc <= pc + 32'd1; end
|
|
`TSX: begin res <= isp; pc <= pc + 32'd1; end
|
|
`TXS,`TXA,`TXY: begin res <= x; pc <= pc + 32'd1; end
|
|
`TAX,`TAY,`TAS: begin res <= acc; pc <= pc + 32'd1; end
|
|
`TYA,`TYX: begin res <= y; pc <= pc + 32'd1; end
|
|
`TRS: begin
|
|
res <= rfoa; pc <= pc + 32'd2; end
|
|
`TSR: begin
|
|
Rt <= ir[15:12];
|
|
case(ir[11:8])
|
|
4'h0: res <= {write_allocate,dcacheOn,icacheOn};
|
|
4'h1: res <= dp;
|
|
4'h2: res <= prod[31:0];
|
|
4'h3: res <= prod[63:32];
|
|
4'h4: res <= tick;
|
|
4'h5: begin res <= lfsr; lfsr <= {lfsr[30:0],lfsr_fb}; end
|
|
4'h6: res <= dp8;
|
|
4'h7: res <= abs8;
|
|
4'h8: res <= {vbr[31:1],nmoi};
|
|
4'hE: res <= {spage[31:8],sp};
|
|
4'hF: res <= isp;
|
|
endcase
|
|
pc <= pc + 32'd2;
|
|
end
|
|
`ASL_ACC: begin res <= {acc,1'b0}; pc <= pc + 32'd1; end
|
|
`ROL_ACC: begin res <= {acc,cf}; pc <= pc + 32'd1; end
|
|
`LSR_ACC: begin res <= {acc[0],1'b0,acc[31:1]}; pc <= pc + 32'd1; end
|
|
`ROR_ACC: begin res <= {acc[0],cf,acc[31:1]}; pc <= pc + 32'd1; end
|
|
|
|
`RR:
|
|
begin
|
|
state <= IFETCH;
|
|
case(ir[23:20])
|
|
`ADD_RR: begin res <= rfoa + rfob; a <= rfoa; b <= rfob; end
|
|
`SUB_RR: begin res <= rfoa - rfob; a <= rfoa; b <= rfob; end
|
|
`AND_RR: begin res <= rfoa & rfob; a <= rfoa; b <= rfob; end // for bit flags
|
|
`OR_RR: begin res <= rfoa | rfob; a <= rfoa; b <= rfob; end
|
|
`EOR_RR: begin res <= rfoa ^ rfob; a <= rfoa; b <= rfob; end
|
|
`MUL_RR: begin state <= MULDIV1; end
|
|
`MULS_RR: begin state <= MULDIV1; end
|
|
`DIV_RR: begin state <= MULDIV1; end
|
|
`DIVS_RR: begin state <= MULDIV1; end
|
|
`MOD_RR: begin state <= MULDIV1; end
|
|
`MODS_RR: begin state <= MULDIV1; end
|
|
`ASL_RRR: begin a <= rfoa; b <= rfob; state <= CALC; end
|
|
`LSR_RRR: begin a <= rfoa; b <= rfob; state <= CALC; end
|
|
endcase
|
|
Rt <= ir[19:16];
|
|
pc <= pc + 32'd3;
|
|
end
|
|
`LD_RR: begin res <= rfoa; Rt <= ir[15:12]; pc <= pc + 32'd2; end
|
|
`ASL_RR: begin res <= {rfoa,1'b0}; pc <= pc + 32'd2; Rt <= ir[15:12]; end
|
|
`ROL_RR: begin res <= {rfoa,cf}; pc <= pc + 32'd2; Rt <= ir[15:12]; end
|
|
`LSR_RR: begin res <= {rfoa[0],1'b0,rfoa[31:1]}; pc <= pc + 32'd2; Rt <= ir[15:12]; end
|
|
`ROR_RR: begin res <= {rfoa[0],cf,rfoa[31:1]}; pc <= pc + 32'd2; Rt <= ir[15:12]; end
|
|
`DEC_RR: begin res <= rfoa - 32'd1; pc <= pc + 32'd2; Rt <= ir[15:12]; end
|
|
`INC_RR: begin res <= rfoa + 32'd1; pc <= pc + 32'd2; Rt <= ir[15:12]; end
|
|
|
|
`ADD_IMM8: begin res <= rfoa + {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; a <= rfoa; b <= {{24{ir[23]}},ir[23:16]}; end
|
|
`SUB_IMM8: begin res <= rfoa - {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; a <= rfoa; b <= {{24{ir[23]}},ir[23:16]}; end
|
|
`OR_IMM8: begin res <= rfoa | {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; b <= {{24{ir[23]}},ir[23:16]}; end
|
|
`AND_IMM8: begin res <= rfoa & {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; b <= {{24{ir[23]}},ir[23:16]}; end
|
|
`EOR_IMM8: begin res <= rfoa ^ {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; pc <= pc + 32'd3; b <= {{24{ir[23]}},ir[23:16]}; end
|
|
`CMP_IMM8: begin res <= acc - {{24{ir[15]}},ir[15:8]}; Rt <= 4'h0; pc <= pc + 32'd2; b <= {{24{ir[15]}},ir[15:8]}; end
|
|
`ASL_IMM8: begin a <= rfoa; b <= ir[20:16]; Rt <= ir[15:12]; pc <= pc + 32'd3; state <= CALC; end
|
|
`LSR_IMM8: begin a <= rfoa; b <= ir[20:16]; Rt <= ir[15:12]; pc <= pc + 32'd3; state <= CALC; end
|
|
|
|
`ADD_IMM16: begin res <= rfoa + {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
|
|
`SUB_IMM16: begin res <= rfoa - {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
|
|
`OR_IMM16: begin res <= rfoa | {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; b <= {{16{ir[31]}},ir[31:16]}; end
|
|
`AND_IMM16: begin res <= rfoa & {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; b <= {{16{ir[31]}},ir[31:16]}; end
|
|
`EOR_IMM16: begin res <= rfoa ^ {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; pc <= pc + 32'd4; b <= {{16{ir[31]}},ir[31:16]}; end
|
|
|
|
`ADD_IMM32: begin res <= rfoa + ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; a <= rfoa; b <= ir[47:16]; end
|
|
`SUB_IMM32: begin res <= rfoa - ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; a <= rfoa; b <= ir[47:16]; end
|
|
`OR_IMM32: begin res <= rfoa | ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; b <= ir[47:16]; end
|
|
`AND_IMM32: begin res <= rfoa & ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; b <= ir[47:16]; end
|
|
`EOR_IMM32: begin res <= rfoa ^ ir[47:16]; Rt <= ir[15:12]; pc <= pc + 32'd6; b <= ir[47:16]; end
|
|
|
|
`LDX_IMM32,`LDY_IMM32,`LDA_IMM32: begin res <= ir[39:8]; pc <= pc + 32'd5; end
|
|
`LDX_IMM16,`LDA_IMM16: begin res <= {{16{ir[23]}},ir[23:8]}; pc <= pc + 32'd3; end
|
|
`LDX_IMM8,`LDA_IMM8: begin res <= {{24{ir[15]}},ir[15:8]}; pc <= pc + 32'd2; end
|
|
|
|
`LDX_ZPX,`LDY_ZPX:
|
|
begin
|
|
radr <= zpx32xy_address;
|
|
pc <= pc + 32'd3;
|
|
state <= LOAD1;
|
|
end
|
|
`ORB_ZPX:
|
|
begin
|
|
a <= rfoa;
|
|
Rt <= ir[19:16];
|
|
radr <= zpx32_address[31:2];
|
|
radr2LSB <= zpx32_address[1:0];
|
|
pc <= pc + 32'd4;
|
|
state <= LOAD1;
|
|
end
|
|
`LDX_ABS,`LDY_ABS:
|
|
begin
|
|
radr <= ir[39:8];
|
|
pc <= pc + 32'd5;
|
|
state <= LOAD1;
|
|
end
|
|
`ORB_ABS:
|
|
begin
|
|
a <= rfoa;
|
|
Rt <= ir[15:12];
|
|
radr <= ir[47:18];
|
|
radr2LSB <= ir[17:16];
|
|
pc <= pc + 32'd6;
|
|
state <= LOAD1;
|
|
end
|
|
`LDX_ABSY,`LDY_ABSX:
|
|
begin
|
|
radr <= absx32xy_address;
|
|
pc <= pc + 32'd6;
|
|
state <= LOAD1;
|
|
end
|
|
`ORB_ABSX:
|
|
begin
|
|
a <= rfoa;
|
|
Rt <= ir[19:16];
|
|
radr <= absx32_address[31:2];
|
|
radr2LSB <= absx32_address[1:0];
|
|
pc <= pc + 32'd7;
|
|
state <= LOAD1;
|
|
end
|
|
`ST_ZPX:
|
|
begin
|
|
wadr <= zpx32_address;
|
|
wdat <= rfoa;
|
|
pc <= pc + 32'd4;
|
|
state <= STORE1;
|
|
end
|
|
`STB_ZPX:
|
|
begin
|
|
wadr <= zpx32_address[31:2];
|
|
wadr2LSB <= zpx32_address[1:0];
|
|
pc <= pc + 32'd4;
|
|
state <= STORE1;
|
|
end
|
|
`ST_ABS:
|
|
begin
|
|
wadr <= ir[47:16];
|
|
wdat <= rfoa;
|
|
pc <= pc + 32'd6;
|
|
state <= STORE1;
|
|
end
|
|
`STB_ABS:
|
|
begin
|
|
wadr <= ir[47:18];
|
|
wadr2LSB <= ir[17:16];
|
|
wdat <= {4{rfoa[7:0]}};
|
|
pc <= pc + 32'd6;
|
|
state <= STORE1;
|
|
end
|
|
`ST_ABSX:
|
|
begin
|
|
wadr <= absx32_address;
|
|
wdat <= rfoa;
|
|
pc <= pc + 32'd7;
|
|
state <= STORE1;
|
|
end
|
|
`STB_ABSX:
|
|
begin
|
|
wadr <= absx32_address[31:2];
|
|
wadr2LSB <= absx32_address[1:0];
|
|
wdat <= {4{rfoa[7:0]}};
|
|
pc <= pc + 32'd7;
|
|
state <= STORE1;
|
|
end
|
|
`STX_ZPX:
|
|
begin
|
|
wadr <= dp + ir[23:12] + rfoa;
|
|
wdat <= x;
|
|
pc <= pc + 32'd3;
|
|
state <= STORE1;
|
|
end
|
|
`STX_ABS:
|
|
begin
|
|
wadr <= ir[39:8];
|
|
wdat <= x;
|
|
pc <= pc + 32'd5;
|
|
state <= STORE1;
|
|
end
|
|
`STY_ZPX:
|
|
begin
|
|
wadr <= dp + ir[23:12] + rfoa;
|
|
wdat <= y;
|
|
pc <= pc + 32'd3;
|
|
state <= STORE1;
|
|
end
|
|
`STY_ABS:
|
|
begin
|
|
wadr <= ir[39:8];
|
|
wdat <= y;
|
|
pc <= pc + 32'd5;
|
|
state <= STORE1;
|
|
end
|
|
`ADD_ZPX,`SUB_ZPX,`OR_ZPX,`AND_ZPX,`EOR_ZPX:
|
|
begin
|
|
a <= rfoa;
|
|
Rt <= ir[19:16];
|
|
radr <= zpx32_address;
|
|
pc <= pc + 32'd4;
|
|
state <= LOAD1;
|
|
end
|
|
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
|
|
begin
|
|
radr <= dp + rfoa + ir[23:12];
|
|
pc <= pc + 32'd3;
|
|
state <= LOAD1;
|
|
end
|
|
`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX:
|
|
begin
|
|
a <= rfoa;
|
|
if (ir[7:0]==`ST_IX)
|
|
res <= rfoa; // for ST_IX, Rt=0
|
|
else
|
|
Rt <= ir[19:16];
|
|
pc <= pc + 32'd4;
|
|
radr <= dp + ir[31:20] + rfob;
|
|
state <= IX1;
|
|
end
|
|
`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND,`ST_RIND:
|
|
begin
|
|
radr <= rfob;
|
|
wadr <= rfob; // for store
|
|
wdat <= rfoa;
|
|
a <= rfoa;
|
|
if (ir[7:0]==`ST_RIND) begin
|
|
res <= rfoa; // for ST_IX, Rt=0
|
|
pc <= pc + 32'd2;
|
|
state <= STORE1;
|
|
end
|
|
else begin
|
|
Rt <= ir[19:16];
|
|
pc <= pc + 32'd3;
|
|
state <= LOAD1;
|
|
end
|
|
end
|
|
`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY:
|
|
begin
|
|
a <= rfoa;
|
|
if (ir[7:0]==`ST_IY)
|
|
res <= rfoa; // for ST_IY, Rt=0
|
|
else
|
|
Rt <= ir[19:16];
|
|
pc <= pc + 32'd4;
|
|
radr <= dp + ir[31:20];
|
|
state <= IY1;
|
|
end
|
|
`ADD_ABS,`SUB_ABS,`OR_ABS,`AND_ABS,`EOR_ABS:
|
|
begin
|
|
a <= rfoa;
|
|
radr <= ir[47:16];
|
|
Rt <= ir[15:12];
|
|
pc <= pc + 32'd6;
|
|
state <= LOAD1;
|
|
end
|
|
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
|
|
begin
|
|
radr <= ir[39:8];
|
|
pc <= pc + 32'd5;
|
|
state <= LOAD1;
|
|
end
|
|
`ADD_ABSX,`SUB_ABSX,`OR_ABSX,`AND_ABSX,`EOR_ABSX:
|
|
begin
|
|
a <= rfoa;
|
|
radr <= ir[55:24] + rfob;
|
|
Rt <= ir[19:16];
|
|
pc <= pc + 32'd7;
|
|
state <= LOAD1;
|
|
end
|
|
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
|
|
begin
|
|
radr <= ir[47:16] + rfob;
|
|
pc <= pc + 32'd6;
|
|
state <= LOAD1;
|
|
end
|
|
`CPX_IMM32:
|
|
begin
|
|
res <= x - ir[39:8];
|
|
pc <= pc + 32'd5;
|
|
state <= IFETCH;
|
|
end
|
|
`CPY_IMM32:
|
|
begin
|
|
res <= y - ir[39:8];
|
|
pc <= pc + 32'd5;
|
|
state <= IFETCH;
|
|
end
|
|
`CPX_ZPX:
|
|
begin
|
|
radr <= dp + ir[23:12] + rfoa;
|
|
pc <= pc + 32'd3;
|
|
state <= LOAD1;
|
|
end
|
|
`CPY_ZPX:
|
|
begin
|
|
radr <= dp + ir[23:12] + rfoa;
|
|
pc <= pc + 32'd3;
|
|
state <= LOAD1;
|
|
end
|
|
`CPX_ABS:
|
|
begin
|
|
radr <= ir[39:8];
|
|
pc <= pc + 32'd5;
|
|
state <= LOAD1;
|
|
end
|
|
`CPY_ABS:
|
|
begin
|
|
radr <= ir[39:8];
|
|
pc <= pc + 32'd5;
|
|
state <= LOAD1;
|
|
end
|
|
`BRK:
|
|
begin
|
|
bf <= 1'b1;
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= pc + 32'd1;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= pc + 32'd1;
|
|
vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
|
|
state <= IRQ1;
|
|
end
|
|
`JMP:
|
|
begin
|
|
pc[15:0] <= ir[23:8];
|
|
state <= IFETCH;
|
|
end
|
|
`JML:
|
|
begin
|
|
pc <= ir[39:8];
|
|
state <= IFETCH;
|
|
end
|
|
`JMP_IND:
|
|
begin
|
|
radr <= ir[39:8];
|
|
state <= JMP_IND1;
|
|
end
|
|
`JMP_INDX:
|
|
begin
|
|
radr <= ir[39:8] + x;
|
|
state <= JMP_IND1;
|
|
end
|
|
`JMP_RIND:
|
|
begin
|
|
pc <= rfoa;
|
|
res <= pc + 32'd2;
|
|
Rt <= ir[15:12];
|
|
state <= IFETCH;
|
|
end
|
|
`JSR:
|
|
begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= pc + 32'd3;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= pc + 32'd3;
|
|
vect <= {pc[31:16],ir[23:8]};
|
|
state <= JSR1;
|
|
end
|
|
`JSR_RIND:
|
|
begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= pc + 32'd2;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= pc + 32'd2;
|
|
vect <= rfoa;
|
|
state <= JSR1;
|
|
$stop;
|
|
end
|
|
`JSL:
|
|
begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= pc + 32'd5;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= pc + 32'd5;
|
|
vect <= ir[39:8];
|
|
state <= JSR1;
|
|
end
|
|
`BSR:
|
|
begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= pc + 32'd3;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= pc + 32'd3;
|
|
vect <= pc + {{16{ir[23]}},ir[23:8]};
|
|
state <= JSR1;
|
|
end
|
|
`JSR_INDX:
|
|
begin
|
|
radr <= isp - 32'd1;
|
|
wadr <= isp - 32'd1;
|
|
wdat <= pc + 32'd5;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp-32'd1,2'b00};
|
|
dat_o <= pc + 32'd5;
|
|
state <= JSR_INDX1;
|
|
end
|
|
// `JSR16:
|
|
// begin
|
|
// radr <= isp - 32'd1;
|
|
// wadr <= isp - 32'd1;
|
|
// wdat <= pc + 32'd3;
|
|
// cyc_o <= 1'b1;
|
|
// stb_o <= 1'b1;
|
|
// we_o <= 1'b1;
|
|
// sel_o <= 4'hF;
|
|
// adr_o <= {isp-32'd1,2'b00};
|
|
// dat_o <= pc + 32'd3;
|
|
// state <= JSR161;
|
|
// end
|
|
`RTS,`RTL:
|
|
begin
|
|
radr <= isp;
|
|
state <= RTS1;
|
|
end
|
|
`RTI: begin
|
|
radr <= isp;
|
|
state <= RTI1;
|
|
end
|
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
|
|
begin
|
|
state <= IFETCH;
|
|
if (ir[15:8]==8'h00) begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= pc + 32'd2;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= pc + 32'd2;
|
|
vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
|
|
state <= IRQ1;
|
|
end
|
|
else if (ir[15:8]==8'h1) begin
|
|
if (takb)
|
|
pc <= pc + {{16{ir[31]}},ir[31:16]};
|
|
else
|
|
pc <= pc + 32'd4;
|
|
end
|
|
else begin
|
|
if (takb)
|
|
pc <= pc + {{24{ir[15]}},ir[15:8]};
|
|
else
|
|
pc <= pc + 32'd2;
|
|
end
|
|
end
|
|
/* `BEQ_RR:
|
|
begin
|
|
state <= IFETCH;
|
|
if (ir[23:16]==8'h00) begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= pc + 32'd2;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= pc + 32'd2;
|
|
vect <= `SLP_VECT;
|
|
state <= IRQ1;
|
|
end
|
|
else if (ir[23:16]==8'h1) begin
|
|
if (rfoa==rfob)
|
|
pc <= pc + {{16{ir[39]}},ir[39:24]};
|
|
else
|
|
pc <= pc + 32'd5;
|
|
end
|
|
else begin
|
|
if (takb)
|
|
pc <= pc + {{24{ir[23]}},ir[23:16]};
|
|
else
|
|
pc <= pc + 32'd3;
|
|
end
|
|
end*/
|
|
`BRL:
|
|
begin
|
|
if (ir[23:8]==16'h0000) begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= pc + 32'd3;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= pc + 32'd3;
|
|
vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
|
|
state <= IRQ1;
|
|
end
|
|
else begin
|
|
pc <= pc + {{16{ir[23]}},ir[23:8]};
|
|
state <= IFETCH;
|
|
end
|
|
end
|
|
`PHP:
|
|
begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
we_o <= 1'b1;
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= sr;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= sr;
|
|
isp <= isp_dec;
|
|
state <= PHP1;
|
|
end
|
|
`PHA:
|
|
begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
we_o <= 1'b1;
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= acc;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= acc;
|
|
isp <= isp_dec;
|
|
state <= PHP1;
|
|
end
|
|
`PHX:
|
|
begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
we_o <= 1'b1;
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= x;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= x;
|
|
isp <= isp_dec;
|
|
state <= PHP1;
|
|
end
|
|
`PHY:
|
|
begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
we_o <= 1'b1;
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= y;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= y;
|
|
isp <= isp_dec;
|
|
state <= PHP1;
|
|
end
|
|
`PUSH:
|
|
begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
we_o <= 1'b1;
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= rfoa;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= rfoa;
|
|
state <= PHP1;
|
|
isp <= isp_dec;
|
|
pc <= pc + 32'd1;
|
|
end
|
|
`PLP:
|
|
begin
|
|
radr <= isp;
|
|
state <= PLP1;
|
|
pc <= pc + 32'd1;
|
|
end
|
|
`PLA,`PLX,`PLY:
|
|
begin
|
|
radr <= isp;
|
|
isp <= isp_inc;
|
|
state <= PLA1;
|
|
pc <= pc + 32'd1;
|
|
end
|
|
`POP:
|
|
begin
|
|
Rt <= ir[15:12];
|
|
radr <= isp;
|
|
isp <= isp_inc;
|
|
state <= PLA1;
|
|
pc <= pc + 32'd2;
|
|
end
|
|
default: // unimplemented opcode
|
|
pc <= pc + 32'd1;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
// Stores always write through to memory, then optionally update the cache if
|
|
// there was a write hit.
|
|
STORE1:
|
|
begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
if (em || isStb)
|
|
case(wadr2LSB)
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
else
|
|
sel_o <= 4'hf;
|
|
adr_o <= {wadr,2'b00};
|
|
dat_o <= wdat;
|
|
radr <= wadr; // Do a cache read to test the hit
|
|
state <= STORE2;
|
|
end
|
|
|
|
// Terminal state for stores. Update the data cache if there was a cache hit.
|
|
// Clear any previously set lock status
|
|
STORE2:
|
|
if (ack_i) begin
|
|
state <= IFETCH;
|
|
lock_o <= 1'b0;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'h0;
|
|
dat_o <= 32'h0;
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
dmiss <= `TRUE;
|
|
state <= WAIT_DHIT;
|
|
retstate <= IFETCH;
|
|
end
|
|
end
|
|
WAIT_DHIT:
|
|
if (dhit)
|
|
state <= retstate;
|
|
|
|
`include "byte_ix.v"
|
|
`include "byte_iy.v"
|
|
|
|
// Indirect and indirect X addressing mode eg. LDA ($12,x) : (zp)
|
|
IX1:
|
|
if (unCachedData) begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 4'hf;
|
|
adr_o <= {radr,2'b00};
|
|
state <= IX2;
|
|
end
|
|
else if (dhit) begin
|
|
radr <= rdat;
|
|
state <= IX3;
|
|
end
|
|
else
|
|
dmiss <= `TRUE;
|
|
IX2:
|
|
if (ack_i) begin
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'h0;
|
|
radr <= dat_i;
|
|
state <= IX3;
|
|
end
|
|
IX3:
|
|
if (ir[7:0]==`ST_IX || ir[7:0]==`ST_RIND) begin
|
|
wadr <= radr;
|
|
wdat <= rfoa;
|
|
state <= STORE1;
|
|
end
|
|
else if (unCachedData) begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 4'hf;
|
|
adr_o <= {radr,2'b00};
|
|
state <= IX4;
|
|
end
|
|
else if (dhit) begin
|
|
b <= rdat;
|
|
state <= CALC;
|
|
end
|
|
else
|
|
dmiss <= `TRUE;
|
|
IX4:
|
|
if (ack_i) begin
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'h0;
|
|
b <= dat_i;
|
|
state <= CALC;
|
|
end
|
|
|
|
|
|
// Indirect Y addressing mode eg. LDA ($12),y
|
|
IY1:
|
|
if (unCachedData) begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 4'hf;
|
|
adr_o <= {radr,2'b00};
|
|
state <= IY2;
|
|
end
|
|
else if (dhit) begin
|
|
radr <= rdat;
|
|
state <= IY3;
|
|
end
|
|
else
|
|
dmiss <= `TRUE;
|
|
IY2:
|
|
if (ack_i) begin
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'h0;
|
|
radr <= dat_i;
|
|
state <= IY3;
|
|
end
|
|
IY3:
|
|
begin
|
|
radr <= radr + y;
|
|
wadr <= radr + y;
|
|
wdat <= rfoa;
|
|
if (ir==`ST_IY)
|
|
state <= STORE1;
|
|
else
|
|
state <= LOAD1;
|
|
end
|
|
|
|
// Performs the data fetch for both eight bit and 32 bit modes
|
|
// Handle the following address modes: zp : zp,Rn : abs : abs,Rn
|
|
LOAD1:
|
|
if (unCachedData) begin
|
|
if (isRMW)
|
|
lock_o <= 1'b1;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 4'hf;
|
|
adr_o <= {radr,2'b00};
|
|
state <= LOAD2;
|
|
end
|
|
else if (dhit) begin
|
|
b8 <= rdat8;
|
|
b <= rdat;
|
|
state <= CALC;
|
|
end
|
|
else
|
|
dmiss <= `TRUE;
|
|
LOAD2:
|
|
if (ack_i) begin
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'd0;
|
|
b8 <= dati;
|
|
b <= dat_i;
|
|
state <= CALC;
|
|
end
|
|
|
|
`include "calc.v"
|
|
|
|
JSR1:
|
|
if (ack_i) begin
|
|
state <= IFETCH;
|
|
retstate <= IFETCH;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'd0;
|
|
dat_o <= 32'd0;
|
|
pc <= vect;
|
|
isp <= isp_dec;
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
|
end
|
|
|
|
`include "byte_jsr.v"
|
|
`include "byte_jsl.v"
|
|
|
|
JSR_INDX1:
|
|
if (ack_i) begin
|
|
state <= JMP_IND1;
|
|
retstate <= JMP_IND1;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'd0;
|
|
dat_o <= 32'd0;
|
|
radr <= ir[39:8] + x;
|
|
isp <= isp_dec;
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
dmiss <= `TRUE;
|
|
state <= WAIT_DHIT;
|
|
end
|
|
end
|
|
BYTE_JSR_INDX1:
|
|
if (ack_i) begin
|
|
state <= BYTE_JSR_INDX2;
|
|
retstate <= BYTE_JSR_INDX2;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
|
end
|
|
BYTE_JSR_INDX2:
|
|
begin
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
wdat <= {4{pcp2[7:0]}};
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{pcp2[7:0]}};
|
|
sp <= sp_dec;
|
|
state <= BYTE_JSR_INDX3;
|
|
end
|
|
BYTE_JSR_INDX3:
|
|
if (ack_i) begin
|
|
state <= BYTE_JMP_IND1;
|
|
retstate <= BYTE_JMP_IND1;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'd0;
|
|
dat_o <= 32'd0;
|
|
radr <= absx_address[15:2];
|
|
radr2LSB <= absx_address[1:0];
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
|
end
|
|
JSR161:
|
|
if (ack_i) begin
|
|
state <= IFETCH;
|
|
retstate <= IFETCH;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
pc <= {{16{ir[23]}},ir[23:8]};
|
|
isp <= isp_dec;
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
end
|
end
|
end
|
|
|
`include "byte_plp.v"
|
`include "byte_plp.v"
|
`include "byte_rts.v"
|
`include "byte_rts.v"
|
`include "byte_rti.v"
|
`include "byte_rti.v"
|
`include "rti.v"
|
`include "rti.v"
|
`include "rts.v"
|
`include "rts.v"
|
|
|
PHP1:
|
`include "php.v"
|
if (ack_i) begin
|
|
state <= IFETCH;
|
|
retstate <= IFETCH;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'd0;
|
|
dat_o <= 32'd0;
|
|
pc <= pc + 32'd1;
|
|
if (dhit) begin
|
|
wr <= 1'b1;
|
|
wrsel <= sel_o;
|
|
end
|
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
|
end
|
|
`include "plp.v"
|
`include "plp.v"
|
`include "pla.v"
|
`include "pla.v"
|
|
|
`include "byte_irq.v"
|
`include "byte_irq.v"
|
`include "byte_jmp_ind.v"
|
`include "byte_jmp_ind.v"
|
