| Line 30... |
Line 30... |
`define RST_VECT 34'h3FFFFFFF8
|
`define RST_VECT 34'h3FFFFFFF8
|
`define NMI_VECT 34'h3FFFFFFF4
|
`define NMI_VECT 34'h3FFFFFFF4
|
`define IRQ_VECT 34'h3FFFFFFF0
|
`define IRQ_VECT 34'h3FFFFFFF0
|
`define BRK_VECTNO 9'd0
|
`define BRK_VECTNO 9'd0
|
`define SLP_VECTNO 9'd1
|
`define SLP_VECTNO 9'd1
|
|
`define BYTE_RST_VECT 34'h00000FFFC
|
`define BYTE_NMI_VECT 34'h00000FFFA
|
`define BYTE_NMI_VECT 34'h00000FFFA
|
`define BYTE_IRQ_VECT 34'h00000FFFE
|
`define BYTE_IRQ_VECT 34'h00000FFFE
|
|
|
`define BRK 8'h00
|
`define BRK 8'h00
|
`define RTI 8'h40
|
`define RTI 8'h40
|
| Line 371... |
Line 372... |
`define TSB_ABS 8'h0C
|
`define TSB_ABS 8'h0C
|
|
|
`define BAZ 8'hC1
|
`define BAZ 8'hC1
|
`define BXZ 8'hD1
|
`define BXZ 8'hD1
|
`define BEQ_RR 8'hE2
|
`define BEQ_RR 8'hE2
|
|
`define INT0 8'hDC
|
|
`define INT1 8'hDD
|
|
|
|
`define NOTHING 4'd0
|
|
`define SR_70 4'd1
|
|
`define SR_310 4'd2
|
|
`define BYTE_70 4'd3
|
|
`define WORD_310 4'd4
|
|
`define PC_70 4'd5
|
|
`define PC_158 4'd6
|
|
`define PC_2316 4'd7
|
|
`define PC_3124 4'd8
|
|
`define PC_310 4'd9
|
|
`define WORD_311 4'd10
|
|
`define IA_310 4'd11
|
|
`define IA_70 4'd12
|
|
`define IA_158 4'd13
|
|
`define BYTE_71 4'd14
|
|
|
module icachemem(wclk, wr, adr, dat, rclk, pc, insn);
|
module icachemem(wclk, wr, adr, dat, rclk, pc, insn);
|
input wclk;
|
input wclk;
|
input wr;
|
input wr;
|
input [33:0] adr;
|
input [33:0] adr;
|
input [31:0] dat;
|
input [31:0] dat;
|
input rclk;
|
input rclk;
|
input [31:0] pc;
|
input [31:0] pc;
|
output reg [55:0] insn;
|
output reg [63:0] insn;
|
|
|
wire [63:0] insn0;
|
wire [63:0] insn0;
|
wire [63:0] insn1;
|
wire [63:0] insn1;
|
wire [31:0] pcp8 = pc + 32'd8;
|
wire [31:0] pcp8 = pc + 32'd8;
|
reg [31:0] rpc;
|
reg [31:0] rpc;
|
| Line 460... |
Line 479... |
.o(insn1[63:32])
|
.o(insn1[63:32])
|
);
|
);
|
|
|
always @(rpc or insn0 or insn1)
|
always @(rpc or insn0 or insn1)
|
case(rpc[2:0])
|
case(rpc[2:0])
|
3'd0: insn <= insn0[55:0];
|
3'd0: insn <= insn0[63:0];
|
3'd1: insn <= insn0[63:8];
|
3'd1: insn <= {insn1[7:0],insn0[63:8]};
|
3'd2: insn <= {insn1[7:0],insn0[63:16]};
|
3'd2: insn <= {insn1[15:0],insn0[63:16]};
|
3'd3: insn <= {insn1[15:0],insn0[63:24]};
|
3'd3: insn <= {insn1[23:0],insn0[63:24]};
|
3'd4: insn <= {insn1[23:0],insn0[63:32]};
|
3'd4: insn <= {insn1[31:0],insn0[63:32]};
|
3'd5: insn <= {insn1[31:0],insn0[63:40]};
|
3'd5: insn <= {insn1[39:0],insn0[63:40]};
|
3'd6: insn <= {insn1[39:0],insn0[63:48]};
|
3'd6: insn <= {insn1[47:0],insn0[63:48]};
|
3'd7: insn <= {insn1[47:0],insn0[63:56]};
|
3'd7: insn <= {insn1[55:0],insn0[63:56]};
|
endcase
|
endcase
|
endmodule
|
endmodule
|
|
|
module tagmem(wclk, wr, adr, rclk, pc, hit0, hit1);
|
module tagmem(wclk, wr, adr, rclk, pc, hit0, hit1);
|
input wclk;
|
input wclk;
|
| Line 611... |
Line 630... |
assign v = (op ^ s ^ b) & (~op ^ a ^ b);
|
assign v = (op ^ s ^ b) & (~op ^ a ^ b);
|
|
|
endmodule
|
endmodule
|
|
|
|
|
module rtf65002d(rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, we_o, sel_o, adr_o, dat_i, dat_o);
|
module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o);
|
parameter IDLE = 3'd0;
|
parameter IDLE = 3'd0;
|
parameter LOAD_DCACHE = 3'd1;
|
parameter LOAD_DCACHE = 3'd1;
|
parameter LOAD_ICACHE = 3'd2;
|
parameter LOAD_ICACHE = 3'd2;
|
parameter LOAD_IBUF1 = 3'd3;
|
parameter LOAD_IBUF1 = 3'd3;
|
parameter LOAD_IBUF2 = 3'd4;
|
parameter LOAD_IBUF2 = 3'd4;
|
| Line 721... |
Line 740... |
parameter RESET2 = 7'd100;
|
parameter RESET2 = 7'd100;
|
parameter MULDIV1 = 7'd101;
|
parameter MULDIV1 = 7'd101;
|
parameter MULDIV2 = 7'd102;
|
parameter MULDIV2 = 7'd102;
|
parameter BYTE_DECODE = 7'd103;
|
parameter BYTE_DECODE = 7'd103;
|
parameter BYTE_CALC = 7'd104;
|
parameter BYTE_CALC = 7'd104;
|
|
parameter BUS_ERROR = 7'd105;
|
|
parameter INSN_BUS_ERROR = 7'd106;
|
|
parameter LOAD_MAC1 = 7'd107;
|
|
parameter LOAD_MAC2 = 7'd108;
|
|
|
|
input rst_md; // reset mode, 1=emulation mode, 0=native mode
|
input rst_i;
|
input rst_i;
|
input clk_i;
|
input clk_i;
|
input nmi_i;
|
input nmi_i;
|
input irq_i;
|
input irq_i;
|
input [8:0] irq_vect;
|
input [8:0] irq_vect;
|
| Line 734... |
Line 758... |
output reg [5:0] bl_o;
|
output reg [5:0] bl_o;
|
output reg lock_o;
|
output reg lock_o;
|
output reg cyc_o;
|
output reg cyc_o;
|
output reg stb_o;
|
output reg stb_o;
|
input ack_i;
|
input ack_i;
|
|
input err_i;
|
output reg we_o;
|
output reg we_o;
|
output reg [3:0] sel_o;
|
output reg [3:0] sel_o;
|
output reg [33:0] adr_o;
|
output reg [33:0] adr_o;
|
input [31:0] dat_i;
|
input [31:0] dat_i;
|
output reg [31:0] dat_o;
|
output reg [31:0] dat_o;
|
|
|
reg [6:0] state;
|
reg [6:0] state;
|
reg [6:0] retstate;
|
reg [6:0] retstate;
|
reg [2:0] cstate;
|
reg [2:0] cstate;
|
wire [55:0] insn;
|
wire [63:0] insn;
|
reg [55:0] ibuf;
|
reg [63:0] ibuf;
|
reg [31:0] bufadr;
|
reg [31:0] bufadr;
|
|
|
reg cf,nf,zf,vf,bf,im,df,em;
|
reg cf,nf,zf,vf,bf,im,df,em;
|
reg em1;
|
reg em1;
|
reg gie;
|
reg gie;
|
| Line 783... |
Line 808... |
reg [31:0] dp8; // 8 bit mode direct page register
|
reg [31:0] dp8; // 8 bit mode direct page register
|
reg [31:0] abs8; // 8 bit mode absolute address register
|
reg [31:0] abs8; // 8 bit mode absolute address register
|
reg [31:0] vbr; // vector table base register
|
reg [31:0] vbr; // vector table base register
|
wire bhit=pc==bufadr;
|
wire bhit=pc==bufadr;
|
reg [31:0] regfile [15:0];
|
reg [31:0] regfile [15:0];
|
reg [55:0] ir;
|
reg [63:0] ir;
|
wire [3:0] Ra = ir[11:8];
|
wire [3:0] Ra = ir[11:8];
|
wire [3:0] Rb = ir[15:12];
|
wire [3:0] Rb = ir[15:12];
|
reg [31:0] rfoa;
|
reg [31:0] rfoa;
|
reg [31:0] rfob;
|
reg [31:0] rfob;
|
always @(Ra or x or y or acc)
|
always @(Ra or x or y or acc)
|
| Line 847... |
Line 872... |
wire [33:0] radr34p1 = radr34 + 34'd1;
|
wire [33:0] radr34p1 = radr34 + 34'd1;
|
reg [31:0] wadr;
|
reg [31:0] wadr;
|
reg [1:0] wadr2LSB;
|
reg [1:0] wadr2LSB;
|
reg [31:0] wdat;
|
reg [31:0] wdat;
|
wire [31:0] rdat;
|
wire [31:0] rdat;
|
|
reg [3:0] load_what;
|
|
reg [3:0] store_what;
|
reg imiss;
|
reg imiss;
|
reg dmiss;
|
reg dmiss;
|
reg icacheOn,dcacheOn;
|
reg icacheOn,dcacheOn;
|
wire unCachedData = radr[31:20]==12'hFFD || !dcacheOn; // I/O area is uncached
|
wire unCachedData = radr[31:20]==12'hFFD || !dcacheOn; // I/O area is uncached
|
wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn; // The lowest 8kB is uncached.
|
wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn; // The lowest 8kB is uncached.
|
| Line 875... |
Line 902... |
ir[7:0]==`TRB_ZP || ir[7:0]==`TRB_ZPX || ir[7:0]==`TRB_ABS || ir[7:0]==`TSB_ZP || ir[7:0]==`TSB_ZPX || ir[7:0]==`TSB_ABS;
|
ir[7:0]==`TRB_ZP || ir[7:0]==`TRB_ZPX || ir[7:0]==`TRB_ABS || ir[7:0]==`TSB_ZP || ir[7:0]==`TSB_ZPX || ir[7:0]==`TSB_ABS;
|
;
|
;
|
wire isRMW = em ? isRMW8 : isRMW32;
|
wire isRMW = em ? isRMW8 : isRMW32;
|
wire isOrb = ir[7:0]==`ORB_ZPX || ir[7:0]==`ORB_IX || ir[7:0]==`ORB_IY || ir[7:0]==`ORB_ABS || ir[7:0]==`ORB_ABSX;
|
wire isOrb = ir[7:0]==`ORB_ZPX || ir[7:0]==`ORB_IX || ir[7:0]==`ORB_IY || ir[7:0]==`ORB_ABS || ir[7:0]==`ORB_ABSX;
|
wire isStb = ir[7:0]==`STB_ZPX || ir[7:0]==`STB_ABS || ir[7:0]==`STB_ABSX;
|
wire isStb = ir[7:0]==`STB_ZPX || ir[7:0]==`STB_ABS || ir[7:0]==`STB_ABSX;
|
|
wire isRTI = ir[7:0]==`RTI;
|
|
wire isRTL = ir[7:0]==`RTL;
|
|
wire isRTS = ir[7:0]==`RTS;
|
wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
|
wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
|
wire md_done;
|
wire md_done;
|
wire clk;
|
wire clk;
|
|
reg isIY;
|
|
|
mult_div umd1
|
mult_div umd1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
| Line 1047... |
Line 1077... |
dat_o <= 32'd0;
|
dat_o <= 32'd0;
|
nmi_edge <= 1'b0;
|
nmi_edge <= 1'b0;
|
wai <= 1'b0;
|
wai <= 1'b0;
|
first_ifetch <= `TRUE;
|
first_ifetch <= `TRUE;
|
wr <= 1'b0;
|
wr <= 1'b0;
|
em <= 1'b0;
|
|
cf <= 1'b0;
|
cf <= 1'b0;
|
ir <= 56'hEAEAEAEAEAEAEA;
|
ir <= 56'hEAEAEAEAEAEAEA;
|
imiss <= `FALSE;
|
imiss <= `FALSE;
|
dmiss <= `FALSE;
|
dmiss <= `FALSE;
|
dcacheOn <= 1'b0;
|
dcacheOn <= 1'b0;
|
icacheOn <= 1'b1;
|
icacheOn <= 1'b1;
|
write_allocate <= 1'b0;
|
write_allocate <= 1'b0;
|
nmoi <= 1'b1;
|
nmoi <= 1'b1;
|
state <= RESET1;
|
state <= RESET1;
|
cstate <= IDLE;
|
cstate <= IDLE;
|
|
if (rst_md) begin
|
|
pc <= 32'h0000FFF0; // set high-order pc to zero
|
|
vect <= `BYTE_RST_VECT;
|
|
em <= 1'b1;
|
|
end
|
|
else begin
|
vect <= `RST_VECT;
|
vect <= `RST_VECT;
|
|
em <= 1'b0;
|
pc <= 32'hFFFFFFF0;
|
pc <= 32'hFFFFFFF0;
|
|
end
|
spage <= 32'h00000100;
|
spage <= 32'h00000100;
|
bufadr <= 32'd0;
|
bufadr <= 32'd0;
|
dp <= 32'd0;
|
dp <= 32'd0;
|
dp8 <= 32'd0;
|
dp8 <= 32'd0;
|
abs8 <= 32'd0;
|
abs8 <= 32'd0;
|
clk_en <= 1'b1;
|
clk_en <= 1'b1;
|
isCacheReset <= `TRUE;
|
isCacheReset <= `TRUE;
|
gie <= 1'b0;
|
gie <= 1'b0;
|
tick <= 32'd0;
|
tick <= 32'd0;
|
|
isIY <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
tick <= tick + 32'd1;
|
tick <= tick + 32'd1;
|
wr <= 1'b0;
|
wr <= 1'b0;
|
if (nmi_i & !nmi1)
|
if (nmi_i & !nmi1)
|
| Line 1088... |
Line 1126... |
isCacheReset <= `FALSE;
|
isCacheReset <= `FALSE;
|
end
|
end
|
end
|
end
|
RESET2:
|
RESET2:
|
begin
|
begin
|
vect <= `RST_VECT;
|
|
radr <= vect[31:2];
|
radr <= vect[31:2];
|
state <= JMP_IND1;
|
radr2LSB <= vect[1:0];
|
|
load_what <= em ? `PC_70 : `PC_310;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
|
|
`include "ifetch.v"
|
`include "ifetch.v"
|
`include "decode.v"
|
`include "decode.v"
|
`include "byte_decode.v"
|
`include "byte_decode.v"
|
|
|
`include "load.v"
|
`include "load_mac.v"
|
`include "store.v"
|
`include "store.v"
|
|
|
WAIT_DHIT:
|
WAIT_DHIT:
|
if (dhit)
|
if (dhit)
|
state <= retstate;
|
state <= retstate;
|
|
|
`include "byte_ix.v"
|
|
`include "byte_iy.v"
|
|
|
|
// Indirect and indirect X addressing mode eg. LDA ($12,x) : (zp)
|
|
IX1:
|
|
if (unCachedData) begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 4'hf;
|
|
adr_o <= {radr,2'b00};
|
|
state <= IX2;
|
|
end
|
|
else if (dhit) begin
|
|
radr <= rdat;
|
|
wadr <= rdat;
|
|
wdat <= a;
|
|
if (ir[7:0]==`ST_IX)
|
|
state <= STORE1;
|
|
else
|
|
state <= LOAD1;
|
|
end
|
|
else
|
|
dmiss <= `TRUE;
|
|
IX2:
|
|
if (ack_i) begin
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'h0;
|
|
radr <= dat_i;
|
|
wadr <= dat_i; // for stores
|
|
wdat <= a;
|
|
if (ir[7:0]==`ST_IX)
|
|
state <= STORE1;
|
|
else
|
|
state <= LOAD1;
|
|
end
|
|
|
|
|
|
// Indirect Y addressing mode eg. LDA ($12),y
|
|
IY1:
|
|
if (unCachedData) begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 4'hf;
|
|
adr_o <= {radr,2'b00};
|
|
state <= IY2;
|
|
end
|
|
else if (dhit) begin
|
|
radr <= rdat;
|
|
state <= IY3;
|
|
end
|
|
else
|
|
dmiss <= `TRUE;
|
|
IY2:
|
|
if (ack_i) begin
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'h0;
|
|
radr <= dat_i;
|
|
state <= IY3;
|
|
end
|
|
IY3:
|
|
begin
|
|
radr <= radr + y;
|
|
wadr <= radr + y;
|
|
wdat <= a;
|
|
if (ir[7:0]==`ST_IY)
|
|
state <= STORE1;
|
|
else
|
|
state <= LOAD1;
|
|
end
|
|
|
|
`include "byte_calc.v"
|
`include "byte_calc.v"
|
`include "calc.v"
|
`include "calc.v"
|
`include "byte_jsr.v"
|
`include "byte_jsr.v"
|
`include "byte_jsl.v"
|
`include "byte_jsl.v"
|
|
|
| Line 1207... |
Line 1172... |
end
|
end
|
end
|
end
|
|
|
JSR_INDX1:
|
JSR_INDX1:
|
if (ack_i) begin
|
if (ack_i) begin
|
state <= JMP_IND1;
|
load_what <= `PC_310;
|
retstate <= JMP_IND1;
|
state <= LOAD_MAC1;
|
|
retstate <= LOAD_MAC1;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
adr_o <= 34'd0;
|
adr_o <= 34'd0;
|
| Line 1247... |
Line 1213... |
state <= WAIT_DHIT;
|
state <= WAIT_DHIT;
|
dmiss <= `TRUE;
|
dmiss <= `TRUE;
|
end
|
end
|
end
|
end
|
|
|
`include "byte_plp.v"
|
|
`include "byte_rts.v"
|
|
`include "byte_rti.v"
|
|
`include "rti.v"
|
|
`include "rts.v"
|
|
|
|
`include "php.v"
|
`include "php.v"
|
`include "plp.v"
|
|
`include "pla.v"
|
|
|
|
`include "byte_irq.v"
|
`include "byte_irq.v"
|
`include "byte_jmp_ind.v"
|
|
|
|
IRQ1:
|
IRQ1:
|
if (ack_i) begin
|
if (ack_i) begin
|
|
ir <= 64'd0; // Force instruction decoder to BRK
|
state <= IRQ2;
|
state <= IRQ2;
|
retstate <= IRQ2;
|
retstate <= IRQ2;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
| Line 1293... |
Line 1250... |
dat_o <= sr;
|
dat_o <= sr;
|
state <= IRQ3;
|
state <= IRQ3;
|
end
|
end
|
IRQ3:
|
IRQ3:
|
if (ack_i) begin
|
if (ack_i) begin
|
state <= JMP_IND1;
|
load_what <= `PC_310;
|
retstate <= JMP_IND1;
|
state <= LOAD_MAC1;
|
|
retstate <= LOAD_MAC1;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
sel_o <= 4'h0;
|
sel_o <= 4'h0;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
| Line 1313... |
Line 1271... |
radr <= vect[31:2];
|
radr <= vect[31:2];
|
if (!bf)
|
if (!bf)
|
im <= 1'b1;
|
im <= 1'b1;
|
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
|
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
|
end
|
end
|
JMP_IND1:
|
|
if (unCachedData) begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {radr,2'b00};
|
|
state <= JMP_IND2;
|
|
end
|
|
else if (dhit) begin
|
|
pc <= rdat;
|
|
state <= IFETCH;
|
|
end
|
|
else
|
|
dmiss <= `TRUE;
|
|
JMP_IND2:
|
|
if (ack_i) begin
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'd0;
|
|
pc <= dat_i;
|
|
state <= IFETCH;
|
|
end
|
|
MULDIV1:
|
MULDIV1:
|
state <= MULDIV2;
|
state <= MULDIV2;
|
MULDIV2:
|
MULDIV2:
|
if (md_done) begin
|
if (md_done) begin
|
state <= IFETCH;
|
state <= IFETCH;
|
| Line 1351... |
Line 1287... |
`MOD_RR: begin res <= r; end
|
`MOD_RR: begin res <= r; end
|
`MODS_RR: begin res <= r; end
|
`MODS_RR: begin res <= r; end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
BUS_ERROR:
|
|
begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= pc;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= pc;
|
|
vect <= {vbr[31:9],9'd508,2'b00};
|
|
state <= IRQ1;
|
|
end
|
|
INSN_BUS_ERROR:
|
|
begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= pc;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= pc;
|
|
vect <= {vbr[31:9],9'd509,2'b00};
|
|
state <= IRQ1;
|
|
end
|
|
|
endcase
|
endcase
|
|
|
`include "cache_controller.v"
|
`include "cache_controller.v"
|
|
|
end
|
end
|
