| Line 98... |
Line 98... |
`define ADD_IX 8'h61
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`define ADD_IX 8'h61
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`define ADD_IY 8'h71
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`define ADD_IY 8'h71
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`define ADD_ABS 8'h6D
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`define ADD_ABS 8'h6D
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`define ADD_ABSX 8'h7D
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`define ADD_ABSX 8'h7D
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`define ADD_RIND 8'h72
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`define ADD_RIND 8'h72
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`define ADD_DSP 8'h63
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`define SUB_IMM8 8'hE5
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`define SUB_IMM8 8'hE5
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`define SUB_IMM16 8'hF9
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`define SUB_IMM16 8'hF9
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`define SUB_IMM32 8'hE9
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`define SUB_IMM32 8'hE9
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`define SUB_ZPX 8'hF5
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`define SUB_ZPX 8'hF5
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`define SUB_IX 8'hE1
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`define SUB_IX 8'hE1
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`define SUB_IY 8'hF1
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`define SUB_IY 8'hF1
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`define SUB_ABS 8'hED
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`define SUB_ABS 8'hED
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`define SUB_ABSX 8'hFD
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`define SUB_ABSX 8'hFD
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`define SUB_RIND 8'hF2
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`define SUB_RIND 8'hF2
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`define SUB_DSP 8'hE3
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// CMP = SUB r0,....
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// CMP = SUB r0,....
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`define ADC_IMM 8'h69
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`define ADC_IMM 8'h69
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`define ADC_ZP 8'h65
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`define ADC_ZP 8'h65
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| Line 161... |
Line 163... |
`define AND_ABS 8'h2D
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`define AND_ABS 8'h2D
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`define AND_ABSX 8'h3D
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`define AND_ABSX 8'h3D
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`define AND_ABSY 8'h39
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`define AND_ABSY 8'h39
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`define AND_RIND 8'h32
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`define AND_RIND 8'h32
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`define AND_I 8'h32
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`define AND_I 8'h32
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`define AND_DSP 8'h23
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`define OR_IMM8 8'h05
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`define OR_IMM8 8'h05
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`define OR_IMM16 8'h19
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`define OR_IMM16 8'h19
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`define OR_IMM32 8'h09
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`define OR_IMM32 8'h09
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`define OR_ZPX 8'h15
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`define OR_ZPX 8'h15
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`define OR_IX 8'h01
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`define OR_IX 8'h01
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`define OR_IY 8'h11
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`define OR_IY 8'h11
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`define OR_ABS 8'h0D
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`define OR_ABS 8'h0D
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`define OR_ABSX 8'h1D
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`define OR_ABSX 8'h1D
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`define OR_RIND 8'h12
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`define OR_RIND 8'h12
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`define OR_DSP 8'h03
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`define ORA_IMM 8'h09
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`define ORA_IMM 8'h09
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`define ORA_ZP 8'h05
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`define ORA_ZP 8'h05
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`define ORA_ZPX 8'h15
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`define ORA_ZPX 8'h15
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`define ORA_IX 8'h01
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`define ORA_IX 8'h01
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| Line 195... |
Line 199... |
`define EOR_ABS 8'h4D
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`define EOR_ABS 8'h4D
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`define EOR_ABSX 8'h5D
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`define EOR_ABSX 8'h5D
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`define EOR_ABSY 8'h59
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`define EOR_ABSY 8'h59
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`define EOR_RIND 8'h52
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`define EOR_RIND 8'h52
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`define EOR_I 8'h52
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`define EOR_I 8'h52
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`define EOR_DSP 8'h43
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// LD is OR rt,r0,....
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// LD is OR rt,r0,....
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`define ST_ZPX 8'h95
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`define ST_ZPX 8'h95
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`define ST_IX 8'h81
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`define ST_IX 8'h81
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`define ST_IY 8'h91
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`define ST_IY 8'h91
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`define ST_ABS 8'h8D
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`define ST_ABS 8'h8D
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`define ST_ABSX 8'h9D
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`define ST_ABSX 8'h9D
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`define ST_RIND 8'h92
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`define ST_RIND 8'h92
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`define ST_DSP 8'h83
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`define ORB_ZPX 8'hB5
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`define ORB_ZPX 8'hB5
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`define ORB_IX 8'hA1
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`define ORB_IX 8'hA1
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`define ORB_IY 8'hB1
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`define ORB_IY 8'hB1
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`define ORB_ABS 8'hAD
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`define ORB_ABS 8'hAD
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| Line 374... |
Line 380... |
`define BAZ 8'hC1
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`define BAZ 8'hC1
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`define BXZ 8'hD1
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`define BXZ 8'hD1
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`define BEQ_RR 8'hE2
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`define BEQ_RR 8'hE2
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`define INT0 8'hDC
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`define INT0 8'hDC
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`define INT1 8'hDD
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`define INT1 8'hDD
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`define SUB_SP 8'h4B
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`define MVP 8'h44
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`define MVN 8'h54
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`define NOTHING 4'd0
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`define NOTHING 4'd0
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`define SR_70 4'd1
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`define SR_70 4'd1
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`define SR_310 4'd2
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`define SR_310 4'd2
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`define BYTE_70 4'd3
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`define BYTE_70 4'd3
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| Line 390... |
Line 399... |
`define WORD_311 4'd10
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`define WORD_311 4'd10
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`define IA_310 4'd11
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`define IA_310 4'd11
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`define IA_70 4'd12
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`define IA_70 4'd12
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`define IA_158 4'd13
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`define IA_158 4'd13
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`define BYTE_71 4'd14
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`define BYTE_71 4'd14
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`define WORD_312 4'd15
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module icachemem(wclk, wr, adr, dat, rclk, pc, insn);
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module icachemem(wclk, wr, adr, dat, rclk, pc, insn);
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input wclk;
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input wclk;
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input wr;
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input wr;
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input [33:0] adr;
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input [33:0] adr;
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| Line 744... |
Line 754... |
parameter BYTE_CALC = 7'd104;
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parameter BYTE_CALC = 7'd104;
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parameter BUS_ERROR = 7'd105;
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parameter BUS_ERROR = 7'd105;
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parameter INSN_BUS_ERROR = 7'd106;
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parameter INSN_BUS_ERROR = 7'd106;
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parameter LOAD_MAC1 = 7'd107;
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parameter LOAD_MAC1 = 7'd107;
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parameter LOAD_MAC2 = 7'd108;
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parameter LOAD_MAC2 = 7'd108;
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parameter MVN1 = 7'd109;
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parameter MVN2 = 7'd110;
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parameter MVN3 = 7'd111;
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parameter MVP1 = 7'd112;
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parameter MVP2 = 7'd113;
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input rst_md; // reset mode, 1=emulation mode, 0=native mode
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input rst_md; // reset mode, 1=emulation mode, 0=native mode
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input rst_i;
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input rst_i;
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input clk_i;
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input clk_i;
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input nmi_i;
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input nmi_i;
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| Line 797... |
Line 812... |
wire [7:0] sp_dec = sp - 8'd1;
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wire [7:0] sp_dec = sp - 8'd1;
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wire [7:0] sp_inc = sp + 8'd1;
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wire [7:0] sp_inc = sp + 8'd1;
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wire [31:0] isp_dec = isp - 32'd1;
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wire [31:0] isp_dec = isp - 32'd1;
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wire [31:0] isp_inc = isp + 32'd1;
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wire [31:0] isp_inc = isp + 32'd1;
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reg [31:0] pc;
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reg [31:0] pc;
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reg [31:0] opc;
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wire [31:0] pcp1 = pc + 32'd1;
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wire [31:0] pcp1 = pc + 32'd1;
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wire [31:0] pcp2 = pc + 32'd2;
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wire [31:0] pcp2 = pc + 32'd2;
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wire [31:0] pcp3 = pc + 32'd3;
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wire [31:0] pcp3 = pc + 32'd3;
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wire [31:0] pcp4 = pc + 32'd4;
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wire [31:0] pcp4 = pc + 32'd4;
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wire [31:0] pcp8 = pc + 32'd8;
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wire [31:0] pcp8 = pc + 32'd8;
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| Line 874... |
Line 890... |
reg [1:0] wadr2LSB;
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reg [1:0] wadr2LSB;
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reg [31:0] wdat;
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reg [31:0] wdat;
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wire [31:0] rdat;
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wire [31:0] rdat;
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reg [3:0] load_what;
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reg [3:0] load_what;
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reg [3:0] store_what;
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reg [3:0] store_what;
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reg [31:0] derr_address;
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reg imiss;
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reg imiss;
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reg dmiss;
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reg dmiss;
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reg icacheOn,dcacheOn;
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reg icacheOn,dcacheOn;
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wire unCachedData = radr[31:20]==12'hFFD || !dcacheOn; // I/O area is uncached
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wire unCachedData = radr[31:20]==12'hFFD || !dcacheOn; // I/O area is uncached
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wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn; // The lowest 8kB is uncached.
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wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn; // The lowest 8kB is uncached.
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| Line 905... |
Line 922... |
wire isOrb = ir[7:0]==`ORB_ZPX || ir[7:0]==`ORB_IX || ir[7:0]==`ORB_IY || ir[7:0]==`ORB_ABS || ir[7:0]==`ORB_ABSX;
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wire isOrb = ir[7:0]==`ORB_ZPX || ir[7:0]==`ORB_IX || ir[7:0]==`ORB_IY || ir[7:0]==`ORB_ABS || ir[7:0]==`ORB_ABSX;
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wire isStb = ir[7:0]==`STB_ZPX || ir[7:0]==`STB_ABS || ir[7:0]==`STB_ABSX;
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wire isStb = ir[7:0]==`STB_ZPX || ir[7:0]==`STB_ABS || ir[7:0]==`STB_ABSX;
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wire isRTI = ir[7:0]==`RTI;
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wire isRTI = ir[7:0]==`RTI;
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wire isRTL = ir[7:0]==`RTL;
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wire isRTL = ir[7:0]==`RTL;
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wire isRTS = ir[7:0]==`RTS;
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wire isRTS = ir[7:0]==`RTS;
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wire isMove = ir[7:0]==`MVP || ir[7:0]==`MVN;
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wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
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wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
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wire md_done;
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wire md_done;
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wire clk;
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wire clk;
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reg isIY;
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reg isIY;
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| Line 1291... |
Line 1309... |
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BUS_ERROR:
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BUS_ERROR:
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begin
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begin
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radr <= isp_dec;
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radr <= isp_dec;
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wadr <= isp_dec;
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wadr <= isp_dec;
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wdat <= pc;
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wdat <= opc;
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if (em | isOrb | isStb)
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derr_address <= adr_o[31:0];
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else
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derr_address <= adr_o[33:2];
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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we_o <= 1'b1;
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we_o <= 1'b1;
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sel_o <= 4'hF;
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sel_o <= 4'hF;
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adr_o <= {isp_dec,2'b00};
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adr_o <= {isp_dec,2'b00};
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dat_o <= pc;
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dat_o <= opc;
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vect <= {vbr[31:9],9'd508,2'b00};
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vect <= {vbr[31:9],9'd508,2'b00};
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state <= IRQ1;
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state <= IRQ1;
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end
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end
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INSN_BUS_ERROR:
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INSN_BUS_ERROR:
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begin
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begin
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radr <= isp_dec;
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radr <= isp_dec;
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wadr <= isp_dec;
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wadr <= isp_dec;
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wdat <= pc;
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wdat <= opc;
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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we_o <= 1'b1;
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we_o <= 1'b1;
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sel_o <= 4'hF;
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sel_o <= 4'hF;
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adr_o <= {isp_dec,2'b00};
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adr_o <= {isp_dec,2'b00};
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dat_o <= pc;
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dat_o <= opc;
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vect <= {vbr[31:9],9'd509,2'b00};
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vect <= {vbr[31:9],9'd509,2'b00};
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state <= IRQ1;
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state <= IRQ1;
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end
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end
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|
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MVN1:
|
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begin
|
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radr <= x;
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x <= x + 32'd1;
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retstate <= MVN2;
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load_what <= `WORD_312;
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state <= LOAD_MAC1;
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end
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MVN2:
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begin
|
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wadr <= y;
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wdat <= b;
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y <= y + 32'd1;
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acc <= acc - 32'd1;
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state <= STORE1;
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end
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MVN3:
|
|
begin
|
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state <= IFETCH;
|
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if (acc==32'hFFFFFFFF)
|
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pc <= pc + 32'd1;
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end
|
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MVP1:
|
|
begin
|
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radr <= x;
|
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x <= x - 32'd1;
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retstate <= MVP2;
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load_what <= `WORD_312;
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state <= LOAD_MAC1;
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end
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MVP2:
|
|
begin
|
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wadr <= y;
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wdat <= b;
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y <= y - 32'd1;
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acc <= acc - 32'd1;
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state <= STORE1;
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end
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|
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endcase
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endcase
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|
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`include "cache_controller.v"
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`include "cache_controller.v"
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|
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end
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end
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