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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002d.v] - Diff between revs 32 and 35

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Line 24... Line 24... 
//                                                                          
//                                                                          
// ============================================================================
 
// ============================================================================
 
//
 
//
 
`include "rtf65002_defines.v"
 
`include "rtf65002_defines.v"
 
 
 
 
 
module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o, km_o);
 
module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, rty_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o, km_o);
 
parameter RESET1 = 6'd0;
 
parameter RESET1 = 6'd0;
 
parameter IFETCH = 6'd1;
 
parameter IFETCH = 6'd1;
 
parameter DECODE = 6'd2;
 
parameter DECODE = 6'd2;
 
parameter STORE1 = 6'd3;
 
parameter STORE1 = 6'd3;
 
parameter STORE2 = 6'd4;
 
parameter STORE2 = 6'd4;
Line 44... Line 44... 
parameter MULDIV1 = 6'd14;
 
parameter MULDIV1 = 6'd14;
 
parameter MULDIV2 = 6'd15;
 
parameter MULDIV2 = 6'd15;
 
parameter BYTE_DECODE = 6'd16;
 
parameter BYTE_DECODE = 6'd16;
 
parameter BYTE_CALC = 6'd17;
 
parameter BYTE_CALC = 6'd17;
 
parameter BUS_ERROR = 6'd18;
 
parameter BUS_ERROR = 6'd18;
 
parameter INSN_BUS_ERROR = 6'd19;
 
parameter LOAD_MAC1 = 6'd19;
 
parameter LOAD_MAC1 = 6'd20;
 
parameter LOAD_MAC2 = 6'd20;
 
parameter LOAD_MAC2 = 6'd21;
 
parameter LOAD_MAC3 = 6'd21;
 
parameter LOAD_MAC3 = 6'd22;
 
parameter MVN3 = 6'd22;
 
parameter MVN3 = 6'd23;
 
parameter PUSHA1 = 6'd23;
 
parameter PUSHA1 = 6'd24;
 
parameter POPA1 = 6'd24;
 
parameter POPA1 = 6'd25;
 
parameter BYTE_IFETCH = 6'd25;
 
parameter BYTE_IFETCH = 6'd26;
 
parameter LOAD_DCACHE = 6'd26;
 
parameter LOAD_DCACHE = 6'd27;
 
parameter LOAD_ICACHE = 6'd27;
 
parameter LOAD_ICACHE = 6'd28;
 
parameter LOAD_IBUF1 = 6'd28;
 
parameter LOAD_IBUF1 = 6'd29;
 
parameter LOAD_IBUF2 = 6'd29;
 
parameter LOAD_IBUF2 = 6'd30;
 
parameter LOAD_IBUF3 = 6'd30;
 
parameter LOAD_IBUF3 = 6'd31;
 
parameter ICACHE1 = 6'd31;
 
parameter ICACHE1 = 6'd32;
 
parameter IBUF1 = 6'd32;
 
parameter IBUF1 = 6'd33;
 
parameter DCACHE1 = 6'd33;
 
parameter DCACHE1 = 6'd34;
 
parameter CMPS1 = 6'd34;
 
parameter CMPS1 = 6'd35;
 
 
 
 
 
 
 
input rst_md;           // reset mode, 1=emulation mode, 0=native mode
 
input rst_md;           // reset mode, 1=emulation mode, 0=native mode
 
input rst_i;
 
input rst_i;
 
input clk_i;
 
input clk_i;
 
input nmi_i;
 
input nmi_i;
Line 75... Line 74... 
output reg [5:0] bl_o;
 
output reg [5:0] bl_o;
 
output reg lock_o;
 
output reg lock_o;
 
output reg cyc_o;
 
output reg cyc_o;
 
output reg stb_o;
 
output reg stb_o;
 
input ack_i;
 
input ack_i;
 
 
 
input rty_i;
 
input err_i;
 
input err_i;
 
output reg we_o;
 
output reg we_o;
 
output reg [3:0] sel_o;
 
output reg [3:0] sel_o;
 
output reg [33:0] adr_o;
 
output reg [33:0] adr_o;
 
input [31:0] dat_i;
 
input [31:0] dat_i;
Line 91... Line 91... 
wire [63:0] insn;
 
wire [63:0] insn;
 
reg [63:0] ibuf;
 
reg [63:0] ibuf;
 
reg [31:0] bufadr;
 
reg [31:0] bufadr;
 
reg [63:0] exbuf;
 
reg [63:0] exbuf;
 
 
 
 
 
 
 
integer n;
 
reg cf,nf,zf,vf,bf,im,df,em;
 
reg cf,nf,zf,vf,bf,im,df,em;
 
reg tf;         // trace mode flag
 
reg tf;         // trace mode flag
 
reg ttrig;      // trace trigger
 
reg ttrig;      // trace trigger
 
reg em1;
 
reg em1;
 
reg gie;        // global interrupt enable (set when sp is loaded)
 
reg gie;        // global interrupt enable (set when sp is loaded)
Line 111... Line 112... 
reg [31:0] spage;        // stack page
 
reg [31:0] spage;        // stack page
 
wire [7:0] acc8 = acc[7:0];
 
wire [7:0] acc8 = acc[7:0];
 
wire [7:0] x8 = x[7:0];
 
wire [7:0] x8 = x[7:0];
 
wire [7:0] y8 = y[7:0];
 
wire [7:0] y8 = y[7:0];
 
reg [31:0] isp;          // interrupt stack pointer
 
reg [31:0] isp;          // interrupt stack pointer
 
 
 
reg [31:0] oisp; // original isp for bus retry
 
wire [63:0] prod;
 
wire [63:0] prod;
 
wire [31:0] q,r;
 
wire [31:0] q,r;
 
reg [31:0] tick;
 
reg [31:0] tick;
 
wire [7:0] sp_dec = sp - 8'd1;
 
wire [7:0] sp_dec = sp - 8'd1;
 
wire [7:0] sp_inc = sp + 8'd1;
 
wire [7:0] sp_inc = sp + 8'd1;
 
wire [31:0] isp_dec = isp - 32'd1;
 
wire [31:0] isp_dec = isp - 32'd1;
 
wire [31:0] isp_inc = isp + 32'd1;
 
wire [31:0] isp_inc = isp + 32'd1;
 
reg [3:0] suppress_pcinc;
 
reg [3:0] suppress_pcinc;
 
reg [31:0] pc;
 
reg [31:0] pc;
 
reg [31:0] opc;
 
reg [31:0] opc;
 
wire [3:0] pc_inc,pc_inc8;
 
wire [3:0] pc_inc;
 
 
 
wire [3:0] pc_inc8;
 
wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc);        // for branches
 
wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc);        // for branches
 
wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc);        // for branches
 
wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc);        // for branches
 
wire [31:0] pcp8 = pc + 32'd8;                                           // cache controller needs this
 
wire [31:0] pcp8 = pc + 32'd8;                                           // cache controller needs this
 
reg [31:0] abs8; // 8 bit mode absolute address register
 
reg [31:0] abs8; // 8 bit mode absolute address register
 
reg [31:0] vbr;          // vector table base register
 
reg [31:0] vbr;          // vector table base register
 
wire bhit=pc==bufadr;
 
wire bhit=pc==bufadr;
 
 
 
reg [2:0] bcnt;          // burst count for cache controller
 
reg [31:0] regfile [15:0];
 
reg [31:0] regfile [15:0];
 
reg [63:0] ir;
 
reg [63:0] ir;
 
reg pg2;
 
reg pg2;
 
wire [8:0] ir9 = {pg2,ir[7:0]};
 
wire [8:0] ir9 = {pg2,ir[7:0]};
 
wire [3:0] Ra = ir[11:8];
 
wire [3:0] Ra = ir[11:8];
Line 177... Line 181... 
wire resz8 = res8[7:0]==8'h00;
 
wire resz8 = res8[7:0]==8'h00;
 
wire resz32 = res[31:0]==32'd0;
 
wire resz32 = res[31:0]==32'd0;
 
wire resn8 = res8[7];
 
wire resn8 = res8[7];
 
wire resn32 = res[31];
 
wire resn32 = res[31];
 
 
 
 
 
reg [31:0] vect;
 
reg [33:0] vect;
 
reg [31:0] ia;                   // temporary reg to hold indirect address
 
reg [31:0] ia;                   // temporary reg to hold indirect address
 
reg isInsnCacheLoad;
 
reg isInsnCacheLoad;
 
reg isDataCacheLoad;
 
reg isDataCacheLoad;
 
reg isCacheReset;
 
reg isCacheReset;
 
wire hit0,hit1;
 
wire hit0,hit1;
Line 201... Line 205... 
reg [1:0] wadr2LSB;
 
reg [1:0] wadr2LSB;
 
reg [31:0] wdat;
 
reg [31:0] wdat;
 
wire [31:0] rdat;
 
wire [31:0] rdat;
 
reg [4:0] load_what;
 
reg [4:0] load_what;
 
reg [5:0] store_what;
 
reg [5:0] store_what;
 
 
 
reg [8:0] intno;                 // interrupt number to take
 
reg [31:0] derr_address;
 
reg [31:0] derr_address;
 
reg imiss;
 
reg imiss;
 
reg dmiss;
 
reg dmiss;
 
reg icacheOn,dcacheOn;
 
reg icacheOn,dcacheOn;
 
`ifdef SUPPORT_DCACHE
 
`ifdef SUPPORT_DCACHE
Line 222... Line 227... 
wire clfsr_fb;
 
wire clfsr_fb;
 
xnor(clfsr_fb,clfsr[0],clfsr[1],clfsr[21],clfsr[31]);
 
xnor(clfsr_fb,clfsr[0],clfsr[1],clfsr[21],clfsr[31]);
 
wire [1:0] whichrd;
 
wire [1:0] whichrd;
 
wire whichwr=clfsr[0];
 
wire whichwr=clfsr[0];
 
`endif
 
`endif
 
 
 
reg [31:0] ilfsr;
 
 
 
wire ilfsr_fb;
 
 
 
xnor(ilfsr_fb,ilfsr[0],ilfsr[1],ilfsr[21],ilfsr[31]);
 
reg km;                 // kernel mode indicator
 
reg km;                 // kernel mode indicator
 
assign km_o = km;
 
assign km_o = km;
 
 
 
 
 
 
 
`ifdef DEBUG
 
reg [31:0] history_buf [127:0];
 
reg [31:0] history_buf [127:0];
 
reg [6:0] history_ndx;
 
reg [6:0] history_ndx;
 
reg hist_capture;
 
reg hist_capture;
 
 
 
`endif
 
 
 
 
 
reg isBusErr;
 
reg isBusErr;
 
reg isBrk,isMove,isSts;
 
reg isBrk,isMove,isSts;
 
reg isRTI,isRTL,isRTS;
 
reg isRTI,isRTL,isRTS;
 
reg isOrb,isStb;
 
reg isOrb,isStb;
Line 279... Line 289... 
                isBrk <= ir9==`BRK;
 
                isBrk <= ir9==`BRK;
 
                isMove <= ir9==`MVP || ir9==`MVN;
 
                isMove <= ir9==`MVP || ir9==`MVN;
 
                isSts <= ir9==`STS;
 
                isSts <= ir9==`STS;
 
                isJsrIndx <= ir9==`JSR_INDX;
 
                isJsrIndx <= ir9==`JSR_INDX;
 
                isJsrInd <= ir9==`JSR_IND;
 
                isJsrInd <= ir9==`JSR_IND;
 
                ldMuldiv <= ir9==`MUL_IMM8 || ir9==`DIV_IMM8 || ir9==`MOD_IMM8 || (ir9==`RR && (
 
                ldMuldiv <= ir9==`MUL_IMM8 || ir9==`MUL_IMM16 || ir9==`MUL_IMM32 ||
 
 
 
                        ir9==`DIV_IMM8 || ir9==`MOD_IMM8 || ir9==`DIV_IMM16 || ir9==`DIV_IMM32 || ir9==`MOD_IMM16 || ir9==`MOD_IMM32 ||
 
 
 
                        (ir9==`RR && (
 
                        ir[23:20]==`MUL_RR || ir[23:20]==`MULS_RR || ir[23:20]==`DIV_RR || ir[23:20]==`DIVS_RR || ir[23:20]==`MOD_RR || ir[23:20]==`MODS_RR));
 
                        ir[23:20]==`MUL_RR || ir[23:20]==`MULS_RR || ir[23:20]==`DIV_RR || ir[23:20]==`DIVS_RR || ir[23:20]==`MOD_RR || ir[23:20]==`MODS_RR));
 
                isPusha <= ir9==`PUSHA;
 
                isPusha <= ir9==`PUSHA;
 
                isPopa <= ir9==`POPA;
 
                isPopa <= ir9==`POPA;
 
        end
 
        end
 
        else
 
        else
Line 367... Line 379... 
);
 
);
 
 
 
 
 
rtf65002_itagmem4k tgm0 (
 
rtf65002_itagmem4k tgm0 (
 
        .wclk(clk),
 
        .wclk(clk),
 
        .wr((ack_i & isInsnCacheLoad)|isCacheReset),
 
        .wr((ack_i & isInsnCacheLoad)|isCacheReset),
 
        .adr({adr_o[31:1],!isCacheReset}),
 
        .adr({adr_o[33:1],!isCacheReset}),
 
        .rclk(~clk),
 
        .rclk(~clk),
 
        .pc(pc),
 
        .pc(pc),
 
        .hit0(hit0),
 
        .hit0(hit0),
 
        .hit1(hit1)
 
        .hit1(hit1)
 
);
 
);
Line 388... Line 400... 
);
 
);
 
 
 
 
 
rtf65002_itagmem8k tgm0 (
 
rtf65002_itagmem8k tgm0 (
 
        .wclk(clk),
 
        .wclk(clk),
 
        .wr((ack_i & isInsnCacheLoad)|isCacheReset),
 
        .wr((ack_i & isInsnCacheLoad)|isCacheReset),
 
        .adr({adr_o[31:1],!isCacheReset}),
 
        .adr({adr_o[33:1],!isCacheReset}),
 
        .rclk(~clk),
 
        .rclk(~clk),
 
        .pc(pc),
 
        .pc(pc),
 
        .hit0(hit0),
 
        .hit0(hit0),
 
        .hit1(hit1)
 
        .hit1(hit1)
 
);
 
);
Line 485... Line 497... 
2'd0:   dati <= dat_i[7:0];
 
2'd0:   dati <= dat_i[7:0];
 
2'd1:   dati <= dat_i[15:8];
 
2'd1:   dati <= dat_i[15:8];
 
2'd2:   dati <= dat_i[23:16];
 
2'd2:   dati <= dat_i[23:16];
 
2'd3:   dati <= dat_i[31:24];
 
2'd3:   dati <= dat_i[31:24];
 
endcase
 
endcase
 
 
 
`ifdef SUPPORT_DCACHE
 
reg [7:0] rdat8;
 
reg [7:0] rdat8;
 
always @(radr2LSB or rdat)
 
always @(radr2LSB or rdat)
 
case(radr2LSB)
 
case(radr2LSB)
 
2'd0:   rdat8 <= rdat[7:0];
 
2'd0:   rdat8 <= rdat[7:0];
 
2'd1:   rdat8 <= rdat[15:8];
 
2'd1:   rdat8 <= rdat[15:8];
 
2'd2:   rdat8 <= rdat[23:16];
 
2'd2:   rdat8 <= rdat[23:16];
 
2'd3:   rdat8 <= rdat[31:24];
 
2'd3:   rdat8 <= rdat[31:24];
 
endcase
 
endcase
 
 
 
`endif
 
 
 
 
 
// Evaluate branches
 
// Evaluate branches
 
// 
// 
reg takb;
 
reg takb;
 
always @(ir9 or cf or vf or nf or zf)
 
always @(ir9 or cf or vf or nf or zf)
Line 602... Line 616... 
        sel_o <= 4'h0;
 
        sel_o <= 4'h0;
 
        adr_o <= 34'd0;
 
        adr_o <= 34'd0;
 
        dat_o <= 32'd0;
 
        dat_o <= 32'd0;
 
        nmi_edge <= 1'b0;
 
        nmi_edge <= 1'b0;
 
        wai <= 1'b0;
 
        wai <= 1'b0;
 
        first_ifetch <= `TRUE;
 
 
 
        cf <= 1'b0;
 
        cf <= 1'b0;
 
        ir <= 64'hEAEAEAEAEAEAEAEA;
 
        ir <= 64'hEAEAEAEAEAEAEAEA;
 
        imiss <= `FALSE;
 
        imiss <= `FALSE;
 
        dmiss <= `FALSE;
 
        dmiss <= `FALSE;
 
        dcacheOn <= 1'b0;
 
        dcacheOn <= 1'b0;
Line 633... Line 646... 
        isCacheReset <= `TRUE;
 
        isCacheReset <= `TRUE;
 
        gie <= 1'b0;
 
        gie <= 1'b0;
 
        tick <= 32'd0;
 
        tick <= 32'd0;
 
        isIY <= 1'b0;
 
        isIY <= 1'b0;
 
        load_what <= `NOTHING;
 
        load_what <= `NOTHING;
 
 
 
`ifdef DEBUG
 
        hist_capture <= `TRUE;
 
        hist_capture <= `TRUE;
 
        history_ndx <= 6'd0;
 
        history_ndx <= 6'd0;
 
 
 
`endif
 
        pg2 <= `FALSE;
 
        pg2 <= `FALSE;
 
        tf <= `FALSE;
 
        tf <= `FALSE;
 
        km <= `TRUE;
 
        km <= `TRUE;
 
end
 
end
 
else begin
 
else begin
 
tick <= tick + 32'd1;
 
tick <= tick + 32'd1;
 
 
 
ilfsr <= {ilfsr,ilfsr_fb};
 
if (nmi_i & !nmi1)
 
if (nmi_i & !nmi1)
 
        nmi_edge <= 1'b1;
 
        nmi_edge <= 1'b1;
 
if (nmi_i|nmi1)
 
if (nmi_i|nmi1)
 
        clk_en <= 1'b1;
 
        clk_en <= 1'b1;
 
case(state)
 
case(state)
Line 713... Line 729... 
`ifdef SUPPORT_BERR
 
`ifdef SUPPORT_BERR
 
BUS_ERROR:
 
BUS_ERROR:
 
        begin
 
        begin
 
                pg2 <= `FALSE;
 
                pg2 <= `FALSE;
 
                ir <= {8{`BRK}};
 
                ir <= {8{`BRK}};
 
 
 
`ifdef DEBUG
 
                hist_capture <= `FALSE;
 
                hist_capture <= `FALSE;
 
 
 
`endif
 
                radr <= isp_dec;
 
                radr <= isp_dec;
 
                wadr <= isp_dec;
 
                wadr <= isp_dec;
 
                isp <= isp_dec;
 
                isp <= isp_dec;
 
                store_what <= `STW_OPC;
 
                store_what <= `STW_OPC;
 
                if (em | isOrb | isStb)
 
                vect <= {vbr[31:9],intno,2'b00};
 
                        derr_address <= adr_o[31:0];
 
 
 
                else
 
 
 
                        derr_address <= adr_o[33:2];
 
 
 
                vect <= {vbr[31:9],9'd508,2'b00};
 
 
 
                hwi <= `TRUE;
 
 
 
                isBusErr <= `TRUE;
 
 
 
                state <= STORE1;
 
 
 
        end
 
 
 
INSN_BUS_ERROR:
 
 
 
        begin
 
 
 
                pg2 <= `FALSE;
 
 
 
                ir <= {8{`BRK}};
 
 
 
                hist_capture <= `FALSE;
 
 
 
                radr <= isp_dec;
 
 
 
                wadr <= isp_dec;
 
 
 
                isp <= isp_dec;
 
 
 
                store_what <= `STW_OPC;
 
 
 
                derr_address <= 34'd0;
 
 
 
                vect <= {vbr[31:9],9'd509,2'b00};
 
 
 
                hwi <= `TRUE;
 
                hwi <= `TRUE;
 
                isBusErr <= `TRUE;
 
                isBusErr <= `TRUE;
 
                state <= STORE1;
 
                state <= STORE1;
 
        end
 
        end
 
`endif
 
`endif
Line 752... Line 751... 
endcase
 
endcase
 
end
 
end
 
`include "decode.v"
 
`include "decode.v"
 
`include "calc.v"
 
`include "calc.v"
 
`include "load_tsk.v"
 
`include "load_tsk.v"
 
 
 
`include "wb_task.v"
 
 
 
 
 
 
 
task next_state;
 
 
 
input [5:0] nxt;
 
 
 
begin
 
 
 
        state <= nxt;
 
 
 
end
 
 
 
endtask
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
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