| Line 103... |
Line 103... |
reg nmoi; // native mode on interrupt
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reg nmoi; // native mode on interrupt
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wire [31:0] sr = {nf,vf,em,tf,23'b0,bf,df,im,zf,cf};
|
wire [31:0] sr = {nf,vf,em,tf,23'b0,bf,df,im,zf,cf};
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wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};
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wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};
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reg nmi1,nmi_edge;
|
reg nmi1,nmi_edge;
|
reg wai;
|
reg wai;
|
|
reg wrrf; // write register file
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reg [31:0] acc;
|
reg [31:0] acc;
|
reg [31:0] x;
|
reg [31:0] x;
|
reg [31:0] y;
|
reg [31:0] y;
|
reg [7:0] sp;
|
reg [7:0] sp;
|
reg [31:0] spage; // stack page
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reg [31:0] spage; // stack page
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| Line 653... |
Line 654... |
history_ndx <= 6'd0;
|
history_ndx <= 6'd0;
|
`endif
|
`endif
|
pg2 <= `FALSE;
|
pg2 <= `FALSE;
|
tf <= `FALSE;
|
tf <= `FALSE;
|
km <= `TRUE;
|
km <= `TRUE;
|
|
wrrf <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
|
wrrf <= 1'b0;
|
tick <= tick + 32'd1;
|
tick <= tick + 32'd1;
|
ilfsr <= {ilfsr,ilfsr_fb};
|
ilfsr <= {ilfsr,ilfsr_fb};
|
if (nmi_i & !nmi1)
|
if (nmi_i & !nmi1)
|
nmi_edge <= 1'b1;
|
nmi_edge <= 1'b1;
|
if (nmi_i|nmi1)
|
if (nmi_i|nmi1)
|
| Line 747... |
Line 750... |
|
|
`include "rtf65002_string.v"
|
`include "rtf65002_string.v"
|
`include "cache_controller.v"
|
`include "cache_controller.v"
|
|
|
endcase
|
endcase
|
|
|
|
if (wrrf || state==IFETCH || state==LOAD_MAC3) begin
|
|
regfile[Rt] <= res[31:0];
|
|
case(Rt)
|
|
4'h1: acc <= res[31:0];
|
|
4'h2: x <= res[31:0];
|
|
4'h3: y <= res[31:0];
|
|
default: ;
|
|
endcase
|
end
|
end
|
|
|
|
end
|
|
|
|
|
`include "decode.v"
|
`include "decode.v"
|
`include "calc.v"
|
`include "calc.v"
|
`include "load_tsk.v"
|
`include "load_tsk.v"
|
`include "wb_task.v"
|
`include "wb_task.v"
|
|
|
| Line 760... |
Line 776... |
begin
|
begin
|
state <= nxt;
|
state <= nxt;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
function [127:0] fnStateName;
|
|
input [5:0] state;
|
|
case(state)
|
|
RESET1: fnStateName = "RESET1 ";
|
|
RESET2: fnStateName = "RESET2 ";
|
|
IFETCH: fnStateName = "IFETCH ";
|
|
DECODE: fnStateName = "DECODE ";
|
|
STORE1: fnStateName = "STORE1 ";
|
|
STORE2: fnStateName = "STORE2 ";
|
|
CALC: fnStateName = "CALC ";
|
|
RTS1: fnStateName = "RTS1 ";
|
|
IY3: fnStateName = "IY3 ";
|
|
BYTE_IX5: fnStateName = "BYTE_IX5 ";
|
|
BYTE_IY5: fnStateName = "BYTE_IY5 ";
|
|
WAIT_DHIT: fnStateName = "WAIT_DHIT ";
|
|
MULDIV1: fnStateName = "MULDIV1 ";
|
|
MULDIV2: fnStateName = "MULDIV2 ";
|
|
BYTE_DECODE: fnStateName = "BYTE_DECODE";
|
|
BYTE_CALC: fnStateName = "BYTE_CALC ";
|
|
BUS_ERROR: fnStateName = "BUS_ERROR ";
|
|
LOAD_MAC1: fnStateName = "LOAD_MAC1 ";
|
|
LOAD_MAC2: fnStateName = "LOAD_MAC2 ";
|
|
LOAD_MAC3: fnStateName = "LOAD_MAC3 ";
|
|
MVN3: fnStateName = "MVN3 ";
|
|
PUSHA1: fnStateName = "PUSHA1 ";
|
|
POPA1: fnStateName = "POPA1 ";
|
|
BYTE_IFETCH: fnStateName = "BYTE_IFETCH";
|
|
LOAD_DCACHE: fnStateName = "LOAD_DCACHE";
|
|
LOAD_ICACHE: fnStateName = "LOAD_ICACHE";
|
|
LOAD_IBUF1: fnStateName = "LOAD_IBUF1 ";
|
|
LOAD_IBUF2: fnStateName = "LOAD_IBUF2 ";
|
|
LOAD_IBUF3: fnStateName = "LOAD_IBUF3 ";
|
|
ICACHE1: fnStateName = "ICACHE1 ";
|
|
IBUF1: fnStateName = "IBUF1 ";
|
|
DCACHE1: fnStateName = "DCACHE1 ";
|
|
CMPS1: fnStateName = "CMPS1 ";
|
|
default: fnStateName = "UNKNOWN ";
|
|
endcase
|
|
endfunction
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
