| Line 1... |
Line 1... |
`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \\__/ o\ (C) 2013, 2014 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// rtf65002.v
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// rtf65002.v
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| Line 60... |
Line 60... |
parameter LOAD_IBUF3 = 6'd30;
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parameter LOAD_IBUF3 = 6'd30;
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parameter ICACHE1 = 6'd31;
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parameter ICACHE1 = 6'd31;
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parameter IBUF1 = 6'd32;
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parameter IBUF1 = 6'd32;
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parameter DCACHE1 = 6'd33;
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parameter DCACHE1 = 6'd33;
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parameter CMPS1 = 6'd34;
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parameter CMPS1 = 6'd34;
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parameter HALF_CALC = 6'd35;
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parameter MVN816 = 6'd36;
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parameter SPIN_CYCLES = 8'd30;
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input rst_md; // reset mode, 1=emulation mode, 0=native mode
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input rst_md; // reset mode, 1=emulation mode, 0=native mode
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input rst_i;
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input rst_i;
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input clk_i;
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input clk_i;
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input nmi_i;
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input nmi_i;
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| Line 99... |
Line 103... |
reg ttrig; // trace trigger
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reg ttrig; // trace trigger
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reg em1;
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reg em1;
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reg gie; // global interrupt enable (set when sp is loaded)
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reg gie; // global interrupt enable (set when sp is loaded)
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reg hwi; // hardware interrupt indicator
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reg hwi; // hardware interrupt indicator
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reg nmoi; // native mode on interrupt
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reg nmoi; // native mode on interrupt
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wire [31:0] sr = {nf,vf,em,tf,23'b0,bf,df,im,zf,cf};
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wire [31:0] sr = {nf,vf,em,tf,17'b0,m816,m_bit,x_bit,3'b0,bf,df,im,zf,cf};
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wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};
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reg m_bit; // acc/mem is 16 bit
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reg x_bit; // index regs are 16 bit
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reg m816; // 816 mode
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wire m16 = m816 & ~m_bit;
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wire xb16 = m816 & ~x_bit;
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wire [7:0] sr8 = m816 ? {nf,vf,m_bit,x_bit,df,im,zf,cf} : {nf,vf,1'b0,bf,df,im,zf,cf};
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reg nmi1,nmi_edge;
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reg nmi1,nmi_edge;
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reg wai;
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reg wai;
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reg spi; // spinlock interrupt
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reg [7:0] spi_cnt;
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reg wrrf; // write register file
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reg wrrf; // write register file
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reg [31:0] acc;
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reg [31:0] acc;
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reg [31:0] x;
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reg [31:0] x;
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reg [31:0] y;
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reg [31:0] y;
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reg [7:0] sp;
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reg [15:0] sp;
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reg [15:0] dpr; // direct page register
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reg [7:0] dbr; // data bank register
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reg [31:0] spage; // stack page
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reg [31:0] spage; // stack page
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wire [7:0] acc8 = acc[7:0];
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wire [7:0] acc8 = acc[7:0];
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wire [7:0] x8 = x[7:0];
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wire [7:0] x8 = x[7:0];
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wire [7:0] y8 = y[7:0];
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wire [7:0] y8 = y[7:0];
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wire [15:0] acc16 = acc[15:0];
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wire [15:0] x16 = x[15:0];
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wire [15:0] y16 = y[15:0];
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wire [31:0] x_dec = x - 32'd1;
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wire [31:0] x_inc = x + 32'd1;
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wire [31:0] y_dec = y - 32'd1;
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wire [31:0] y_inc = y + 32'd1;
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wire [31:0] acc_dec = acc - 32'd1;
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wire [31:0] acc_inc = acc + 32'd1;
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reg [31:0] isp; // interrupt stack pointer
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reg [31:0] isp; // interrupt stack pointer
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reg [31:0] oisp; // original isp for bus retry
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reg [31:0] oisp; // original isp for bus retry
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wire [63:0] prod;
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wire [63:0] prod;
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reg [15:0] tmp16;
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wire [31:0] q,r;
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wire [31:0] q,r;
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reg [31:0] tick;
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reg [31:0] tick;
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wire [7:0] sp_dec = sp - 8'd1;
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wire [15:0] sp_dec = sp - 16'd1;
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wire [7:0] sp_inc = sp + 8'd1;
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wire [15:0] sp_inc = sp + 16'd1;
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wire [15:0] sp_dec2 = sp - 16'd2;
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wire [31:0] isp_dec = isp - 32'd1;
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wire [31:0] isp_dec = isp - 32'd1;
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wire [31:0] isp_inc = isp + 32'd1;
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wire [31:0] isp_inc = isp + 32'd1;
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reg [3:0] suppress_pcinc;
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reg [3:0] suppress_pcinc;
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reg [31:0] pc;
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reg [31:0] pc;
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reg [31:0] opc;
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reg [31:0] opc;
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wire [3:0] pc_inc;
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wire [3:0] pc_inc;
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reg [3:0] pc_inc2;
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wire [3:0] pc_inc8;
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wire [3:0] pc_inc8;
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wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc); // for branches
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wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc); // for branches
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wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc); // for branches
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wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc); // for branches
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wire [31:0] pcp8 = pc + 32'd8; // cache controller needs this
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wire [31:0] pcp8 = pc + 32'd8; // cache controller needs this
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reg [31:0] abs8; // 8 bit mode absolute address register
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reg [31:0] abs8; // 8 bit mode absolute address register
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| Line 160... |
Line 185... |
default: rfob <= regfile[Rb];
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default: rfob <= regfile[Rb];
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endcase
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endcase
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reg [3:0] Rt;
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reg [3:0] Rt;
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reg [33:0] ea;
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reg [33:0] ea;
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reg first_ifetch;
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reg first_ifetch;
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reg [5:0] ic_whence;
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reg [31:0] lfsr;
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reg [31:0] lfsr;
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wire lfsr_fb;
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wire lfsr_fb;
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xnor(lfsr_fb,lfsr[0],lfsr[1],lfsr[21],lfsr[31]);
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xnor(lfsr_fb,lfsr[0],lfsr[1],lfsr[21],lfsr[31]);
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reg [31:0] a, b;
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reg [31:0] a, b;
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wire signed [31:0] as = a;
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wire signed [31:0] as = a;
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| Line 171... |
Line 197... |
wire lt = as < bs;
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wire lt = as < bs;
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wire eq = a==b;
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wire eq = a==b;
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wire ltu = a < b;
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wire ltu = a < b;
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reg [7:0] b8;
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reg [7:0] b8;
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reg [15:0] b16;
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wire [32:0] alu_out;
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wire [32:0] alu_out;
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reg [32:0] res;
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reg [32:0] res;
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reg [16:0] res16;
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reg [8:0] res8;
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reg [8:0] res8;
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wire resv8,resv32;
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wire resv8,resv16,resv32;
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wire resc8 = res8[8];
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wire resc8 = res8[8];
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wire resc16 = res16[16];
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wire resc32 = res[32];
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wire resc32 = res[32];
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wire resz8 = res8[7:0]==8'h00;
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wire resz8 = ~|res8[7:0];
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wire resz32 = res[31:0]==32'd0;
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wire resz16 = ~|res16[15:0];
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wire resz32 = ~|res[31:0];
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wire resn8 = res8[7];
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wire resn8 = res8[7];
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wire resn16 = res16[15];
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wire resn32 = res[31];
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wire resn32 = res[31];
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reg [33:0] vect;
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reg [33:0] vect;
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reg [31:0] ia; // temporary reg to hold indirect address
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reg [31:0] ia; // temporary reg to hold indirect address
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reg isInsnCacheLoad;
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reg isInsnCacheLoad;
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| Line 242... |
Line 273... |
reg hist_capture;
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reg hist_capture;
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`endif
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`endif
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reg isBusErr;
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reg isBusErr;
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reg isBrk,isMove,isSts;
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reg isBrk,isMove,isSts;
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reg isMove816;
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reg isRTI,isRTL,isRTS;
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reg isRTI,isRTL,isRTS;
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reg isOrb,isStb;
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reg isOrb,isStb;
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reg isRMW;
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reg isRMW;
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reg isSub,isSub8;
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reg isSub,isSub8;
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reg isJsrIndx,isJsrInd;
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reg isJsrIndx,isJsrInd;
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| Line 310... |
Line 342... |
wire isAtni = 1'b0;
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wire isAtni = 1'b0;
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`endif
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`endif
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wire md_done;
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wire md_done;
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wire clk;
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wire clk;
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reg isIY;
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reg isIY;
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reg isIY24;
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reg isI24;
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rtf65002_pcinc upci1
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rtf65002_pcinc upci1
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(
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(
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.opcode(ir9),
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.opcode(ir9),
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.suppress_pcinc(suppress_pcinc),
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.suppress_pcinc(suppress_pcinc),
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| Line 322... |
Line 356... |
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rtf65002_pcinc8 upci2
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rtf65002_pcinc8 upci2
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(
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(
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.opcode(ir[7:0]),
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.opcode(ir[7:0]),
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.suppress_pcinc(suppress_pcinc),
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.suppress_pcinc(suppress_pcinc),
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.inc(pc_inc8)
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.inc(pc_inc8),
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.m16(m16),
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.xb16(xb16)
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);
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);
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mult_div umd1
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mult_div umd1
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(
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(
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.rst(rst_i),
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.rst(rst_i),
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| Line 477... |
Line 513... |
.b(b8[7]),
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.b(b8[7]),
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.s(res8[7]),
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.s(res8[7]),
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.v(resv8)
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.v(resv8)
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);
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);
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wire [7:0] bcaio;
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wire [15:0] bcaio;
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wire [7:0] bcao;
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wire [15:0] bcao;
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wire [7:0] bcsio;
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wire [15:0] bcsio;
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wire [7:0] bcso;
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wire [15:0] bcso;
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wire bcaico,bcaco,bcsico,bcsco;
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wire bcaico,bcaco,bcsico,bcsco;
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wire bcaico8,bcaco8,bcsico8,bcsco8;
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`ifdef SUPPORT_BCD
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`ifdef SUPPORT_BCD
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BCDAdd ubcdai1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcaio),.c(bcaico));
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BCDAdd4 ubcdai1 (.ci(cf),.a(acc16),.b(ir[23:8]),.o(bcaio),.c(bcaico),.c8(bcaico8));
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BCDAdd ubcda2 (.ci(cf),.a(acc8),.b(b8),.o(bcao),.c(bcaco));
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BCDAdd4 ubcda2 (.ci(cf),.a(acc16),.b(b8),.o(bcao),.c(bcaco),.c8(bcaco8));
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BCDSub ubcdsi1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcsio),.c(bcsico));
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BCDSub4 ubcdsi1 (.ci(cf),.a(acc16),.b(ir[23:8]),.o(bcsio),.c(bcsico),.c8(bcsico8));
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BCDSub ubcds2 (.ci(cf),.a(acc8),.b(b8),.o(bcso),.c(bcsco));
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BCDSub4 ubcds2 (.ci(cf),.a(acc16),.b(b8),.o(bcso),.c(bcsco),.c8(bcsco8));
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`endif
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`endif
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reg [7:0] dati;
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reg [7:0] dati;
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always @(radr2LSB or dat_i)
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always @(radr2LSB or dat_i)
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case(radr2LSB)
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case(radr2LSB)
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| Line 533... |
Line 570... |
`BGT: takb <= (nf & vf & !zf) + (!nf & !vf & !zf);
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`BGT: takb <= (nf & vf & !zf) + (!nf & !vf & !zf);
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`BLE: takb <= zf | (nf & !vf)|(!nf & vf);
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`BLE: takb <= zf | (nf & !vf)|(!nf & vf);
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default: takb <= 1'b0;
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default: takb <= 1'b0;
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endcase
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endcase
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|
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wire [31:0] iapy8 = ia + y8; // Don't add in abs8, already included with ia
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wire [31:0] mvnsrc_address = {abs8[31:24],ir[23:16],x16};
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wire [31:0] zp_address = {abs8[31:16],8'h00,ir[15:8]};
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wire [31:0] mvndst_address = {abs8[31:24],ir[15: 8],y16};
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wire [31:0] zpx_address = {abs8[31:16],8'h00,ir[15:8]} + x8;
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wire [31:0] iapy8 = ia + y16; // Don't add in abs8, already included with ia
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wire [31:0] zpy_address = {abs8[31:16],8'h00,ir[15:8]} + y8;
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wire [31:0] zp_address = {abs8[31:16],8'h00,ir[15:8]} + dpr;
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wire [31:0] abs_address = {abs8[31:16],ir[23:8]};
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wire [31:0] zpx_address = {abs8[31:16],{8'h00,ir[15:8]} + x16} + dpr;
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wire [31:0] absx_address = {abs8[31:16],ir[23:8] + {8'h0,x8}}; // simulates 64k bank wrap-around
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wire [31:0] zpy_address = {abs8[31:16],{8'h00,ir[15:8]} + y16} + dpr;
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wire [31:0] absy_address = {abs8[31:16],ir[23:8] + {8'h0,y8}};
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wire [31:0] abs_address = {abs8[31:24],dbr,ir[23:8]};
|
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wire [31:0] absx_address = {abs8[31:24],dbr,ir[23:8] + x16}; // simulates 64k bank wrap-around
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wire [31:0] absy_address = {abs8[31:24],dbr,ir[23:8] + y16};
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wire [31:0] al_address = {abs8[31:24],ir[31:8]};
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wire [31:0] alx_address = {abs8[31:24],ir[31:8] + x16};
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wire [31:0] zpx32xy_address = ir[23:12] + rfoa;
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wire [31:0] zpx32xy_address = ir[23:12] + rfoa;
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wire [31:0] absx32xy_address = ir[47:16] + rfob;
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wire [31:0] absx32xy_address = ir[47:16] + rfob;
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wire [31:0] zpx32_address = ir[31:20] + rfob;
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wire [31:0] zpx32_address = ir[31:20] + rfob;
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wire [31:0] absx32_address = ir[55:24] + rfob;
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wire [31:0] absx32_address = ir[55:24] + rfob;
|
|
|
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wire [31:0] dsp_address = m816 ? {abs8[31:24],8'h00,sp + ir[15:8]} : {abs8[31:16],8'h01,sp[7:0]+ir[15:8]};
|
|
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rtf65002_alu ualu1
|
rtf65002_alu ualu1
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.state(state),
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.state(state),
|
.resin(res),
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.resin(res),
|
| Line 617... |
Line 660... |
sel_o <= 4'h0;
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sel_o <= 4'h0;
|
adr_o <= 34'd0;
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adr_o <= 34'd0;
|
dat_o <= 32'd0;
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dat_o <= 32'd0;
|
nmi_edge <= 1'b0;
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nmi_edge <= 1'b0;
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wai <= 1'b0;
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wai <= 1'b0;
|
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spi <= 1'b0;
|
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spi_cnt <= SPIN_CYCLES;
|
cf <= 1'b0;
|
cf <= 1'b0;
|
ir <= 64'hEAEAEAEAEAEAEAEA;
|
ir <= 64'hEAEAEAEAEAEAEAEA;
|
imiss <= `FALSE;
|
imiss <= `FALSE;
|
dmiss <= `FALSE;
|
dmiss <= `FALSE;
|
dcacheOn <= 1'b0;
|
dcacheOn <= 1'b0;
|
icacheOn <= 1'b1;
|
icacheOn <= 1'b1;
|
write_allocate <= 1'b0;
|
write_allocate <= 1'b0;
|
nmoi <= 1'b1;
|
nmoi <= 1'b1;
|
state <= RESET1;
|
state <= RESET1;
|
|
m816 <= 1'b0;
|
|
m_bit <= 1'b1;
|
|
x_bit <= 1'b1;
|
if (rst_md) begin
|
if (rst_md) begin
|
pc <= 32'h0000FFF0; // set high-order pc to zero
|
pc <= 32'h0000FFF0; // set high-order pc to zero
|
vect <= `BYTE_RST_VECT;
|
vect <= `BYTE_RST_VECT;
|
em <= 1'b1;
|
em <= 1'b1;
|
end
|
end
|
| Line 638... |
Line 686... |
em <= 1'b0;
|
em <= 1'b0;
|
pc <= 32'hFFFFFFF0;
|
pc <= 32'hFFFFFFF0;
|
end
|
end
|
suppress_pcinc <= 4'hF;
|
suppress_pcinc <= 4'hF;
|
exbuf <= 64'd0;
|
exbuf <= 64'd0;
|
|
dbr <= 8'h00;
|
|
dpr <= 16'h0000;
|
spage <= 32'h00000100;
|
spage <= 32'h00000100;
|
bufadr <= 32'd0;
|
bufadr <= 32'd0;
|
abs8 <= 32'd0;
|
abs8 <= 32'd0;
|
clk_en <= 1'b1;
|
clk_en <= 1'b1;
|
isCacheReset <= `TRUE;
|
isCacheReset <= `TRUE;
|
gie <= 1'b0;
|
gie <= 1'b0;
|
tick <= 32'd0;
|
tick <= 32'd0;
|
isIY <= 1'b0;
|
isIY <= 1'b0;
|
|
isIY24 <= 1'b0;
|
|
isI24 <= `FALSE;
|
load_what <= `NOTHING;
|
load_what <= `NOTHING;
|
`ifdef DEBUG
|
`ifdef DEBUG
|
hist_capture <= `TRUE;
|
hist_capture <= `TRUE;
|
history_ndx <= 6'd0;
|
history_ndx <= 6'd0;
|
`endif
|
`endif
|
| Line 689... |
Line 741... |
`include "ifetch.v"
|
`include "ifetch.v"
|
`ifdef SUPPORT_EM8
|
`ifdef SUPPORT_EM8
|
`include "byte_ifetch.v"
|
`include "byte_ifetch.v"
|
`include "byte_decode.v"
|
`include "byte_decode.v"
|
`include "byte_calc.v"
|
`include "byte_calc.v"
|
|
`ifdef SUPPORT_816
|
|
`include "half_calc.v"
|
|
`endif
|
`endif
|
`endif
|
|
|
`include "load_mac.v"
|
`include "load_mac.v"
|
`include "store.v"
|
`include "store.v"
|
|
|
| Line 742... |
Line 797... |
isp <= isp_dec;
|
isp <= isp_dec;
|
store_what <= `STW_OPC;
|
store_what <= `STW_OPC;
|
vect <= {vbr[31:9],intno,2'b00};
|
vect <= {vbr[31:9],intno,2'b00};
|
hwi <= `TRUE;
|
hwi <= `TRUE;
|
isBusErr <= `TRUE;
|
isBusErr <= `TRUE;
|
state <= STORE1;
|
next_state(STORE1);
|
end
|
end
|
`endif
|
`endif
|
|
|
`include "rtf65002_string.v"
|
`include "rtf65002_string.v"
|
`include "cache_controller.v"
|
`include "cache_controller.v"
|
| Line 768... |
Line 823... |
|
|
`include "decode.v"
|
`include "decode.v"
|
`include "calc.v"
|
`include "calc.v"
|
`include "load_tsk.v"
|
`include "load_tsk.v"
|
`include "wb_task.v"
|
`include "wb_task.v"
|
|
`include "misc_task.v"
|
|
|
task next_state;
|
task next_state;
|
input [5:0] nxt;
|
input [5:0] nxt;
|
begin
|
begin
|
state <= nxt;
|
state <= nxt;
|
| Line 812... |
Line 868... |
LOAD_IBUF3: fnStateName = "LOAD_IBUF3 ";
|
LOAD_IBUF3: fnStateName = "LOAD_IBUF3 ";
|
ICACHE1: fnStateName = "ICACHE1 ";
|
ICACHE1: fnStateName = "ICACHE1 ";
|
IBUF1: fnStateName = "IBUF1 ";
|
IBUF1: fnStateName = "IBUF1 ";
|
DCACHE1: fnStateName = "DCACHE1 ";
|
DCACHE1: fnStateName = "DCACHE1 ";
|
CMPS1: fnStateName = "CMPS1 ";
|
CMPS1: fnStateName = "CMPS1 ";
|
|
HALF_CALC: fnStateName = "HALF_CALC ";
|
default: fnStateName = "UNKNOWN ";
|
default: fnStateName = "UNKNOWN ";
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
endmodule
|
endmodule
|
