| Line 1... |
Line 1... |
// ============================================================================
|
// ============================================================================
|
// __
|
// __
|
// \\__/ o\ (C) 2013 Robert Finch, Stratford
|
// \\__/ o\ (C) 2013,2014 Robert Finch, Stratford
|
// \ __ / All rights reserved.
|
// \ __ / All rights reserved.
|
// \/_// robfinch<remove>@opencores.org
|
// \/_// robfinch<remove>@opencores.org
|
// ||
|
// ||
|
//
|
//
|
// This source file is free software: you can redistribute it and/or modify
|
// This source file is free software: you can redistribute it and/or modify
|
| Line 17... |
Line 17... |
//
|
//
|
// You should have received a copy of the GNU General Public License
|
// You should have received a copy of the GNU General Public License
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
//
|
//
|
// Memory store states
|
// Memory store states
|
// The store states work for either eight bit or 32 bit mode
|
// The store states work for 8, 16 or 32 bit mode
|
// ============================================================================
|
// ============================================================================
|
//
|
//
|
// Stores always write through to memory, then optionally update the cache if
|
// Stores always write through to memory, then optionally update the cache if
|
// there was a write hit.
|
// there was a write hit.
|
STORE1:
|
STORE1:
|
| Line 48... |
Line 48... |
`STW_PC3124: wb_write(1,{4{pc[31:24]}});
|
`STW_PC3124: wb_write(1,{4{pc[31:24]}});
|
`STW_PC2316: wb_write(1,{4{pc[23:16]}});
|
`STW_PC2316: wb_write(1,{4{pc[23:16]}});
|
`STW_PC158: wb_write(1,{4{pc[15:8]}});
|
`STW_PC158: wb_write(1,{4{pc[15:8]}});
|
`STW_PC70: wb_write(1,{4{pc[7:0]}});
|
`STW_PC70: wb_write(1,{4{pc[7:0]}});
|
`STW_SR70: wb_write(1,{4{sr8}});
|
`STW_SR70: wb_write(1,{4{sr8}});
|
`STW_DEF8: wb_write(1,wdat);
|
`STW_DEF8: wb_write(1,{4{wdat[7:0]}});
|
|
`endif
|
|
`ifdef SUPPORT_816
|
|
`STW_DEF70: begin wb_write(1,{4{wdat[7:0]}}); lock_o <= 1'b1; end
|
|
`STW_DEF158: wb_write(1,{4{wdat[15:8]}});
|
|
`STW_ACC70: begin wb_write(1,{4{acc[7:0]}}); lock_o <= 1'b1; end
|
|
`STW_ACC158: wb_write(1,{4{acc[15:8]}});
|
|
`STW_X70: begin wb_write(1,{4{x[7:0]}}); lock_o <= 1'b1; end
|
|
`STW_X158: wb_write(1,{4{x[15:8]}});
|
|
`STW_Y70: begin wb_write(1,{4{y[7:0]}}); lock_o <= 1'b1; end
|
|
`STW_Y158: wb_write(1,{4{y[15:8]}});
|
|
`STW_Z70: begin wb_write(1,{4{8'h00}}); lock_o <= 1'b1; end
|
|
`STW_Z158: wb_write(1,{4{8'h00}});
|
|
`STW_DBR: wb_write(1,{4{dbr}});
|
|
`STW_DPR158: begin wb_write(1,{4{dpr[15:8]}}); lock_o <= 1'b1; end
|
|
`STW_DPR70: wb_write(1,{4{dpr[7:0]}});
|
|
`STW_TMP158: begin wb_write(1,{4{tmp16[15:8]}}); lock_o <= 1'b1; end
|
|
`STW_TMP70: wb_write(1,{4{tmp16[7:0]}});
|
|
`STW_IA158: begin wb_write(1,{4{ia[15:8]}}); lock_o <= 1'b1; end
|
|
`STW_IA70: wb_write(1,{4{ia[7:0]}});
|
`endif
|
`endif
|
default: wb_write(0,wdat);
|
default: wb_write(0,wdat);
|
endcase
|
endcase
|
`ifdef SUPPORT_DCACHE
|
`ifdef SUPPORT_DCACHE
|
radr <= wadr; // Do a cache read to test the hit
|
radr <= wadr; // Do a cache read to test the hit
|
| Line 72... |
Line 91... |
wb_nack();
|
wb_nack();
|
isp <= oisp;
|
isp <= oisp;
|
state <= DECODE;
|
state <= DECODE;
|
end
|
end
|
else if (ack_i) begin
|
else if (ack_i) begin
|
wdat <= dat_o;
|
// wdat <= dat_o;
|
if (isMove|isSts) begin
|
if (!em && (isMove|isSts)) begin
|
state <= MVN3;
|
state <= MVN3;
|
retstate <= MVN3;
|
retstate <= MVN3;
|
end
|
end
|
else begin
|
else begin
|
if (em) begin
|
if (em) begin
|
|
if (isMove) begin
|
|
state <= MVN816;
|
|
retstate <= MVN816;
|
|
end
|
|
else begin
|
state <= BYTE_IFETCH;
|
state <= BYTE_IFETCH;
|
retstate <= BYTE_IFETCH;
|
retstate <= BYTE_IFETCH;
|
end
|
end
|
|
end
|
else begin
|
else begin
|
state <= IFETCH;
|
state <= IFETCH;
|
retstate <= IFETCH;
|
retstate <= IFETCH;
|
end
|
end
|
end
|
end
|
| Line 125... |
Line 150... |
wadr <= isp_dec;
|
wadr <= isp_dec;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
end
|
end
|
ir[11:8] <= ir[11:8] + 4'd1;
|
ir[11:8] <= ir[11:8] + 4'd1;
|
end
|
end
|
|
`ifdef SUPPORT_816
|
|
`STW_DEF70:
|
|
begin
|
|
lock_o <= 1'b1;
|
|
wadr2LSB <= wadr2LSB + 2'b01;
|
|
if (wadr2LSB==2'b11)
|
|
wadr <= wadr + 32'd1;
|
|
store_what <= `STW_DEF158;
|
|
retstate <= STORE1;
|
|
state <= STORE1;
|
|
end
|
|
`STW_ACC70:
|
|
begin
|
|
lock_o <= 1'b1;
|
|
wadr2LSB <= wadr2LSB + 2'b01;
|
|
if (wadr2LSB==2'b11)
|
|
wadr <= wadr + 32'd1;
|
|
store_what <= `STW_ACC158;
|
|
retstate <= STORE1;
|
|
state <= STORE1;
|
|
end
|
|
`STW_X70:
|
|
begin
|
|
lock_o <= 1'b1;
|
|
wadr2LSB <= wadr2LSB + 2'b01;
|
|
if (wadr2LSB==2'b11)
|
|
wadr <= wadr + 32'd1;
|
|
store_what <= `STW_X158;
|
|
retstate <= STORE1;
|
|
state <= STORE1;
|
|
end
|
|
`STW_Y70:
|
|
begin
|
|
lock_o <= 1'b1;
|
|
wadr2LSB <= wadr2LSB + 2'b01;
|
|
if (wadr2LSB==2'b11)
|
|
wadr <= wadr + 32'd1;
|
|
store_what <= `STW_Y158;
|
|
retstate <= STORE1;
|
|
state <= STORE1;
|
|
end
|
|
`STW_Z70:
|
|
begin
|
|
lock_o <= 1'b1;
|
|
wadr2LSB <= wadr2LSB + 2'b01;
|
|
if (wadr2LSB==2'b11)
|
|
wadr <= wadr + 32'd1;
|
|
store_what <= `STW_Z158;
|
|
retstate <= STORE1;
|
|
state <= STORE1;
|
|
end
|
|
`STW_DPR158:
|
|
begin
|
|
set_sp();
|
|
store_what <= `STW_DPR70;
|
|
retstate <= STORE1;
|
|
state <= STORE1;
|
|
end
|
|
`STW_TMP158:
|
|
begin
|
|
set_sp();
|
|
store_what <= `STW_TMP70;
|
|
retstate <= STORE1;
|
|
state <= STORE1;
|
|
end
|
|
`STW_IA158:
|
|
begin
|
|
set_sp();
|
|
store_what <= `STW_IA70;
|
|
retstate <= STORE1;
|
|
state <= STORE1;
|
|
end
|
|
`endif
|
`ifdef SUPPORT_EM8
|
`ifdef SUPPORT_EM8
|
`STW_PC3124:
|
`STW_PC3124:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
| Line 139... |
Line 237... |
retstate <= STORE1;
|
retstate <= STORE1;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STW_PC2316:
|
`STW_PC2316:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
if (ir9 != `PHK) begin
|
wadr <= {spage[31:8],sp[7:2]};
|
set_sp();
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
sp <= sp_dec;
|
|
store_what <= `STW_PC158;
|
store_what <= `STW_PC158;
|
retstate <= STORE1;
|
retstate <= STORE1;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
|
end
|
`STW_PC158:
|
`STW_PC158:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
set_sp();
|
wadr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
sp <= sp_dec;
|
|
store_what <= `STW_PC70;
|
store_what <= `STW_PC70;
|
retstate <= STORE1;
|
retstate <= STORE1;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STW_PC70:
|
`STW_PC70:
|
begin
|
begin
|
case({1'b0,ir[7:0]})
|
case({1'b0,ir[7:0]})
|
`BRK: begin
|
`BRK,`COP:
|
radr <= {spage[31:8],sp[7:2]};
|
begin
|
wadr <= {spage[31:8],sp[7:2]};
|
set_sp();
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
sp <= sp_dec;
|
|
store_what <= `STW_SR70;
|
store_what <= `STW_SR70;
|
retstate <= STORE1;
|
retstate <= STORE1;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`JSR: begin
|
`JSR: begin
|
pc[15:0] <= ir[23:8];
|
pc[15:0] <= ir[23:8];
|
end
|
end
|
`JSL: begin
|
`JSL: begin
|
pc <= ir[39:8];
|
pc[23:0] <= ir[31:8];
|
end
|
end
|
`JSR_INDX:
|
`JSR_INDX:
|
begin
|
begin
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
retstate <= LOAD_MAC1;
|
retstate <= LOAD_MAC1;
|
| Line 199... |
Line 288... |
pc[31:16] <= abs8[31:16];
|
pc[31:16] <= abs8[31:16];
|
radr <= vect[33:2];
|
radr <= vect[33:2];
|
radr2LSB <= vect[1:0];
|
radr2LSB <= vect[1:0];
|
im <= hwi;
|
im <= hwi;
|
end
|
end
|
|
else if (ir[7:0]==`COP) begin
|
|
load_what <= `PC_70;
|
|
state <= LOAD_MAC1;
|
|
retstate <= LOAD_MAC1;
|
|
pc[31:16] <= abs8[31:16];
|
|
radr <= vect[33:2];
|
|
radr2LSB <= vect[1:0];
|
|
im <= 1'b1;
|
|
end
|
end
|
end
|
`endif
|
`endif
|
default:
|
default:
|
if (isJsrIndx) begin
|
if (isJsrIndx) begin
|
load_what <= `PC_310;
|
load_what <= `PC_310;
|
