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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [store.v] - Diff between revs 23 and 25

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Rev 23 Rev 25
Line 27... Line 27...
STORE1:
STORE1:
        begin
        begin
                cyc_o <= 1'b1;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                we_o <= 1'b1;
                if (em || isStb)
                if (em || isStb) begin
                        case(wadr2LSB)
                        case(wadr2LSB)
                        2'd0:   sel_o <= 4'b0001;
                        2'd0:   sel_o <= 4'b0001;
                        2'd1:   sel_o <= 4'b0010;
                        2'd1:   sel_o <= 4'b0010;
                        2'd2:   sel_o <= 4'b0100;
                        2'd2:   sel_o <= 4'b0100;
                        2'd3:   sel_o <= 4'b1000;
                        2'd3:   sel_o <= 4'b1000;
                        endcase
                        endcase
 
                end
                else
                else
                        sel_o <= 4'hf;
                        sel_o <= 4'hf;
                adr_o <= {wadr,2'b00};
                adr_o <= {wadr,2'b00};
                dat_o <= wdat;
                dat_o <= wdat;
                radr <= wadr;           // Do a cache read to test the hit
                radr <= wadr;           // Do a cache read to test the hit

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