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https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
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Rev 30 |
| Line 38... |
Line 38... |
endcase
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endcase
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end
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end
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else
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else
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sel_o <= 4'hf;
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sel_o <= 4'hf;
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adr_o <= {wadr,2'b00};
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adr_o <= {wadr,2'b00};
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dat_o <= wdat;
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case(store_what)
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`STW_ACC: dat_o <= acc;
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`STW_X: dat_o <= x;
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`STW_Y: dat_o <= y;
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`STW_PC: dat_o <= pc;
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`STW_PC2: dat_o <= pc + 32'd2;
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`STW_PCHWI: dat_o <= pc+{30'b0,~hwi,1'b0};
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`STW_SR: dat_o <= sr;
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`STW_RFA: dat_o <= rfoa;
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`STW_RFA8: dat_o <= {4{rfoa[7:0]}};
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`STW_A: dat_o <= a;
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`STW_B: dat_o <= b;
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`STW_CALC: dat_o <= calc_res;
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`ifdef SUPPORT_EM8
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`STW_ACC8: dat_o <= {4{acc8}};
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`STW_X8: dat_o <= {4{x8}};
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`STW_Y8: dat_o <= {4{y8}};
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`STW_PC3124: dat_o <= {4{pc[31:24]}};
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`STW_PC2316: dat_o <= {4{pc[23:16]}};
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`STW_PC158: dat_o <= {4{pc[15:8]}};
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`STW_PC70: dat_o <= {4{pc[7:0]}};
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`STW_SR70: dat_o <= {4{sr8}};
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`endif
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default: dat_o <= wdat;
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endcase
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`ifdef SUPPORT_DCACHE
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radr <= wadr; // Do a cache read to test the hit
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radr <= wadr; // Do a cache read to test the hit
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`endif
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state <= STORE2;
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state <= STORE2;
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end
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end
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// Terminal state for stores. Update the data cache if there was a cache hit.
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// Terminal state for stores. Update the data cache if there was a cache hit.
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// Clear any previously set lock status
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// Clear any previously set lock status
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STORE2:
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STORE2:
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if (ack_i) begin
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if (ack_i) begin
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if (isMove)
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wdat <= dat_o;
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if (isMove|isSts) begin
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state <= MVN3;
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state <= MVN3;
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else
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retstate <= MVN3;
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end
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else begin
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state <= IFETCH;
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state <= IFETCH;
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retstate <= IFETCH;
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end
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lock_o <= 1'b0;
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lock_o <= 1'b0;
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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sel_o <= 4'h0;
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adr_o <= 34'h0;
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adr_o <= 34'h0;
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dat_o <= 32'h0;
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dat_o <= 32'h0;
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case(store_what)
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`STW_PC,`STW_PC2,`STW_PCHWI:
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if (isBrk) begin
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radr <= isp_dec;
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wadr <= isp_dec;
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isp <= isp_dec;
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store_what <= `STW_SR;
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state <= STORE1;
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retstate <= STORE1;
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end
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`STW_SR:
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if (isBrk) begin
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load_what <= `PC_310;
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state <= LOAD_MAC1;
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retstate <= LOAD_MAC1;
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radr <= vect[31:2];
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if (hwi)
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im <= 1'b1;
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em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
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end
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`ifdef SUPPORT_EM8
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`STW_PC3124:
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begin
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store_what <= `STW_PC2316;
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state <= STORE1;
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end
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`STW_PC2316:
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begin
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store_what <= `STW_PC158;
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state <= STORE1;
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end
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`STW_PC158:
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begin
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store_what <= `STW_PC70;
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state <= STORE1;
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end
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`STW_PC70:
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begin
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if (ir[7:0]==`BRK) begin
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store_what <= `STW_SR70;
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state <= STORE1;
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end
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end
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`endif
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endcase
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`ifdef SUPPORT_DCACHE
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if (dhit) begin
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if (dhit) begin
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wrsel <= sel_o;
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wrsel <= sel_o;
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wr <= 1'b1;
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wr <= 1'b1;
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end
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end
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else if (write_allocate) begin
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else if (write_allocate) begin
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dmiss <= `TRUE;
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dmiss <= `TRUE;
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state <= WAIT_DHIT;
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state <= WAIT_DHIT;
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if (isMove)
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retstate <= MVN3;
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else
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retstate <= IFETCH;
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end
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end
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`endif
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end
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end
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`ifdef SUPPORT_BERR
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else if (err_i) begin
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else if (err_i) begin
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lock_o <= 1'b0;
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lock_o <= 1'b0;
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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sel_o <= 4'h0;
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dat_o <= 32'h0;
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dat_o <= 32'h0;
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state <= BUS_ERROR;
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state <= BUS_ERROR;
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end
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end
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`endif
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