| Line 45... |
Line 45... |
`STW_X: dat_o <= x;
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`STW_X: dat_o <= x;
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`STW_Y: dat_o <= y;
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`STW_Y: dat_o <= y;
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`STW_PC: dat_o <= pc;
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`STW_PC: dat_o <= pc;
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`STW_PC2: dat_o <= pc + 32'd2;
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`STW_PC2: dat_o <= pc + 32'd2;
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`STW_PCHWI: dat_o <= pc+{30'b0,~hwi,1'b0};
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`STW_PCHWI: dat_o <= pc+{30'b0,~hwi,1'b0};
|
|
`STW_OPC: dat_o <= opc;
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`STW_SR: dat_o <= sr;
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`STW_SR: dat_o <= sr;
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`STW_RFA: dat_o <= rfoa;
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`STW_RFA: dat_o <= rfoa;
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`STW_RFA8: dat_o <= {4{rfoa[7:0]}};
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`STW_RFA8: dat_o <= {4{rfoa[7:0]}};
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`STW_A: dat_o <= a;
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`STW_A: dat_o <= a;
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`STW_B: dat_o <= b;
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`STW_B: dat_o <= b;
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`STW_CALC: dat_o <= calc_res;
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`STW_CALC: dat_o <= res;
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`ifdef SUPPORT_EM8
|
`ifdef SUPPORT_EM8
|
`STW_ACC8: dat_o <= {4{acc8}};
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`STW_ACC8: dat_o <= {4{acc8}};
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`STW_X8: dat_o <= {4{x8}};
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`STW_X8: dat_o <= {4{x8}};
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`STW_Y8: dat_o <= {4{y8}};
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`STW_Y8: dat_o <= {4{y8}};
|
|
`STW_Z8: dat_o <= {4{8'h00}};
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`STW_PC3124: dat_o <= {4{pc[31:24]}};
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`STW_PC3124: dat_o <= {4{pc[31:24]}};
|
`STW_PC2316: dat_o <= {4{pc[23:16]}};
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`STW_PC2316: dat_o <= {4{pc[23:16]}};
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`STW_PC158: dat_o <= {4{pc[15:8]}};
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`STW_PC158: dat_o <= {4{pc[15:8]}};
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`STW_PC70: dat_o <= {4{pc[7:0]}};
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`STW_PC70: dat_o <= {4{pc[7:0]}};
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`STW_SR70: dat_o <= {4{sr8}};
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`STW_SR70: dat_o <= {4{sr8}};
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| Line 79... |
Line 81... |
if (isMove|isSts) begin
|
if (isMove|isSts) begin
|
state <= MVN3;
|
state <= MVN3;
|
retstate <= MVN3;
|
retstate <= MVN3;
|
end
|
end
|
else begin
|
else begin
|
|
if (em) begin
|
|
state <= BYTE_IFETCH;
|
|
retstate <= BYTE_IFETCH;
|
|
end
|
|
else begin
|
state <= IFETCH;
|
state <= IFETCH;
|
retstate <= IFETCH;
|
retstate <= IFETCH;
|
end
|
end
|
|
end
|
lock_o <= 1'b0;
|
lock_o <= 1'b0;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
we_o <= 1'b0;
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we_o <= 1'b0;
|
sel_o <= 4'h0;
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sel_o <= 4'h0;
|
adr_o <= 34'h0;
|
adr_o <= 34'h0;
|
dat_o <= 32'h0;
|
dat_o <= 32'h0;
|
case(store_what)
|
case(store_what)
|
`STW_PC,`STW_PC2,`STW_PCHWI:
|
`STW_PC,`STW_PC2,`STW_PCHWI,`STW_OPC:
|
if (isBrk) begin
|
if (isBrk|isBusErr) begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
store_what <= `STW_SR;
|
store_what <= `STW_SR;
|
state <= STORE1;
|
state <= STORE1;
|
retstate <= STORE1;
|
retstate <= STORE1;
|
end
|
end
|
`STW_SR:
|
`STW_SR:
|
if (isBrk) begin
|
if (isBrk|isBusErr) begin
|
load_what <= `PC_310;
|
load_what <= `PC_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
retstate <= LOAD_MAC1;
|
retstate <= LOAD_MAC1;
|
radr <= vect[31:2];
|
radr <= vect[31:2];
|
if (hwi)
|
ttrig <= 1'b0;
|
|
tf <= 1'b0; // turn off trace mode
|
im <= 1'b1;
|
im <= 1'b1;
|
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
|
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
|
end
|
end
|
|
`STW_RFA:
|
|
if (isPusha) begin
|
|
if (ir[11:8]==4'hF) begin
|
|
state <= IFETCH;
|
|
retstate <= IFETCH;
|
|
end
|
|
else begin
|
|
state <= STORE1;
|
|
retstate <= STORE1;
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
isp <= isp_dec;
|
|
end
|
|
ir[11:8] <= ir[11:8] + 4'd1;
|
|
end
|
`ifdef SUPPORT_EM8
|
`ifdef SUPPORT_EM8
|
`STW_PC3124:
|
`STW_PC3124:
|
begin
|
begin
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
store_what <= `STW_PC2316;
|
store_what <= `STW_PC2316;
|
|
sp <= sp_dec;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STW_PC2316:
|
`STW_PC2316:
|
begin
|
begin
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
sp <= sp_dec;
|
store_what <= `STW_PC158;
|
store_what <= `STW_PC158;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STW_PC158:
|
`STW_PC158:
|
begin
|
begin
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
sp <= sp_dec;
|
store_what <= `STW_PC70;
|
store_what <= `STW_PC70;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STW_PC70:
|
`STW_PC70:
|
begin
|
begin
|
if (ir[7:0]==`BRK) begin
|
case({1'b0,ir[7:0]})
|
|
`BRK: begin
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
sp <= sp_dec;
|
store_what <= `STW_SR70;
|
store_what <= `STW_SR70;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
|
`JSR: begin
|
|
pc <= ir[23:8];
|
|
$display("setting pc=%h", ir[23:8]);
|
|
end
|
|
`JSL: begin
|
|
pc <= ir[39:8];
|
|
end
|
|
`JSR_INDX:
|
|
begin
|
|
state <= LOAD_MAC1;
|
|
retstate <= LOAD_MAC1;
|
|
load_what <= `PC_70;
|
|
radr <= absx_address[31:2];
|
|
radr2LSB <= absx_address[1:0];
|
|
end
|
|
endcase
|
|
end
|
|
`STW_SR70:
|
|
begin
|
|
if (ir[7:0]==`BRK) begin
|
|
load_what <= `PC_70;
|
|
state <= LOAD_MAC1;
|
|
retstate <= LOAD_MAC1;
|
|
pc[31:16] <= abs8[31:16];
|
|
radr <= vect[31:2];
|
|
radr2LSB <= vect[1:0];
|
|
im <= hwi;
|
|
end
|
end
|
end
|
`endif
|
`endif
|
|
default:
|
|
if (isJsrIndx) begin
|
|
load_what <= `PC_310;
|
|
state <= LOAD_MAC1;
|
|
retstate <= LOAD_MAC1;
|
|
radr <= ir[39:8] + x;
|
|
end
|
|
else if (isJsrInd) begin
|
|
load_what <= `PC_310;
|
|
state <= LOAD_MAC1;
|
|
retstate <= LOAD_MAC1;
|
|
radr <= ir[39:8];
|
|
end
|
endcase
|
endcase
|
`ifdef SUPPORT_DCACHE
|
`ifdef SUPPORT_DCACHE
|
if (dhit) begin
|
if (!dhit && write_allocate) begin
|
wrsel <= sel_o;
|
state <= DCACHE1;
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
dmiss <= `TRUE;
|
|
state <= WAIT_DHIT;
|
|
end
|
end
|
`endif
|
`endif
|
end
|
end
|
`ifdef SUPPORT_BERR
|
`ifdef SUPPORT_BERR
|
else if (err_i) begin
|
else if (err_i) begin
|
