| Line 24... |
Line 24... |
//
|
//
|
// Stores always write through to memory, then optionally update the cache if
|
// Stores always write through to memory, then optionally update the cache if
|
// there was a write hit.
|
// there was a write hit.
|
STORE1:
|
STORE1:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
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|
if (em || isStb) begin
|
|
case(wadr2LSB)
|
|
2'd0: sel_o <= 4'b0001;
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|
2'd1: sel_o <= 4'b0010;
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|
2'd2: sel_o <= 4'b0100;
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|
2'd3: sel_o <= 4'b1000;
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|
endcase
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|
end
|
|
else
|
|
sel_o <= 4'hf;
|
|
adr_o <= {wadr,2'b00};
|
|
case(store_what)
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case(store_what)
|
`STW_ACC: dat_o <= acc;
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`STW_ACC: wb_write(0,acc);
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`STW_X: dat_o <= x;
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`STW_X: wb_write(0,x);
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`STW_Y: dat_o <= y;
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`STW_Y: wb_write(0,y);
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`STW_PC: dat_o <= pc;
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`STW_PC: wb_write(0,pc);
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`STW_PC2: dat_o <= pc + 32'd2;
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`STW_PC2: wb_write(0,pc + 32'd2);
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`STW_PCHWI: dat_o <= pc+{30'b0,~hwi,1'b0};
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`STW_PCHWI: wb_write(0,pc+{30'b0,~hwi,1'b0});
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`STW_OPC: dat_o <= opc;
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`STW_OPC: wb_write(0,opc);
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`STW_SR: dat_o <= sr;
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`STW_SR: wb_write(0,sr);
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`STW_RFA: dat_o <= rfoa;
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`STW_RFA: wb_write(0,rfoa);
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`STW_RFA8: dat_o <= {4{rfoa[7:0]}};
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`STW_RFA8: wb_write(1,{4{rfoa[7:0]}});
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`STW_A: dat_o <= a;
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`STW_A: wb_write(0,a);
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`STW_B: dat_o <= b;
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`STW_B: wb_write(0,b);
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`STW_CALC: dat_o <= res;
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`STW_CALC: wb_write(0,res[31:0]);
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`ifdef SUPPORT_EM8
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`ifdef SUPPORT_EM8
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`STW_ACC8: dat_o <= {4{acc8}};
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`STW_ACC8: wb_write(1,{4{acc8}});
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`STW_X8: dat_o <= {4{x8}};
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`STW_X8: wb_write(1,{4{x8}});
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`STW_Y8: dat_o <= {4{y8}};
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`STW_Y8: wb_write(1,{4{y8}});
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`STW_Z8: dat_o <= {4{8'h00}};
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`STW_Z8: wb_write(1,{4{8'h00}});
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`STW_PC3124: dat_o <= {4{pc[31:24]}};
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`STW_PC3124: wb_write(1,{4{pc[31:24]}});
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`STW_PC2316: dat_o <= {4{pc[23:16]}};
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`STW_PC2316: wb_write(1,{4{pc[23:16]}});
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`STW_PC158: dat_o <= {4{pc[15:8]}};
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`STW_PC158: wb_write(1,{4{pc[15:8]}});
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`STW_PC70: dat_o <= {4{pc[7:0]}};
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`STW_PC70: wb_write(1,{4{pc[7:0]}});
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`STW_SR70: dat_o <= {4{sr8}};
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`STW_SR70: wb_write(1,{4{sr8}});
|
|
`STW_DEF8: wb_write(1,wdat);
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`endif
|
`endif
|
default: dat_o <= wdat;
|
default: wb_write(0,wdat);
|
endcase
|
endcase
|
`ifdef SUPPORT_DCACHE
|
`ifdef SUPPORT_DCACHE
|
radr <= wadr; // Do a cache read to test the hit
|
radr <= wadr; // Do a cache read to test the hit
|
`endif
|
`endif
|
state <= STORE2;
|
state <= STORE2;
|
end
|
end
|
|
|
// Terminal state for stores. Update the data cache if there was a cache hit.
|
// Terminal state for stores. Update the data cache if there was a cache hit.
|
// Clear any previously set lock status
|
// Clear any previously set lock status
|
STORE2:
|
STORE2:
|
if (ack_i) begin
|
// On a retry operation, restore the stack pointer which may have been
|
|
// modified, then go back to the decode state to pick up original
|
|
// addresses and data. This doesn't work for block move/store
|
|
if (rty_i) begin
|
|
wb_nack();
|
|
isp <= oisp;
|
|
state <= DECODE;
|
|
end
|
|
else if (ack_i) begin
|
wdat <= dat_o;
|
wdat <= dat_o;
|
if (isMove|isSts) begin
|
if (isMove|isSts) begin
|
state <= MVN3;
|
state <= MVN3;
|
retstate <= MVN3;
|
retstate <= MVN3;
|
end
|
end
|
| Line 91... |
Line 86... |
state <= IFETCH;
|
state <= IFETCH;
|
retstate <= IFETCH;
|
retstate <= IFETCH;
|
end
|
end
|
end
|
end
|
lock_o <= 1'b0;
|
lock_o <= 1'b0;
|
cyc_o <= 1'b0;
|
wb_nack();
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'h0;
|
|
dat_o <= 32'h0;
|
|
case(store_what)
|
case(store_what)
|
`STW_PC,`STW_PC2,`STW_PCHWI,`STW_OPC:
|
`STW_PC,`STW_PC2,`STW_PCHWI,`STW_OPC:
|
if (isBrk|isBusErr) begin
|
if (isBrk|isBusErr) begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
| Line 112... |
Line 102... |
`STW_SR:
|
`STW_SR:
|
if (isBrk|isBusErr) begin
|
if (isBrk|isBusErr) begin
|
load_what <= `PC_310;
|
load_what <= `PC_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
retstate <= LOAD_MAC1;
|
retstate <= LOAD_MAC1;
|
radr <= vect[31:2];
|
radr <= vect[33:2];
|
ttrig <= 1'b0;
|
ttrig <= 1'b0;
|
tf <= 1'b0; // turn off trace mode
|
tf <= 1'b0; // turn off trace mode
|
im <= 1'b1;
|
im <= 1'b1;
|
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
|
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
|
end
|
end
|
| Line 142... |
Line 132... |
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
store_what <= `STW_PC2316;
|
store_what <= `STW_PC2316;
|
sp <= sp_dec;
|
sp <= sp_dec;
|
|
retstate <= STORE1;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STW_PC2316:
|
`STW_PC2316:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
sp <= sp_dec;
|
sp <= sp_dec;
|
store_what <= `STW_PC158;
|
store_what <= `STW_PC158;
|
|
retstate <= STORE1;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STW_PC158:
|
`STW_PC158:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
sp <= sp_dec;
|
sp <= sp_dec;
|
store_what <= `STW_PC70;
|
store_what <= `STW_PC70;
|
|
retstate <= STORE1;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STW_PC70:
|
`STW_PC70:
|
begin
|
begin
|
case({1'b0,ir[7:0]})
|
case({1'b0,ir[7:0]})
|
| Line 174... |
Line 167... |
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
sp <= sp_dec;
|
sp <= sp_dec;
|
store_what <= `STW_SR70;
|
store_what <= `STW_SR70;
|
|
retstate <= STORE1;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`JSR: begin
|
`JSR: begin
|
pc <= ir[23:8];
|
pc[15:0] <= ir[23:8];
|
$display("setting pc=%h", ir[23:8]);
|
|
end
|
end
|
`JSL: begin
|
`JSL: begin
|
pc <= ir[39:8];
|
pc <= ir[39:8];
|
end
|
end
|
`JSR_INDX:
|
`JSR_INDX:
|
| Line 200... |
Line 193... |
if (ir[7:0]==`BRK) begin
|
if (ir[7:0]==`BRK) begin
|
load_what <= `PC_70;
|
load_what <= `PC_70;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
retstate <= LOAD_MAC1;
|
retstate <= LOAD_MAC1;
|
pc[31:16] <= abs8[31:16];
|
pc[31:16] <= abs8[31:16];
|
radr <= vect[31:2];
|
radr <= vect[33:2];
|
radr2LSB <= vect[1:0];
|
radr2LSB <= vect[1:0];
|
im <= hwi;
|
im <= hwi;
|
end
|
end
|
end
|
end
|
`endif
|
`endif
|
| Line 229... |
Line 222... |
`endif
|
`endif
|
end
|
end
|
`ifdef SUPPORT_BERR
|
`ifdef SUPPORT_BERR
|
else if (err_i) begin
|
else if (err_i) begin
|
lock_o <= 1'b0;
|
lock_o <= 1'b0;
|
cyc_o <= 1'b0;
|
wb_nack();
|
stb_o <= 1'b0;
|
if (em | isStb)
|
we_o <= 1'b0;
|
derr_address <= adr_o[31:0];
|
sel_o <= 4'h0;
|
else
|
dat_o <= 32'h0;
|
derr_address <= adr_o[33:2];
|
|
intno <= 9'd508;
|
state <= BUS_ERROR;
|
state <= BUS_ERROR;
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
