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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [ALU.v] - Diff between revs 6 and 8

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// ============================================================================
// ============================================================================
//  ALU
//  ALU
//  - perform datapath operations
//  - perform datapath operations
//
//
//
//
//  (C) 2009-2012  Robert Finch
//  (C) 2009-2013  Robert Finch
//  robfinch[remove]@opencores.org
//  robfinch[remove]@finitron.ca
//
//
//
//
// This source file is free software: you can redistribute it and/or modify 
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// by the Free Software Foundation, either version 3 of the License, or     
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        .divByZero(),
        .divByZero(),
        .done(div32_done)
        .done(div32_done)
);
);
 
 
 
 
always @(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT)
always @*       //(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT)
        begin
        begin
                casex(ir)
                casex(ir)
                `MOV_M2AL,`MOV_M2AX,`LDS,`LES:
                `MOV_M2AL,`MOV_M2AX,`LDS,`LES:
                        alu_o <= a;
                        alu_o <= a;
                `MOV_MR,`MOV_R2S,
                `MOV_MR,`MOV_R2S,
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                `XOR,`XOR_ALI8,`XOR_AXI16: alu_o <= a ^ b;
                `XOR,`XOR_ALI8,`XOR_AXI16: alu_o <= a ^ b;
                `CMP,`CMP_ALI8,`CMP_AXI16: alu_o <= a - b;
                `CMP,`CMP_ALI8,`CMP_AXI16: alu_o <= a - b;
                `SCASB,`SCASW,`CMPSB,`CMPSW: alu_o <= a - b;
                `SCASB,`SCASW,`CMPSB,`CMPSW: alu_o <= a - b;
                `INC_REG: alu_o <= a + 16'd1;
                `INC_REG: alu_o <= a + 16'd1;
                `DEC_REG: alu_o <= a - 16'd1;
                `DEC_REG: alu_o <= a - 16'd1;
                `IMUL: alu_o <= w ? p : wp[15:0];
//              `IMUL: alu_o <= w ? p : wp[15:0];
                `ALU_I2R8:
                `ALU_I2R8:
                        case(TTT)
                        case(TTT)
                        3'd0:   alu_o <= a + b;                 // ADD
                        3'd0:   alu_o <= a + b;                 // ADD
                        3'd1:   alu_o <= a | b;                 // OR
                        3'd1:   alu_o <= a | b;                 // OR
                        3'd2:   alu_o <= a + b + cf;    // ADC
                        3'd2:   alu_o <= a + b + cf;    // ADC
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                        3'd5:   alu_o <= a - b;                 // SUB
                        3'd5:   alu_o <= a - b;                 // SUB
                        3'd6:   alu_o <= a ^ b;                 // XOR
                        3'd6:   alu_o <= a ^ b;                 // XOR
                        default:        alu_o <= 16'h0000;
                        default:        alu_o <= 16'h0000;
                        endcase
                        endcase
                8'hF6,8'hF7:
                8'hF6,8'hF7:
 
                        begin
                        case(TTT)
                        case(TTT)
                        3'd0:   alu_o <= a & b;                 // TEST
                        3'd0:   alu_o <= a & b;                 // TEST
                        3'd2:   alu_o <= ~b;                    // NOT
                        3'd2:   alu_o <= ~b;                    // NOT
                        3'd3:   alu_o <= -b;                    // NEG
                        3'd3:   alu_o <= -b;                    // NEG
                        3'd4:   alu_o <= w ? p32[15:0] : p16;            // MUL
                        3'd4:   alu_o <= w ? p32[15:0] : p16;            // MUL
                        3'd5:   alu_o <= w ? wp[15:0] : p[15:0];  // IMUL
                        3'd5:   alu_o <= w ? wp[15:0] : p[15:0];  // IMUL
                        3'd6:   alu_o <= 16'h0000;              // DIV
                        3'd6:   alu_o <= 16'h0000;              // DIV
                        3'd7:   alu_o <= 16'h0000;              // IDIV
                        3'd7:   alu_o <= 16'h0000;              // IDIV
                        default:        alu_o <= 16'h0000;
                        default:        alu_o <= 16'h0000;
                        endcase
                        endcase
 
                        end
                `AAA:
                `AAA:
                        if (al[3:0]>4'h9 || af) begin
                        if (al[3:0]>4'h9 || af) begin
                                alu_o[3:0] <= al[3:0] + 4'd6;
                                alu_o[3:0] <= al[3:0] + 4'd6;
                                alu_o[7:4] <= 4'h0;
                                alu_o[7:4] <= 4'h0;
                                alu_o[15:8] <= ah + 8'd1;
                                alu_o[15:8] <= ah + 8'd1;

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