URL
https://opencores.org/ocsvn/rtf8088/rtf8088/trunk
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Rev 7 |
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//=============================================================================
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//=============================================================================
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// CMPSB
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// CMPSB
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//
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//
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//
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//
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// 2009-2012 Robert Finch
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// 2009-2013 Robert Finch
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// Stratford
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// Stratford
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// robfinch<remove>@opencores.org
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// robfinch<remove>@finitron.ca
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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//
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//
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//
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//
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//=============================================================================
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//=============================================================================
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//
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//
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CMPSB:
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CMPSB:
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`include "check_for_ints.v"
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begin
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else begin
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read(`CT_RDMEM,{seg_reg,`SEG_SHIFT} + si);
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cyc_type <= `CT_RDMEM;
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lock_o <= 1'b0;
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lock_o <= 1'b0;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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we_o <= 1'b0;
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adr_o <= {seg_reg,`SEG_SHIFT} + si;
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state <= CMPSB1;
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state <= CMPSB1;
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end
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end
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CMPSB1:
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CMPSB1:
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if (ack_i) begin
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if (ack_i) begin
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nack();
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state <= CMPSB2;
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state <= CMPSB2;
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`TERMINATE_CYCLE
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lock_o <= 1'b0;
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lock_o <= 1'b0;
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a[ 7:0] <= dat_i[7:0];
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a[ 7:0] <= dat_i[7:0];
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a[15:8] <= {8{dat_i[7]}};
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a[15:8] <= {8{dat_i[7]}};
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end
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end
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CMPSB2:
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CMPSB2:
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begin
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begin
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state <= CMPSB3;
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state <= CMPSB3;
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cyc_type <= `CT_RDMEM;
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read(`CT_RDMEM,esdi);
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lock_o <= 1'b0;
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lock_o <= 1'b0;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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we_o <= 1'b0;
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adr_o <= esdi;
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end
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end
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CMPSB3:
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CMPSB3:
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if (ack_i) begin
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if (ack_i) begin
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nack();
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state <= CMPSB4;
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state <= CMPSB4;
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`TERMINATE_CYCLE
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lock_o <= 1'b0;
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lock_o <= 1'b0;
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b[ 7:0] <= dat_i[7:0];
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b[ 7:0] <= dat_i[7:0];
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b[15:8] <= {8{dat_i[7]}};
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b[15:8] <= {8{dat_i[7]}};
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end
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end
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CMPSB4:
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CMPSB4:
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si <= si_inc;
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si <= si_inc;
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di <= di_inc;
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di <= di_inc;
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end
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end
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if ((repz & !cxz & zf) | (repnz & !cxz & !zf)) begin
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if ((repz & !cxz & zf) | (repnz & !cxz & !zf)) begin
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cx <= cx_dec;
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cx <= cx_dec;
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state <= CMPSB;
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ip <= ir_ip;
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state <= IFETCH;
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end
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end
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else
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else
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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