URL
https://opencores.org/ocsvn/rtf8088/rtf8088/trunk
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| Rev 6 |
Rev 7 |
| Line 47... |
Line 47... |
ld_div16 <= 1'b1;
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ld_div16 <= 1'b1;
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end
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end
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end
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end
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DIVIDE2:
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DIVIDE2:
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begin
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begin
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$display("DIVIDE2");
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ld_div32 <= 1'b0;
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ld_div32 <= 1'b0;
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ld_div16 <= 1'b0;
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ld_div16 <= 1'b0;
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state <= DIVIDE2a;
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state <= DIVIDE2a;
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end
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end
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DIVIDE2a:
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DIVIDE2a:
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begin
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begin
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$display("DIVIDE2a");
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if (w & div32_done)
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if (w & div32_done)
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state <= DIVIDE3;
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state <= DIVIDE3;
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else if (!w & div16_done)
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else if (!w & div16_done)
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state <= DIVIDE3;
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state <= DIVIDE3;
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end
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end
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// Assign results to registers
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// Assign results to registers
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// Trap on divider overflow
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// Trap on divider overflow
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DIVIDE3:
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DIVIDE3:
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begin
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begin
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$display("DIVIDE3 state <= IFETCH");
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state <= IFETCH;
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state <= IFETCH;
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if (w) begin
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if (w) begin
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ax <= q32[15:0];
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ax <= q32[15:0];
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dx <= r32[15:0];
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dx <= r32[15:0];
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if (TTT[0]) begin
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if (TTT[0]) begin
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if (q32[31:16]!={16{q32[15]}}) begin
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if (q32[31:16]!={16{q32[15]}}) begin
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$display("DIVIDE Overflow");
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int_num <= 8'h00;
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int_num <= 8'h00;
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state <= INT2;
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state <= INT2;
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end
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end
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end
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end
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else begin
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else begin
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if (q32[31:16]!=16'h0000) begin
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if (q32[31:16]!=16'h0000) begin
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$display("DIVIDE Overflow");
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int_num <= 8'h00;
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int_num <= 8'h00;
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state <= INT2;
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state <= INT2;
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end
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end
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end
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end
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end
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end
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else begin
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else begin
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ax[ 7:0] <= q16[7:0];
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ax[ 7:0] <= q16[7:0];
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ax[15:8] <= r16;
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ax[15:8] <= r16;
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if (TTT[0]) begin
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if (TTT[0]) begin
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if (q16[15:8]!={8{q16[7]}}) begin
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if (q16[15:8]!={8{q16[7]}}) begin
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$display("DIVIDE Overflow");
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int_num <= 8'h00;
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int_num <= 8'h00;
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state <= INT2;
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state <= INT2;
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end
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end
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end
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end
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else begin
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else begin
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if (q16[15:8]!=8'h00) begin
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if (q16[15:8]!=8'h00) begin
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$display("DIVIDE Overflow");
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int_num <= 8'h00;
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int_num <= 8'h00;
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state <= INT2;
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state <= INT2;
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end
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end
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end
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end
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end
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end
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