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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [FETCH_DISP16.v] - Diff between revs 2 and 8
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Rev 8 |
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Line 1... |
// ============================================================================
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// ============================================================================
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// FETCH_DISP16
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// FETCH_DISP16
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// - detch 16 bit displacement
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// - detch 16 bit displacement
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//
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//
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//
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//
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// 2009-2012 Robert Finch
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// 2009-2013 Robert Finch
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// robfinch[remove]@opencores.org
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// robfinch[remove]@finitron.ca
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// Stratford
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// Stratford
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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Line 27... |
// Fetch 16 bit displacement
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// Fetch 16 bit displacement
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// ============================================================================
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// ============================================================================
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//
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//
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FETCH_DISP16:
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FETCH_DISP16:
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begin
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begin
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`INITIATE_CODE_READ;
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code_read();
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state <= FETCH_DISP16_ACK;
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state <= FETCH_DISP16_ACK;
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end
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end
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FETCH_DISP16_ACK:
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FETCH_DISP16_ACK:
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if (ack_i) begin
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if (ack_i) begin
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state <= FETCH_DISP16a;
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state <= FETCH_DISP16a;
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`PAUSE_CODE_READ
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pause_code_read();
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disp16[7:0] <= dat_i;
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disp16[7:0] <= dat_i;
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end
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end
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FETCH_DISP16a:
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FETCH_DISP16a:
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begin
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begin
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state <= FETCH_DISP16a_ACK;
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state <= FETCH_DISP16a_ACK;
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`INITIATE_CODE_READ
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code_read();
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end
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end
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FETCH_DISP16a_ACK:
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FETCH_DISP16a_ACK:
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if (ack_i) begin
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if (ack_i) begin
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state <= FETCH_DISP16b;
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state <= FETCH_DISP16b;
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`TERMINATE_CODE_READ
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term_code_read();
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disp16[15:8] <= dat_i;
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disp16[15:8] <= dat_i;
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end
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end
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FETCH_DISP16b:
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FETCH_DISP16b:
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casex(ir)
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casex(ir)
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