| Line 29... |
Line 29... |
// $4100000 - the second 4MiB of RAM
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// $4100000 - the second 4MiB of RAM
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//
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//
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//
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//
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// Verilog 1995
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// Verilog 1995
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//
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//
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// ref: XC6SLX45-3
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// 600 LUTs / 2 BRAMs / 410 FF's
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// 150 MHz
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// ============================================================================
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// ============================================================================
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module rtfBitmapController(
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module rtfBitmapController(
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rst_i, s_clk_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i, s_adr_i, s_dat_i, s_dat_o, irq_o,
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rst_i, s_clk_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i, s_adr_i, s_dat_i, s_dat_o, irq_o,
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clk_i, bte_o, cti_o, bl_o, cyc_o, stb_o, ack_i, we_o, sel_o, adr_o, dat_i, dat_o,
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clk_i, bte_o, cti_o, bl_o, cyc_o, stb_o, ack_i, we_o, sel_o, adr_o, dat_i, dat_o,
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| Line 119... |
Line 122... |
reg [11:0] hDisplayed,vDisplayed;
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reg [11:0] hDisplayed,vDisplayed;
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reg [33:0] bm_base_addr1,bm_base_addr2;
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reg [33:0] bm_base_addr1,bm_base_addr2;
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reg [1:0] color_depth;
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reg [1:0] color_depth;
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wire [8:0] fifo_cnt;
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wire [8:0] fifo_cnt;
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reg onoff;
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reg onoff;
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reg [5:0] Bpp; // bits per pixel, 8,16, or 32
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reg [1:0] vbl; // video burst length
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reg [1:0] hres,vres;
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reg [1:0] hres,vres;
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reg greyscale;
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reg page;
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reg page;
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reg pals; // palette select
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reg [11:0] hrefdelay;
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reg [11:0] hrefdelay;
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reg [11:0] vrefdelay;
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reg [11:0] vrefdelay;
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reg [11:0] hctr; // horizontal reference counter
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reg [11:0] hctr; // horizontal reference counter
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wire [11:0] hctr1 = hctr - hrefdelay;
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wire [11:0] hctr1 = hctr - hrefdelay;
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reg [11:0] vctr; // vertical reference counter
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reg [11:0] vctr; // vertical reference counter
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| Line 138... |
Line 143... |
wire [31:0] pal_o;
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wire [31:0] pal_o;
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always @(page or bm_base_addr1 or bm_base_addr2)
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always @(page or bm_base_addr1 or bm_base_addr2)
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baseAddr = page ? bm_base_addr2 : bm_base_addr1;
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baseAddr = page ? bm_base_addr2 : bm_base_addr1;
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// Color palette RAM for 8bpp modes
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syncRam512x32_1rw1r upal1
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syncRam512x32_1rw1r upal1
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(
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(
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.wrst(1'b0),
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.wrst(1'b0),
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.wclk(s_clk_i),
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.wclk(s_clk_i),
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.wce(cs & s_adr_i[13]),
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.wce(cs & s_adr_i[13]),
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| Line 150... |
Line 156... |
.i(s_dat_i),
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.i(s_dat_i),
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.wo(pal_wo),
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.wo(pal_wo),
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.rrst(1'b0),
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.rrst(1'b0),
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.rclk(vclk),
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.rclk(vclk),
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.rce(1'b1),
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.rce(1'b1),
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.radr({1'b0,rgbo4[7:0]}),
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.radr({pals,rgbo4[7:0]}),
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.o(pal_o)
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.o(pal_o)
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);
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);
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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always @(posedge s_clk_i)
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always @(posedge s_clk_i)
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if (rst_i) begin
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if (rst_i) begin
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page <= 1'b0;
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page <= 1'b0;
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hres <= 2'b11;
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pals <= 1'b0;
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vres <= 2'b11;
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hres <= 2'b01;
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hDisplayed <= 12'd340;
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vres <= 2'b01;
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vDisplayed <= 12'd192;
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hDisplayed <= 12'd680;
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vDisplayed <= 12'd384;
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onoff <= 1'b1;
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onoff <= 1'b1;
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vbl <= 2'b11;
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color_depth <= 2'b00;
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color_depth <= 2'b00;
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greyscale <= 1'b0;
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bm_base_addr1 <= {BM_BASE_ADDR1,2'b00};
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bm_base_addr1 <= {BM_BASE_ADDR1,2'b00};
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bm_base_addr2 <= {BM_BASE_ADDR2,2'b00};
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bm_base_addr2 <= {BM_BASE_ADDR2,2'b00};
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hrefdelay <= 12'd218;
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hrefdelay <= 12'd218;
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vrefdelay <= 12'd27;
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vrefdelay <= 12'd27;
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end
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end
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| Line 177... |
Line 186... |
if (s_we_i) begin
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if (s_we_i) begin
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casex(s_adr_i[13:2])
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casex(s_adr_i[13:2])
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REG_CTRL:
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REG_CTRL:
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begin
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begin
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onoff <= s_dat_i[0];
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onoff <= s_dat_i[0];
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vbl <= s_dat_i[8:7];
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color_depth <= s_dat_i[10:9];
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color_depth <= s_dat_i[10:9];
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greyscale <= s_dat_i[11];
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hres <= s_dat_i[17:16];
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hres <= s_dat_i[17:16];
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vres <= s_dat_i[19:18];
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vres <= s_dat_i[19:18];
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end
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end
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REG_CTRL2:
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REG_CTRL2:
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begin
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begin
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page <= s_dat_i[16];
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page <= s_dat_i[16];
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pals <= s_dat_i[17];
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end
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end
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REG_HDISPLAYED: hDisplayed <= s_dat_i[11:0];
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REG_HDISPLAYED: hDisplayed <= s_dat_i[11:0];
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REG_VDISPLAYED: vDisplayed <= s_dat_i[11:0];
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REG_VDISPLAYED: vDisplayed <= s_dat_i[11:0];
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REG_PAGE1ADDR: bm_base_addr1 <= {s_dat_i,2'b00};
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REG_PAGE1ADDR: bm_base_addr1 <= {s_dat_i,2'b00};
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REG_PAGE2ADDR: bm_base_addr2 <= {s_dat_i,2'b00};
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REG_PAGE2ADDR: bm_base_addr2 <= {s_dat_i,2'b00};
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| Line 200... |
Line 212... |
end
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end
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casex(s_adr_i[13:2])
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casex(s_adr_i[13:2])
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REG_CTRL:
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REG_CTRL:
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begin
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begin
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s_dat_o[0] <= onoff;
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s_dat_o[0] <= onoff;
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s_dat_o[8:7] <= vbl;
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s_dat_o[10:9] <= color_depth;
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s_dat_o[10:9] <= color_depth;
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s_dat_o[11] <= greyscale;
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s_dat_o[17:16] <= hres;
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s_dat_o[17:16] <= hres;
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s_dat_o[19:18] <= vres;
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s_dat_o[19:18] <= vres;
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end
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end
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REG_CTRL2:
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REG_CTRL2:
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begin
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begin
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s_dat_o[16] <= page;
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s_dat_o[16] <= page;
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s_dat_o[17] <= pals;
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end
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end
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REG_HDISPLAYED: s_dat_o <= hDisplayed;
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REG_HDISPLAYED: s_dat_o <= hDisplayed;
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REG_VDISPLAYED: s_dat_o <= vDisplayed;
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REG_VDISPLAYED: s_dat_o <= vDisplayed;
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REG_PAGE1ADDR: s_dat_o <= bm_base_addr1;
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REG_PAGE1ADDR: s_dat_o <= bm_base_addr1;
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REG_PAGE2ADDR: s_dat_o <= bm_base_addr2;
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REG_PAGE2ADDR: s_dat_o <= bm_base_addr2;
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| Line 243... |
Line 258... |
else if (hSyncEdge) vctr <= vctr + 1;
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else if (hSyncEdge) vctr <= vctr + 1;
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// Pixel row and column are derived from the horizontal and vertical counts.
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// Pixel row and column are derived from the horizontal and vertical counts.
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always @(vctr1)
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always @(posedge vclk)
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case(vres)
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case(vres)
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2'b00: pixelRow <= vctr1[11:0];
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2'b00: pixelRow <= vctr1[11:0];
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2'b01: pixelRow <= vctr1[11:1];
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2'b01: pixelRow <= vctr1[11:1];
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2'b10: pixelRow <= vctr1[11:2];
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2'b10: pixelRow <= vctr1[11:2];
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default: pixelRow <= vctr1[11:2];
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default: pixelRow <= vctr1[11:2];
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| Line 258... |
Line 273... |
2'b01: pixelCol = hctr1[11:1];
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2'b01: pixelCol = hctr1[11:1];
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2'b10: pixelCol = hctr1[11:2];
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2'b10: pixelCol = hctr1[11:2];
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default: pixelCol = hctr1[11:2];
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default: pixelCol = hctr1[11:2];
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endcase
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endcase
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wire vFetch = vctr1 < vDisplayed;
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wire vFetch = pixelRow < vDisplayed;
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wire fifo_rst = hctr[11:4]==8'h00;
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wire fifo_rst = hctr[11:4]==8'h00;
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wire[23:0] rowOffset = pixelRow * hDisplayed;
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wire[23:0] rowOffset = pixelRow * hDisplayed;
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reg [11:0] fetchCol;
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reg [11:0] fetchCol;
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// The following bypasses loading the fifo when all the pixels from a scanline
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// are buffered in the fifo and the pixel row doesn't change. Since the fifo
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// pointers are reset at the beginning of a scanline, the fifo can be used like
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// a cache.
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wire blankEdge;
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edge_det ed2(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(blank), .pe(blankEdge), .ne(), .ee() );
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reg do_loads;
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reg [11:0] opixelRow;
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reg load_fifo;
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always @(posedge clk_i)
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load_fifo <= fifo_cnt < 9'd500 && vFetch && onoff && xonoff && fetchCol < hDisplayed && !cyc_o && do_loads;
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always @(posedge clk_i)
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if (!(hDisplayed < (12'd2048 >> color_depth)))
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do_loads <= 1'b1;
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else if (pixelRow != opixelRow)
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do_loads <= 1'b1;
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else if (blankEdge)
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do_loads <= 1'b0;
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// - read from assigned video memory address, using burst mode reads
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// - read from assigned video memory address, using burst mode reads
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// - 64 pixels at a time are read
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// - 32 bytes (8 words) at a time are read
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// - video data is fetched one pixel row in advance
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//
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//
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reg [5:0] bcnt;
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reg [5:0] bcnt;
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wire [5:0] bcnt_inc = bcnt + 6'd1;
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wire [5:0] bcnt_inc = bcnt + 6'd1;
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reg [33:0] adr;
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reg [33:0] adr;
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i) begin
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if (rst_i) begin
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wb_nack();
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wb_nack();
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fetchCol <= 12'd0;
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fetchCol <= 12'd0;
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bcnt <= 6'd0;
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bcnt <= 6'd0;
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opixelRow <= 12'hFFF;
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end
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end
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else begin
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else begin
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if (fifo_rst) begin
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if (fifo_rst) begin
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fetchCol <= 12'd0;
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fetchCol <= 12'd0;
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adr <= baseAddr + rowOffset;
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adr <= baseAddr + rowOffset;
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opixelRow <= pixelRow;
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end
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end
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else if (fifo_cnt < 9'd500 && vFetch && onoff && xonoff && fetchCol < hDisplayed && !cyc_o) begin
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else if (load_fifo) begin
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cti_o <= 3'b001; // constant address burst
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cti_o <= vbl==2'b00 ? 3'b000 : 3'b001; // constant address burst
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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sel_o <= 4'b1111;
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sel_o <= 4'b1111;
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bcnt <= 6'd0;
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bcnt <= 6'd0;
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bl_o <= 6'd7;
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case(vbl)
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2'b00: bl_o <= 6'd0;
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2'b01: bl_o <= 6'd1;
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2'b10: bl_o <= 6'd3;
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2'b11: bl_o <= 6'd7;
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endcase
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adr_o <= adr;
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adr_o <= adr;
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end
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end
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if (cyc_o & ack_i) begin
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if (cyc_o & ack_i) begin
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case(color_depth)
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case(color_depth)
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2'b00: fetchCol <= fetchCol + 12'd4;
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2'b00: fetchCol <= fetchCol + 12'd4;
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| Line 326... |
Line 366... |
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reg [11:0] pixelColD1;
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reg [11:0] pixelColD1;
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reg [31:0] rgbo2,rgbo3,rgbo4;
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reg [31:0] rgbo2,rgbo3,rgbo4;
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always @(posedge vclk)
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always @(posedge vclk)
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if (color_depth==2'b00)
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if (color_depth==2'b00)
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rgbo4 <= rgbo2;
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rgbo4 <= greyscale ? {3{rgbo2[7:0]}} : rgbo2;
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else if (color_depth==2'b01)
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else if (color_depth==2'b01)
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rgbo4 <= {rgbo3[14:10],3'b0,rgbo3[9:5],3'b0,rgbo3[4:0],3'b0};
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rgbo4 <= {rgbo3[14:10],3'b0,rgbo3[9:5],3'b0,rgbo3[4:0],3'b0};
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else
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else
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rgbo4 <= rgbo1;
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rgbo4 <= rgbo1;
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| Line 341... |
Line 381... |
if (rd_fifo1)
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if (rd_fifo1)
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de <= ~blank;
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de <= ~blank;
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always @(posedge vclk)
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always @(posedge vclk)
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if (onoff & xonoff & de) begin
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if (onoff & xonoff & de) begin
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if (color_depth==2'b00)
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if (color_depth==2'b00 && !greyscale)
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rgbo <= pal_o;
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rgbo <= pal_o;
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else
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else
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rgbo <= rgbo4;
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rgbo <= rgbo4;
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end
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end
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else
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else
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