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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// Bitmap Controller (416h x 262v x 8bpp):
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// Bitmap Controller
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// - Displays a bitmap from memory.
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// - Displays a bitmap from memory.
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// - the video mode timing to be 1680x1050
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//
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//
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//
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//
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// (C) 2008,2010,2011 Robert Finch
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// __
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// robfinch<remove>@opencores.org
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// \\__/ o\ (C) 2008-2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// The default base screen address is:
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// The default base screen address is:
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// $20000 - the second 128 kb of RAM
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// $4100000 - the second 4MiB of RAM
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//
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//
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//
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//
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// Verilog 1995
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// Verilog 1995
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// Webpack 9.2i xc3s1200-4fg320
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// 64 slices / 118 LUTs / 175.009 MHz
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// 72 ff's / 2 BRAM (2048x16)
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//
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//
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// ============================================================================
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// ============================================================================
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module rtfBitmapController(
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module rtfBitmapController(
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rst_i, clk_i, bte_o, cti_o, cyc_o, stb_o, ack_i, we_o, sel_o, adr_o, dat_i, dat_o,
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rst_i, s_clk_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i, s_adr_i, s_dat_i, s_dat_o, irq_o,
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vclk, eol, eof, blank, rgbo, page
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clk_i, bte_o, cti_o, bl_o, cyc_o, stb_o, ack_i, we_o, sel_o, adr_o, dat_i, dat_o,
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vclk, hSync, vSync, blank, rgbo, xonoff
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);
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);
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parameter BM_BASE_ADDR1 = 44'h000_0002_0000;
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parameter pIOAddress = 32'hFFDC5000;
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parameter BM_BASE_ADDR2 = 44'h000_0004_0000;
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parameter BM_BASE_ADDR1 = 32'h0410_0000;
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parameter BM_BASE_ADDR2 = 32'h0420_0000;
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parameter REG_CTRL = 12'd0;
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parameter REG_CTRL2 = 12'd1;
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parameter REG_HDISPLAYED = 12'd2;
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parameter REG_VDISPLAYED = 12'd3;
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parameter REG_PAGE1ADDR = 12'd5;
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parameter REG_PAGE2ADDR = 12'd6;
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parameter REG_REFDELAY = 12'd7;
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// SYSCON
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// SYSCON
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input rst_i; // system reset
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input rst_i; // system reset
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input clk_i; // system bus interface clock
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// Peripheral slave port
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input s_clk_i;
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input s_cyc_i;
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input s_stb_i;
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output s_ack_o;
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input s_we_i;
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input [33:0] s_adr_i;
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input [31:0] s_dat_i;
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output [31:0] s_dat_o;
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reg [31:0] s_dat_o;
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output irq_o;
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// Video Master Port
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// Video Master Port
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// Used to read memory via burst access
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// Used to read memory via burst access
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input clk_i; // system bus interface clock
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output [1:0] bte_o;
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output [1:0] bte_o;
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output [2:0] cti_o;
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output [2:0] cti_o;
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output [5:0] bl_o;
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output cyc_o; // video burst request
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output cyc_o; // video burst request
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output stb_o;
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output stb_o;
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input ack_i; // vid_acknowledge from memory
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input ack_i; // vid_acknowledge from memory
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output we_o;
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output we_o;
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output [ 1:0] sel_o;
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output [ 3:0] sel_o;
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output [43:0] adr_o; // address for memory access
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output [33:0] adr_o; // address for memory access
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input [15:0] dat_i; // memory data input
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input [31:0] dat_i; // memory data input
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output [15:0] dat_o;
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output [31:0] dat_o;
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// Video
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// Video
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input vclk; // Video clock 73.529 MHz
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input vclk; // Video clock 85.71 MHz
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input eol; // end of scan line
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input hSync; // start/end of scan line
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input eof; // end of frame
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input vSync; // start/end of frame
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input blank; // blank the output
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input blank; // blank the output
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output [7:0] rgbo; // 8-bit RGB output
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output [23:0] rgbo; // 8-bit RGB output
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reg [7:0] rgbo;
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reg [23:0] rgbo;
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input page; // which page to display
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input xonoff;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// IO registers
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// IO registers
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [1:0] bte_o;
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reg [1:0] bte_o;
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reg [2:0] cti_o;
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reg [2:0] cti_o;
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reg [5:0] bl_o;
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reg sync_o;
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reg cyc_o;
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reg cyc_o;
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reg stb_o;
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reg stb_o;
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reg we_o;
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reg we_o;
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reg [1:0] sel_o;
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reg [3:0] sel_o;
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reg [43:0] adr_o;
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reg [33:0] adr_o;
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reg [15:0] dat_o;
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reg [31:0] dat_o;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire cs = s_cyc_i && s_stb_i && (s_adr_i[33:14]==pIOAddress[31:12]);
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reg ack,ack1;
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always @(posedge clk_i)
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begin
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ack1 <= cs;
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ack <= ack1 & cs;
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end
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assign s_ack_o = cs ? (s_we_i ? 1'b1 : ack) : 1'b0;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire [11:0] hctr; // horizontal reference counter
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reg [11:0] hDisplayed,vDisplayed;
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wire [11:0] vctr; // vertical reference counter
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reg [33:0] bm_base_addr1,bm_base_addr2;
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wire [11:0] vctr1 = vctr + 12'd4;
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reg [1:0] color_depth;
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reg [43:0] baseAddr; // base address register
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wire [8:0] fifo_cnt;
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wire [7:0] rgbo1;
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reg onoff;
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reg [5:0] Bpp; // bits per pixel, 8,16, or 32
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reg [1:0] hres,vres;
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reg page;
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reg [11:0] hrefdelay;
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reg [11:0] vrefdelay;
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reg [11:0] hctr; // horizontal reference counter
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wire [11:0] hctr1 = hctr - hrefdelay;
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reg [11:0] vctr; // vertical reference counter
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wire [11:0] vctr1 = vctr - vrefdelay;
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reg [33:0] baseAddr; // base address register
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wire [31:0] rgbo1;
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reg [11:0] pixelRow;
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reg [11:0] pixelRow;
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reg [11:0] pixelCol;
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reg [11:0] pixelCol;
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wire [31:0] pal_wo;
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wire [31:0] pal_o;
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always @(page or bm_base_addr1 or bm_base_addr2)
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baseAddr = page ? bm_base_addr2 : bm_base_addr1;
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syncRam512x32_1rw1r upal1
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(
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.wrst(1'b0),
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.wclk(s_clk_i),
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.wce(cs & s_adr_i[13]),
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.we(s_we_i),
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.wadr(s_adr_i[10:2]),
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.i(s_dat_i),
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.wo(pal_wo),
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.rrst(1'b0),
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.rclk(vclk),
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.rce(1'b1),
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.radr({1'b0,rgbo4[7:0]}),
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.o(pal_o)
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);
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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always @(posedge s_clk_i)
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if (rst_i) begin
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page <= 1'b0;
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hres <= 2'b11;
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vres <= 2'b11;
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hDisplayed <= 12'd340;
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vDisplayed <= 12'd192;
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onoff <= 1'b1;
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color_depth <= 2'b00;
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bm_base_addr1 <= {BM_BASE_ADDR1,2'b00};
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bm_base_addr2 <= {BM_BASE_ADDR2,2'b00};
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hrefdelay <= 12'd218;
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vrefdelay <= 12'd27;
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end
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else begin
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if (cs) begin
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if (s_we_i) begin
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casex(s_adr_i[13:2])
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REG_CTRL:
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begin
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onoff <= s_dat_i[0];
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color_depth <= s_dat_i[10:9];
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hres <= s_dat_i[17:16];
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vres <= s_dat_i[19:18];
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end
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REG_CTRL2:
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begin
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page <= s_dat_i[16];
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end
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REG_HDISPLAYED: hDisplayed <= s_dat_i[11:0];
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REG_VDISPLAYED: vDisplayed <= s_dat_i[11:0];
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REG_PAGE1ADDR: bm_base_addr1 <= {s_dat_i,2'b00};
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REG_PAGE2ADDR: bm_base_addr2 <= {s_dat_i,2'b00};
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REG_REFDELAY:
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begin
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hrefdelay <= s_dat_i[11:0];
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vrefdelay <= s_dat_i[27:16];
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end
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endcase
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end
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casex(s_adr_i[13:2])
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REG_CTRL:
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begin
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s_dat_o[0] <= onoff;
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s_dat_o[10:9] <= color_depth;
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s_dat_o[17:16] <= hres;
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s_dat_o[19:18] <= vres;
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end
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REG_CTRL2:
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begin
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s_dat_o[16] <= page;
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end
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REG_HDISPLAYED: s_dat_o <= hDisplayed;
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REG_VDISPLAYED: s_dat_o <= vDisplayed;
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REG_PAGE1ADDR: s_dat_o <= bm_base_addr1;
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REG_PAGE2ADDR: s_dat_o <= bm_base_addr2;
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REG_REFDELAY: s_dat_o <= {vrefdelay,4'h0,hrefdelay};
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12'b100x_xxxx_xxxx: s_dat_o <= pal_wo;
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endcase
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end
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else
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s_dat_o <= 32'd0;
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end
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always @(page)
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assign irq_o = 1'b0;
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baseAddr = page ? BM_BASE_ADDR2 : BM_BASE_ADDR1;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Horizontal and Vertical timing reference counters
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// Horizontal and Vertical timing reference counters
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// - The memory fetch address is determined from these counters.
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// - The memory fetch address is determined from these counters.
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// - The counters are setup with negative values so that the zero
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// point coincides with the top left of the display.
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire hSyncEdge, vSyncEdge;
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edge_det ed0(.rst(rst_i), .clk(vclk), .ce(1'b1), .i(hSync), .pe(hSyncEdge), .ne(), .ee() );
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edge_det ed1(.rst(rst_i), .clk(vclk), .ce(1'b1), .i(vSync), .pe(vSyncEdge), .ne(), .ee() );
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counter #(12) u1 (.rst(1'b0), .clk(vclk), .ce(1'b1), .ld(eol), .d(12'hEE4), .q(hctr));
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always @(posedge vclk)
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counter #(12) u2 (.rst(1'b0), .clk(vclk), .ce(eol), .ld(eof), .d(12'hFDC), .q(vctr));
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if (rst_i) hctr <= 1;
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else if (hSyncEdge) hctr <= 1;
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else hctr <= hctr + 1;
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always @(posedge vclk)
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if (rst_i) vctr <= 1;
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else if (vSyncEdge) vctr <= 1;
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else if (hSyncEdge) vctr <= vctr + 1;
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// Pixel row and column are derived from the horizontal and vertical counts.
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// Pixel row and column are derived from the horizontal and vertical counts.
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always @(vctr1)
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always @(vctr1)
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pixelRow = vctr1[11:2];
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case(vres)
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always @(hctr)
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2'b00: pixelRow <= vctr1[11:0];
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pixelCol = hctr[11:1];
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2'b01: pixelRow <= vctr1[11:1];
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2'b10: pixelRow <= vctr1[11:2];
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default: pixelRow <= vctr1[11:2];
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wire vFetch = (vctr < 12'd1050) || (vctr > 12'hFF8);
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endcase
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always @(hctr1)
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// Video Request Block
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case(hres)
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// 416x262
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2'b00: pixelCol = hctr1[11:0];
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// - Issue a request for access to memory every 160 clock cycles
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2'b01: pixelCol = hctr1[11:1];
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// - Reset the request flag once an access has been initiated.
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2'b10: pixelCol = hctr1[11:2];
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// - 128 bytes (pixels) are read per scan line
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default: pixelCol = hctr1[11:2];
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// - It takes about 18 clock cycles @ 25 MHz to access 32 bytes of data
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endcase
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// through the memory contoller, or about 53 video clocks
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// 83 video clocks with a 16 MHZ memory controller.
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reg [2:0] vreq;
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// Must be vclk. vid_req will be active for numerous clock cycles as
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// a burst type fetch is used. The ftch and vFetch may only be
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// active for a single video clock cycle. vclk must be used so these
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// signals are not missed due to a clock domain crossing. We luck
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// out here because of the length of time vid_req is active.
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//
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always @(posedge vclk)
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begin
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if (vFetch) begin
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if (vctr1[1:0]!=2'd3) begin // we only need 13 memory accesses
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if (hctr==12'd16) vreq <= 3'b100;
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if (hctr==12'd176) vreq <= 3'b101;
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if (hctr==12'd336) vreq <= 3'b110;
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if (hctr==12'd496) vreq <= 3'b111;
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end
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else
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if (hctr==12'd16) vreq <= 3'b100;
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end
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if (cyc_o) vreq <= 3'b000;
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end
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// Cross the clock domain with the request signal
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wire vFetch = vctr1 < vDisplayed;
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reg do_cyc;
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wire fifo_rst = hctr[11:4]==8'h00;
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always @(posedge clk_i)
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do_cyc <= vreq[2];
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wire[19:0] rowOffset = pixelRow * 10'd416;
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wire[23:0] rowOffset = pixelRow * hDisplayed;
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reg [8:0] fetchCol;
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reg [11:0] fetchCol;
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// - read from assigned video memory address, using burst mode reads
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// - read from assigned video memory address, using burst mode reads
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// - 32 pixels at a time are read
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// - 64 pixels at a time are read
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// - video data is fetched one pixel row in advance
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// - video data is fetched one pixel row in advance
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//
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//
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reg [3:0] bcnt;
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reg [5:0] bcnt;
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wire [5:0] bcnt_inc = bcnt + 6'd1;
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reg [33:0] adr;
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i) begin
|
if (rst_i) begin
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bte_o <= 2'b00; // linear burst
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wb_nack();
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cti_o <= 3'b000; // classic cycle
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fetchCol <= 12'd0;
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cyc_o <= 1'b0;
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bcnt <= 6'd0;
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stb_o <= 1'b0;
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sel_o <= 2'b00;
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we_o <= 1'b0;
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adr_o <= 44'h000_0000_0000;
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dat_o <= 16'h0000;
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fetchCol <= 9'd0;
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bcnt <= 4'd0;
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end
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end
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else begin
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else begin
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if (do_cyc & !cyc_o) begin
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if (fifo_rst) begin
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cti_o <= 3'b010; // incrementing burst cycle
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fetchCol <= 12'd0;
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adr <= baseAddr + rowOffset;
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end
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else if (fifo_cnt < 9'd500 && vFetch && onoff && xonoff && fetchCol < hDisplayed && !cyc_o) begin
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cti_o <= 3'b001; // constant address burst
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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sel_o <= 2'b11;
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sel_o <= 4'b1111;
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bcnt <= 4'd0;
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bcnt <= 6'd0;
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fetchCol <= {vctr1[1:0],vreq[1:0],5'h00};
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bl_o <= 6'd7;
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// This works out to be an even multiple of 32 bytes
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adr_o <= adr;
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adr_o <= baseAddr + rowOffset + 10'd416 + {vctr1[1:0],vreq[1:0],5'h00};
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end
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end
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if (cyc_o & ack_i) begin
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if (cyc_o & ack_i) begin
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adr_o <= adr_o + 32'd2;
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case(color_depth)
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fetchCol <= fetchCol + 9'd2;
|
2'b00: fetchCol <= fetchCol + 12'd4;
|
bcnt <= bcnt + 4'd1;
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2'b01: fetchCol <= fetchCol + 12'd2;
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if (bcnt==4'd14)
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2'b11: fetchCol <= fetchCol + 12'd1;
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default: fetchCol <= 12'hFF0;
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endcase
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bcnt <= bcnt_inc;
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if (bl_o==bcnt_inc)
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cti_o <= 3'b111; // end of burst
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cti_o <= 3'b111; // end of burst
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if (bcnt==4'd15) begin
|
else if (bl_o==bcnt) begin
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cti_o <= 3'b000; // classic cycles again
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wb_nack();
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cyc_o <= 1'b0;
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adr <= adr + 34'd32;
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stb_o <= 1'b0;
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sel_o <= 2'b00;
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adr_o <= 44'h000_0000_0000;
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end
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end
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end
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end
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end
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end
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|
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task wb_nack;
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begin
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|
bte_o <= 2'b00; // linear burst
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cti_o <= 3'b000; // classic cycle
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bl_o <= 6'd0;
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cyc_o <= 1'b0;
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|
stb_o <= 1'b0;
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|
sel_o <= 4'b0000;
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|
we_o <= 1'b0;
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|
adr_o <= 34'h0000_0000;
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|
dat_o <= 32'h0000_0000;
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|
end
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|
endtask
|
|
|
|
reg [11:0] pixelColD1;
|
|
reg [31:0] rgbo2,rgbo3,rgbo4;
|
always @(posedge vclk)
|
always @(posedge vclk)
|
rgbo <= rgbo1;
|
if (color_depth==2'b00)
|
|
rgbo4 <= rgbo2;
|
|
else if (color_depth==2'b01)
|
|
rgbo4 <= {rgbo3[14:10],3'b0,rgbo3[9:5],3'b0,rgbo3[4:0],3'b0};
|
|
else
|
|
rgbo4 <= rgbo1;
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
// Video Line Buffer
|
|
// - gets written in bursts, but read continuously
|
|
// - buffer is used as two halves - one half is displayed (read) while
|
|
// the other is fetched (write).
|
|
// - only the lower eleven bits of the address are used as an index,
|
|
// these bits will match with the addresses generated by the burst
|
|
// controller above.
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
// Storage for 2048x8 bit pixels (2048x8 data)
|
reg rd_fifo,rd_fifo1,rd_fifo2;
|
|
reg de;
|
|
always @(posedge vclk)
|
|
if (rd_fifo1)
|
|
de <= ~blank;
|
|
|
|
always @(posedge vclk)
|
|
if (onoff & xonoff & de) begin
|
|
if (color_depth==2'b00)
|
|
rgbo <= pal_o;
|
|
else
|
|
rgbo <= rgbo4;
|
|
end
|
|
else
|
|
rgbo <= 24'd0;
|
|
|
|
wire vrd;
|
|
always @(posedge vclk) pixelColD1 <= pixelCol;
|
|
always @(posedge vclk)
|
|
if (pixelCol < hDisplayed + 12'd8)
|
|
case({color_depth,hres})
|
|
4'b0000: rd_fifo1 <= hctr[1:0]==2'b00; // 4 clocks
|
|
4'b0001: rd_fifo1 <= hctr[2:0]==3'b000; // 8 clocks
|
|
4'b0010: rd_fifo1 <= hctr[3:0]==4'b0000; // 16 clocks
|
|
4'b0011: rd_fifo1 <= hctr[3:0]==4'b0000; // unsupported
|
|
4'b0100: rd_fifo1 <= hctr[0]==1'b0; // 2 clocks
|
|
4'b0101: rd_fifo1 <= hctr[1:0]==2'b00; // 4 clocks
|
|
4'b0110: rd_fifo1 <= hctr[2:0]==3'b000; // 8 clocks (twice as often as a byte)
|
|
4'b0111: rd_fifo1 <= hctr[2:0]==3'b000;
|
|
4'b1000: rd_fifo1 <= 1'b0;
|
|
4'b1001: rd_fifo1 <= 1'b0;
|
|
4'b1010: rd_fifo1 <= 1'b0;
|
|
4'b1011: rd_fifo1 <= 1'b0;
|
|
4'b1100: rd_fifo1 <= 1'b1;
|
|
4'b1101: rd_fifo1 <= hctr[0]==1'b0;
|
|
4'b1110: rd_fifo1 <= hctr[1:0]==2'b00;
|
|
4'b1111: rd_fifo1 <= hctr[1:0]==2'b00;
|
|
endcase
|
|
reg shift,shift1,shift2;
|
|
always @(posedge vclk)
|
|
if (pixelCol < hDisplayed + 12'd8)
|
|
case({color_depth,hres})
|
|
// shift four times as often as a load
|
|
4'b0000: shift1 <= 1'b1;
|
|
4'b0001: shift1 <= hctr[0]==1'b0;
|
|
4'b0010: shift1 <= hctr[1:0]==2'b00;
|
|
4'b0011: shift1 <= hctr[1:0]==2'b00;
|
|
// shift twice as often as a load
|
|
4'b0100: shift1 <= 1'b1;
|
|
4'b0101: shift1 <= hctr[0]==1'b0;
|
|
4'b0110: shift1 <= hctr[1:0]==2'b00;
|
|
4'b0111: shift1 <= hctr[1:0]==2'b00;
|
|
// unsupported color depth
|
|
4'b1000: shift1 <= 1'b0;
|
|
4'b1001: shift1 <= 1'b0;
|
|
4'b1010: shift1 <= 1'b0;
|
|
4'b1011: shift1 <= 1'b0;
|
|
// nothing to shift (all loads)
|
|
4'b1100: shift1 <= 1'b0;
|
|
4'b1101: shift1 <= 1'b0;
|
|
4'b1110: shift1 <= 1'b0;
|
|
4'b1111: shift1 <= 1'b0;
|
|
endcase
|
|
always @(posedge vclk) shift2 <= shift1;
|
|
always @(posedge vclk) shift <= shift2;
|
|
always @(posedge vclk) rd_fifo2 <= rd_fifo1;
|
|
always @(posedge vclk) rd_fifo <= rd_fifo2;
|
|
always @(posedge vclk)
|
|
if (rd_fifo)
|
|
rgbo2 <= rgbo1;
|
|
else if (shift)
|
|
rgbo2 <= {8'h00,rgbo2[31:8]};
|
|
always @(posedge vclk)
|
|
if (rd_fifo)
|
|
rgbo3 <= rgbo1;
|
|
else if (shift)
|
|
rgbo3 <= {16'h0000,rgbo3[31:16]};
|
|
|
RAMB16_S9_S18 ram0
|
rtfVideoFifo uf1
|
(
|
(
|
.CLKA(vclk),
|
.rst(fifo_rst),
|
.ADDRA({pixelRow[0],pixelCol[8:1],~pixelCol[0]}), // <- pixelCol[0] nonsense, we need the highest pixel first
|
.wclk(clk_i),
|
.DIA(8'hFF),
|
.wr(cyc_o & ack_i),
|
.DIPA(1'b1),
|
.di(dat_i),
|
.DOA(rgbo1),
|
.rclk(vclk),
|
.ENA(1'b1),
|
.rd(rd_fifo),
|
.WEA(1'b0),
|
.do(rgbo1),
|
.SSRA(blank),
|
.cnt(fifo_cnt)
|
|
|
.CLKB(clk_i),
|
|
.ADDRB({~pixelRow[0],fetchCol[8:1]}),
|
|
.DIB(dat_i),
|
|
.DIPB(2'b11),
|
|
.DOB(),
|
|
.ENB(cyc_o),
|
|
.WEB(ack_i),
|
|
.SSRB(1'b0)
|
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
