| Line 53... |
Line 53... |
parameter REG_PX = 10'd9;
|
parameter REG_PX = 10'd9;
|
parameter REG_PY = 10'd10;
|
parameter REG_PY = 10'd10;
|
parameter REG_COLOR = 10'd11;
|
parameter REG_COLOR = 10'd11;
|
parameter REG_PCMD = 10'd12;
|
parameter REG_PCMD = 10'd12;
|
|
|
|
parameter BPP6 = 3'd0;
|
parameter BPP8 = 3'd1;
|
parameter BPP8 = 3'd1;
|
parameter BPP12 = 3'd2;
|
parameter BPP12 = 3'd2;
|
parameter BPP16 = 3'd3;
|
parameter BPP16 = 3'd3;
|
parameter BPP24 = 3'd4;
|
parameter BPP24 = 3'd4;
|
parameter BPP32 = 3'd5;
|
parameter BPP32 = 3'd5;
|
| Line 183... |
Line 184... |
color_depth <= BPP12;
|
color_depth <= BPP12;
|
greyscale <= 1'b0;
|
greyscale <= 1'b0;
|
bm_base_addr1 <= BM_BASE_ADDR1;
|
bm_base_addr1 <= BM_BASE_ADDR1;
|
bm_base_addr2 <= BM_BASE_ADDR2;
|
bm_base_addr2 <= BM_BASE_ADDR2;
|
hrefdelay <= 12'd54;//12'd218;
|
hrefdelay <= 12'd54;//12'd218;
|
vrefdelay <= 12'd16;//12'd27;
|
vrefdelay <= 12'd18;//12'd27;
|
map <= 12'd0;
|
map <= 12'd0;
|
pcmd <= 2'b00;
|
pcmd <= 2'b00;
|
rstcmd1 <= 1'b0;
|
rstcmd1 <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
| Line 261... |
Line 262... |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Horizontal and Vertical timing reference counters
|
// Horizontal and Vertical timing reference counters
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
wire pe_hsync;
|
wire pe_hsync, pe_hsync2;
|
wire pe_vsync;
|
wire pe_vsync;
|
edge_det edh1
|
edge_det edh1
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(vclk),
|
.clk(vclk),
|
| Line 274... |
Line 275... |
.pe(pe_hsync),
|
.pe(pe_hsync),
|
.ne(),
|
.ne(),
|
.ee()
|
.ee()
|
);
|
);
|
|
|
|
edge_det edh2
|
|
(
|
|
.rst(rst_i),
|
|
.clk(m_clk_i),
|
|
.ce(1'b1),
|
|
.i(hsync),
|
|
.pe(pe_hsync2),
|
|
.ne(),
|
|
.ee()
|
|
);
|
|
|
edge_det edv1
|
edge_det edv1
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(vclk),
|
.clk(vclk),
|
.ce(1'b1),
|
.ce(1'b1),
|
| Line 323... |
Line 335... |
end
|
end
|
|
|
reg [4:0] shifts;
|
reg [4:0] shifts;
|
always @(color_depth)
|
always @(color_depth)
|
case(color_depth)
|
case(color_depth)
|
|
BPP6: shifts = 5'd21;
|
BPP8: shifts = 5'd16;
|
BPP8: shifts = 5'd16;
|
BPP12: shifts = 5'd10;
|
BPP12: shifts = 5'd10;
|
BPP16: shifts = 5'd8;
|
BPP16: shifts = 5'd8;
|
BPP24: shifts = 5'd5;
|
BPP24: shifts = 5'd5;
|
BPP32: shifts = 5'd4;
|
BPP32: shifts = 5'd4;
|
default: shifts = 5'd16;
|
default: shifts = 5'd16;
|
endcase
|
endcase
|
|
|
wire vFetch = pixelRow < vDisplayed;
|
wire vFetch = pixelRow < vDisplayed;
|
wire fifo_rrst = pixelCol==12'hFFF;
|
wire fifo_rrst = pixelCol==12'hFFF;
|
wire fifo_wrst = pe_hsync;
|
wire fifo_wrst = pe_hsync2;
|
|
|
wire[31:0] grAddr,xyAddr;
|
wire[31:0] grAddr,xyAddr;
|
reg [11:0] fetchCol;
|
reg [11:0] fetchCol;
|
wire [6:0] mb,me;
|
wire [6:0] mb,me;
|
reg [31:4] strip_addr;
|
|
reg [127:0] mem_strip;
|
reg [127:0] mem_strip;
|
wire [127:0] mem_strip_o;
|
wire [127:0] mem_strip_o;
|
wire [31:0] mem_color;
|
wire [31:0] mem_color;
|
|
|
gfx_CalcAddress u1
|
gfx_CalcAddress u1
|
(
|
(
|
|
.clk(vclk),
|
.base_address_i(baseAddr),
|
.base_address_i(baseAddr),
|
.color_depth_i(color_depth),
|
.color_depth_i({1'b0,color_depth}),
|
.hdisplayed_i(hDisplayed),
|
.hdisplayed_i(hDisplayed),
|
.x_coord_i(0),
|
.x_coord_i(0),
|
.y_coord_i(pixelRow),
|
.y_coord_i(pixelRow),
|
.address_o(grAddr),
|
.address_o(grAddr),
|
.mb_o(),
|
.mb_o(),
|
.me_o()
|
.me_o()
|
);
|
);
|
|
|
gfx_CalcAddress u2
|
gfx_CalcAddress u2
|
(
|
(
|
|
.clk(vclk),
|
.base_address_i(baseAddr),
|
.base_address_i(baseAddr),
|
.color_depth_i(color_depth),
|
.color_depth_i({1'b0,color_depth}),
|
.hdisplayed_i(hDisplayed),
|
.hdisplayed_i(hDisplayed),
|
.x_coord_i(px),
|
.x_coord_i(px),
|
.y_coord_i(py),
|
.y_coord_i(py),
|
.address_o(xyAddr),
|
.address_o(xyAddr),
|
.mb_o(mb),
|
.mb_o(mb),
|
| Line 385... |
Line 399... |
.color_i(color),
|
.color_i(color),
|
.mem_o(mem_strip_o)
|
.mem_o(mem_strip_o)
|
);
|
);
|
|
|
always @(posedge m_clk_i)
|
always @(posedge m_clk_i)
|
if (pe_hsync)
|
if (pe_hsync2)
|
mapctr <= 12'hFFE;
|
mapctr <= 12'hFFE;
|
else begin
|
else begin
|
if (mapctr == map)
|
if (mapctr == map)
|
mapctr <= 12'd0;
|
mapctr <= 12'd0;
|
else
|
else
|
| Line 406... |
Line 420... |
reg do_loads;
|
reg do_loads;
|
reg [11:0] opixelRow;
|
reg [11:0] opixelRow;
|
reg load_fifo;
|
reg load_fifo;
|
always @(posedge m_clk_i)
|
always @(posedge m_clk_i)
|
//load_fifo <= fifo_cnt < 10'd1000 && vFetch && onoff && xonoff && !m_cyc_o && do_loads;
|
//load_fifo <= fifo_cnt < 10'd1000 && vFetch && onoff && xonoff && !m_cyc_o && do_loads;
|
load_fifo <= fifo_cnt < 8'd224 && vFetch && onoff && xonoff && fetchCol < hDisplayed && !m_cyc_o && do_loads && memreq;
|
load_fifo <= /*fifo_cnt < 8'd224 &&*/ vFetch && onoff && xonoff && fetchCol < hDisplayed && !m_cyc_o && do_loads && memreq;
|
|
// The following table indicates the number of pixel that will fit into the
|
|
// video fifo.
|
reg [11:0] hCmp;
|
reg [11:0] hCmp;
|
always @(color_depth)
|
always @(color_depth)
|
case(color_depth)
|
case(color_depth)
|
BPP8: hCmp = 12'd4096;
|
BPP6: hCmp = 12'd4095;
|
|
BPP8: hCmp = 12'd4095; // must be 12 bits
|
BPP12: hCmp = 12'd2559;
|
BPP12: hCmp = 12'd2559;
|
BPP16: hCmp = 12'd2048;
|
BPP16: hCmp = 12'd2048;
|
BPP24: hCmp = 12'd1279;
|
BPP24: hCmp = 12'd1279;
|
BPP32: hCmp = 12'd1024;
|
BPP32: hCmp = 12'd1024;
|
default: hCmp = 12'd1024;
|
default: hCmp = 12'd1024;
|
| Line 422... |
Line 439... |
always @(posedge m_clk_i)
|
always @(posedge m_clk_i)
|
// if hDisplayed > hCmp we always load because the fifo isn't large enough to act as a cache.
|
// if hDisplayed > hCmp we always load because the fifo isn't large enough to act as a cache.
|
if (!(hDisplayed < hCmp))
|
if (!(hDisplayed < hCmp))
|
do_loads <= 1'b1;
|
do_loads <= 1'b1;
|
// otherwise load the fifo only when the row changes to conserve memory bandwidth
|
// otherwise load the fifo only when the row changes to conserve memory bandwidth
|
else if (pixelRow != opixelRow)
|
else if (vc==4'd1)//pixelRow != opixelRow)
|
do_loads <= 1'b1;
|
do_loads <= 1'b1;
|
else if (blankEdge)
|
else if (blankEdge)
|
do_loads <= 1'b0;
|
do_loads <= 1'b0;
|
|
|
assign m_bte_o = 2'b00;
|
assign m_bte_o = 2'b00;
|
| Line 444... |
Line 461... |
parameter WAITLOAD = 3'd6;
|
parameter WAITLOAD = 3'd6;
|
parameter WAITRST = 3'd7;
|
parameter WAITRST = 3'd7;
|
|
|
reg [31:0] adr;
|
reg [31:0] adr;
|
always @(posedge m_clk_i)
|
always @(posedge m_clk_i)
|
|
if (fifo_wrst)
|
|
adr <= grAddr;
|
|
else begin
|
|
if (state==WAITLOAD && m_ack_i)
|
|
adr <= adr + 32'd16;
|
|
end
|
|
|
|
always @(posedge m_clk_i)
|
|
if (fifo_wrst)
|
|
fetchCol <= 12'd0;
|
|
else begin
|
|
if (state==WAITLOAD && m_ack_i)
|
|
fetchCol <= fetchCol + shifts;
|
|
end
|
|
|
|
always @(posedge m_clk_i)
|
if (rst_i) begin
|
if (rst_i) begin
|
wb_nack();
|
wb_nack();
|
fetchCol <= 12'd0;
|
|
opixelRow <= 12'hFFF;
|
|
strip_addr <= 28'hFFFFFFF;
|
|
rstcmd <= 1'b0;
|
rstcmd <= 1'b0;
|
state <= IDLE;
|
state <= IDLE;
|
end
|
end
|
else begin
|
else begin
|
if (fifo_wrst) begin
|
|
fetchCol <= 12'd0;
|
|
adr <= grAddr;
|
|
opixelRow <= pixelRow;
|
|
end
|
|
case(state)
|
case(state)
|
WAITRST:
|
WAITRST:
|
if (pcmd==2'b00) begin
|
if (pcmd==2'b00) begin
|
rstcmd <= 1'b0;
|
rstcmd <= 1'b0;
|
state <= IDLE;
|
state <= IDLE;
|
| Line 473... |
Line 498... |
m_cyc_o <= 1'b1;
|
m_cyc_o <= 1'b1;
|
m_we_o <= 1'b0;
|
m_we_o <= 1'b0;
|
m_adr_o <= adr;
|
m_adr_o <= adr;
|
state <= WAITLOAD;
|
state <= WAITLOAD;
|
end
|
end
|
// The adr_o[6:5]==2'b11 causes the controller to wait until all four
|
// The adr_o[5:4]==2'b11 causes the controller to wait until all four
|
// 128 bit strips from the memory controller have been processed. Otherwise
|
// 128 bit strips from the memory controller have been processed. Otherwise
|
// there would be cache thrashing in the memory controller and the memory
|
// there would be cache thrashing in the memory controller and the memory
|
// bandwidth available would be greatly reduced. However fetches are also
|
// bandwidth available would be greatly reduced. However fetches are also
|
// aloowed when loads are not active or all strips for the current scan-
|
// allowed when loads are not active or all strips for the current scan-
|
// line have been fetched.
|
// line have been fetched.
|
else if (pcmd!=2'b00 && (m_adr_o[6:5]==2'b11 || !(vFetch && onoff && xonoff && fetchCol < hDisplayed) || !do_loads)) begin
|
else if (pcmd!=2'b00 && (m_adr_o[5:4]==2'b11 || !(vFetch && onoff && xonoff && fetchCol < hDisplayed) || !do_loads)) begin
|
if (xyAddr[31:4]!=strip_addr || 1) begin
|
|
m_cyc_o <= 1'b1;
|
m_cyc_o <= 1'b1;
|
m_we_o <= 1'b0;
|
m_we_o <= 1'b0;
|
m_adr_o <= xyAddr;
|
m_adr_o <= xyAddr;
|
state <= LOADSTRIP;
|
state <= LOADSTRIP;
|
end
|
end
|
else if (pcmd==2'b01)
|
|
state <= LOADCOLOR;
|
|
else if (pcmd==2'b10)
|
|
state <= STORESTRIP;
|
|
end
|
|
LOADCOLOR:
|
LOADCOLOR:
|
begin
|
begin
|
color_o <= mem_color;
|
color_o <= mem_color;
|
rstcmd <= 1'b1;
|
rstcmd <= 1'b1;
|
state <= WAITRST;
|
state <= WAITRST;
|
| Line 526... |
Line 545... |
wb_nack();
|
wb_nack();
|
state <= WAITRST;
|
state <= WAITRST;
|
end
|
end
|
WAITLOAD:
|
WAITLOAD:
|
if (m_ack_i) begin
|
if (m_ack_i) begin
|
fetchCol <= fetchCol + shifts;
|
|
wb_nack();
|
wb_nack();
|
adr <= adr + 32'd16;
|
|
state <= IDLE;
|
state <= IDLE;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
| Line 546... |
Line 563... |
reg [11:0] pixelColD1;
|
reg [11:0] pixelColD1;
|
reg [23:0] rgbo2,rgbo4;
|
reg [23:0] rgbo2,rgbo4;
|
reg [127:0] rgbo3;
|
reg [127:0] rgbo3;
|
always @(posedge vclk)
|
always @(posedge vclk)
|
case(color_depth)
|
case(color_depth)
|
|
BPP6: rgbo4 <= greyscale ? {3{rgbo3[5:0],2'b00}} : rgbo3[5:0];
|
BPP8: rgbo4 <= greyscale ? {3{rgbo3[7:0]}} : rgbo3[7:0];
|
BPP8: rgbo4 <= greyscale ? {3{rgbo3[7:0]}} : rgbo3[7:0];
|
BPP12: rgbo4 <= {rgbo3[11:8],4'h0,rgbo3[7:4],4'h0,rgbo3[3:0],4'h0};
|
BPP12: rgbo4 <= {rgbo3[11:8],4'h0,rgbo3[7:4],4'h0,rgbo3[3:0],4'h0};
|
BPP16: rgbo4 <= {rgbo3[15:11],3'b0,rgbo3[10:5],2'b0,rgbo3[4:0],3'b0};
|
BPP16: rgbo4 <= {rgbo3[15:11],3'b0,rgbo3[10:5],2'b0,rgbo3[4:0],3'b0};
|
BPP24: rgbo4 <= rgbo3[23:0];
|
BPP24: rgbo4 <= rgbo3[23:0];
|
BPP32: rgbo4 <= rgbo3[23:0];
|
BPP32: rgbo4 <= rgbo3[23:0];
|
| Line 605... |
Line 623... |
always @(posedge vclk)
|
always @(posedge vclk)
|
if (rd_fifo)
|
if (rd_fifo)
|
rgbo3 <= rgbo1;
|
rgbo3 <= rgbo1;
|
else if (shift) begin
|
else if (shift) begin
|
case(color_depth)
|
case(color_depth)
|
|
BPP6: rgbo3 <= {rgbo3[127:6]};
|
BPP8: rgbo3 <= {rgbo3[127:8]};
|
BPP8: rgbo3 <= {rgbo3[127:8]};
|
BPP12: rgbo3 <= {rgbo3[127:12]};
|
BPP12: rgbo3 <= {rgbo3[127:12]};
|
BPP16: rgbo3 <= {rgbo3[127:16]};
|
BPP16: rgbo3 <= {rgbo3[127:16]};
|
BPP24: rgbo3 <= {rgbo3[127:24]};
|
BPP24: rgbo3 <= {rgbo3[127:24]};
|
BPP32: rgbo3 <= {rgbo3[127:32]};
|
BPP32: rgbo3 <= {rgbo3[127:32]};
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
/* Debugging
|
|
wire [127:0] dat;
|
|
assign dat[11:0] = pixelRow[0] ? 12'hEA4 : 12'h000;
|
|
assign dat[23:12] = pixelRow[1] ? 12'hEA4 : 12'h000;
|
|
assign dat[35:24] = pixelRow[2] ? 12'hEA4 : 12'h000;
|
|
assign dat[47:36] = pixelRow[3] ? 12'hEA4 : 12'h000;
|
|
assign dat[59:48] = pixelRow[4] ? 12'hEA4 : 12'h000;
|
|
assign dat[71:60] = pixelRow[5] ? 12'hEA4 : 12'h000;
|
|
assign dat[83:72] = pixelRow[6] ? 12'hEA4 : 12'h000;
|
|
assign dat[95:84] = pixelRow[7] ? 12'hEA4 : 12'h000;
|
|
assign dat[107:96] = pixelRow[8] ? 12'hEA4 : 12'h000;
|
|
assign dat[119:108] = pixelRow[9] ? 12'hEA4 : 12'h000;
|
|
*/
|
|
|
rtfVideoFifo3 uf1
|
rtfVideoFifo3 uf1
|
(
|
(
|
.wrst(fifo_wrst),
|
.wrst(fifo_wrst),
|
.wclk(m_clk_i),
|
.wclk(m_clk_i),
|
.wr(m_cyc_o & m_ack_i),
|
.wr(m_ack_i && state==WAITLOAD),
|
.di(m_dat_i),
|
.di(m_dat_i),
|
.rrst(fifo_rrst),
|
.rrst(fifo_rrst),
|
.rclk(vclk),
|
.rclk(vclk),
|
.rd(rd_fifo),
|
.rd(rd_fifo),
|
.dout(rgbo1),
|
.dout(rgbo1),
|
| Line 642... |
Line 675... |
reg [127:0] mask;
|
reg [127:0] mask;
|
reg [127:0] o1;
|
reg [127:0] o1;
|
integer nn,n;
|
integer nn,n;
|
always @(mb_i or me_i or nn)
|
always @(mb_i or me_i or nn)
|
for (nn = 0; nn < 128; nn = nn + 1)
|
for (nn = 0; nn < 128; nn = nn + 1)
|
mask[nn] <= (nn >= mb_i) ^ (nn <= me_i) ^ (me_i >= mb_i);
|
mask[nn] <= (nn >= mb_i) & (nn <= me_i);
|
always @*
|
always @*
|
begin
|
begin
|
for (n = 0; n < 128; n = n + 1)
|
for (n = 0; n < 128; n = n + 1)
|
o1[n] = mask[n] ? mem_i[n] : 1'b0;
|
o1[n] = mask[n] ? mem_i[n] : 1'b0;
|
color_o <= o1 >> mb_i;
|
color_o <= o1 >> mb_i;
|
| Line 664... |
Line 697... |
reg [127:0] o2;
|
reg [127:0] o2;
|
reg [127:0] mask;
|
reg [127:0] mask;
|
integer nn,n;
|
integer nn,n;
|
always @(mb_i or me_i or nn)
|
always @(mb_i or me_i or nn)
|
for (nn = 0; nn < 128; nn = nn + 1)
|
for (nn = 0; nn < 128; nn = nn + 1)
|
mask[nn] <= (nn >= mb_i) ^ (nn <= me_i) ^ (me_i >= mb_i);
|
mask[nn] <= (nn >= mb_i) & (nn <= me_i);
|
|
|
always @*
|
always @*
|
begin
|
begin
|
o2 = color_i << mb_i;
|
o2 = color_i << mb_i;
|
for (n = 0; n < 128; n = n + 1) mem_o[n] = (mask[n] ? o2[n] : mem_i[n]);
|
for (n = 0; n < 128; n = n + 1) mem_o[n] = (mask[n] ? o2[n] : mem_i[n]);
|
