URL https://opencores.org/ocsvn/rtfsimpleuart/rtfsimpleuart/trunk

Subversion Repositories rtfsimpleuart

[/] [rtfsimpleuart/] [trunk/] [rtl/] [verilog/] [rtfSimpleUartRx.v] - Diff between revs 13 and 14

Rev 13	Rev 14
Line 137...	Line 137...
`// the local clock (avoids metastability).`	`// the local clock (avoids metastability).`
`reg [5:0] rxdd /* synthesis ramstyle = "logic" */; // synchronizer flops`	`reg [5:0] rxdd /* synthesis ramstyle = "logic" */; // synchronizer flops`
`reg rxdsmp; // majority samples`	`reg rxdsmp; // majority samples`
`reg rdxstart; // for majority style sample solid 3tik-wide sample`	`reg rdxstart; // for majority style sample solid 3tik-wide sample`
`reg [1:0] rxdsum;`	`reg [1:0] rxdsum;`
`always @(posedge clk_i) begin`	`always @(posedge clk_i)`
	`if (baud16x_ce) begin`
`rxdd <= {rxdd[4:0],rxd};`	`rxdd <= {rxdd[4:0],rxd};`
`if (SamplerStyle == 0) begin`	`if (SamplerStyle == 0) begin`
`rxdsmp <= rxdd[3];`	`rxdsmp <= rxdd[3];`
`rdxstart <= rxdd[4]&~rxdd[3];`	`rdxstart <= rxdd[4]&~rxdd[3];`
`end`	`end`
`else begin`	`else begin`
`rxdsum[1] <= rxdsum[0];`	`rxdsum[1] <= rxdsum[0];`
`rxdsum[0] <= {1'b0,rxdd[3]} + {1'b0,rxdd[4]} + {1'b0,rxdd[5]};`	`rxdsum[0] <= {1'b0,rxdd[3]} + {1'b0,rxdd[4]} + {1'b0,rxdd[5]};`
`rxdsmp <= rxdsum[1];`	`rxdsmp <= rxdsum[1];`
`rdxstart <= (rxdsum[1] == 2'b00) & ((rxdsum[1] == 2'b11));`	`rdxstart <= (rxdsum[0] == 2'b00) & ((rxdsum[1] == 2'b11));`
`end`	`end`
`end`	`end`


`define CNT_FRAME (8'h97)	`define CNT_FRAME (8'h97)
`define CNT_FINISH (8'h9D)	`define CNT_FINISH (8'h9D)

`always @(posedge clk_i) begin`	`always @(posedge clk_i) begin`
`if (rst_i) begin`	`if (rst_i) begin`