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// ============================================================================
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// ============================================================================
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// (C) 2006-2011 Robert Finch
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// (C) 2006-2012 Robert Finch
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// robfinch@<remove>opencores.org
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// robfinch@<remove>opencores.org
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//
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//
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// rtfTextController.v
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// rtfTextController.v
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// text controller
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// text controller
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//
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//
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rst_i, clk_i,
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rst_i, clk_i,
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cyc_i, stb_i, ack_o, we_i, sel_i, adr_i, dat_i, dat_o,
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cyc_i, stb_i, ack_o, we_i, sel_i, adr_i, dat_i, dat_o,
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lp, curpos,
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lp, curpos,
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vclk, eol, eof, blank, border, rgbIn, rgbOut
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vclk, eol, eof, blank, border, rgbIn, rgbOut
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);
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);
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parameter COLS = 12'd52;
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parameter COLS = 12'd56;
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parameter ROWS = 12'd31;
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parameter ROWS = 12'd31;
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// Syscon
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// Syscon
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input rst_i; // reset
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input rst_i; // reset
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input clk_i; // clock
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input clk_i; // clock
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input cyc_i; // cycle valid
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input cyc_i; // cycle valid
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input stb_i; // data strobe
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input stb_i; // data strobe
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output ack_o; // transfer acknowledge
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output ack_o; // transfer acknowledge
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input we_i; // write
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input we_i; // write
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input [ 1:0] sel_i; // byte select
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input [ 1:0] sel_i; // byte select
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input [31:0] adr_i; // address
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input [63:0] adr_i; // address
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input [15:0] dat_i; // data input
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input [15:0] dat_i; // data input
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output [15:0] dat_o; // data output
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output [15:0] dat_o; // data output
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reg [15:0] dat_o;
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reg [15:0] dat_o;
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//
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//
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// display and timing signals
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// display and timing signals
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reg [15:0] txtAddr; // index into memory
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reg [15:0] txtAddr; // index into memory
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reg [15:0] penAddr;
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reg [15:0] penAddr;
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wire [8:0] txtOut; // character code
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wire [8:0] txtOut; // character code
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wire [7:0] charOut; // character ROM output
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wire [8:0] charOut; // character ROM output
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wire [3:0] txtBkCode; // background color code
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wire [3:0] txtBkCode; // background color code
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wire [4:0] txtFgCode; // foreground color code
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wire [4:0] txtFgCode; // foreground color code
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reg [4:0] txtTcCode; // transparent color code
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reg [4:0] txtTcCode; // transparent color code
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reg bgt;
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reg bgt;
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wire [8:0] tdat_o;
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wire [8:0] tdat_o;
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wire [8:0] cdat_o;
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wire [8:0] cdat_o;
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wire [7:0] chdat_o;
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wire [8:0] chdat_o;
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wire [2:0] scanindex = scanline[2:0];
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wire [2:0] scanindex = scanline[2:0];
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Address Decoding
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// Address Decoding
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// I/O range FFDx
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// I/O range FFDx
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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wire cs_text = cyc_i && stb_i && (adr_i[31:16]==16'hFFD0);
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wire cs_text = cyc_i && stb_i && (adr_i[63:16]==48'hFFFF_FFFF_FFD0);
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wire cs_color= cyc_i && stb_i && (adr_i[31:16]==16'hFFD1);
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wire cs_color= cyc_i && stb_i && (adr_i[63:16]==48'hFFFF_FFFF_FFD1);
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wire cs_rom = cyc_i && stb_i && (adr_i[31:16]==16'hFFD2);
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wire cs_rom = cyc_i && stb_i && (adr_i[63:16]==48'hFFFF_FFFF_FFD2);
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wire cs_reg = cyc_i && stb_i && (adr_i[31: 8]==24'hFFDA_00);
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wire cs_reg = cyc_i && stb_i && (adr_i[63: 8]==56'hFFFF_FFFF_FFDA_00);
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wire cs_any = cs_text|cs_color|cs_rom|cs_reg;
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// Register outputs
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always @(cs_text or cs_color or cs_rom or cs_reg or tdat_o or cdat_o or chdat_o or rego)
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always @(posedge clk_i)
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if (cs_text) dat_o <= tdat_o;
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if (cs_text) dat_o <= tdat_o;
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else if (cs_color) dat_o <= cdat_o;
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else if (cs_color) dat_o <= cdat_o;
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else if (cs_rom) dat_o <= chdat_o;
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else if (cs_rom) dat_o <= chdat_o;
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else if (cs_reg) dat_o <= rego;
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else if (cs_reg) dat_o <= rego;
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else dat_o <= 16'h0000;
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else dat_o <= 16'h0000;
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.wclk(clk_i),
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.wclk(clk_i),
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.wadr(adr_i[11:0]),
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.wadr(adr_i[11:0]),
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.i(dat_i),
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.i(dat_i),
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.wo(chdat_o),
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.wo(chdat_o),
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.wce(cs_rom),
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.wce(cs_rom),
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.we(we_i),
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.we(1'b0),//we_i),
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.wrst(1'b0),
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.wrst(1'b0),
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.rclk(vclk),
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.rclk(vclk),
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.radr({txtOut,rowscan[2:0]}),
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.radr({txtOut,rowscan[2:0]}),
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.o(charOut),
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.o(charOut),
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always @(posedge vclk)
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always @(posedge vclk)
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if (nhp & ld_shft) txtFgCode1 <= txtFgCode;
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if (nhp & ld_shft) txtFgCode1 <= txtFgCode;
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// bus interfacing
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// bus interfacing
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// - there is a one cycle latency for reads, an ack is generated
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// - there is a two cycle latency for reads, an ack is generated
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// after the synchronous RAM read
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// after the synchronous RAM read
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// - writes can be acknowledged right away.
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// - writes can be acknowledged right away.
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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reg ramRdy;
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reg ramRdy,ramRdy1;
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always @(posedge clk_i)
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always @(posedge clk_i)
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ramRdy = cs_text|cs_rom|cs_color|cs_reg;
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begin
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ramRdy1 <= cs_any & !(ramRdy1|ramRdy);
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ramRdy <= ramRdy1 & cs_any;
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end
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assign ack_o = (cyc_i & stb_i) ? (we_i ? (cs_text|cs_color|cs_rom|cs_reg) : ramRdy) : 1'b0;
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assign ack_o = (cyc_i & stb_i) ? (we_i ? cs_any : ramRdy) : 1'b0;
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Registers
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// Registers
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//
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//
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windowLeft <= 12'd260;
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windowLeft <= 12'd260;
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pixelWidth <= 4'd0;
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pixelWidth <= 4'd0;
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pixelHeight <= 4'd1; // 525 pixels (408 with border)
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pixelHeight <= 4'd1; // 525 pixels (408 with border)
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*/
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*/
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// 52x31
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// 52x31
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windowTop <= 12'd14;
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windowTop <= 12'd12;
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windowLeft <= 12'd117;
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windowLeft <= 12'd128;
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pixelWidth <= 4'd1;
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pixelWidth <= 4'd2;
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pixelHeight <= 4'd3; // 262 pixels (248 with border)
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pixelHeight <= 4'd2; // 262 pixels (248 with border)
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numCols <= COLS;
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numCols <= COLS;
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numRows <= ROWS;
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numRows <= ROWS;
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maxScanline <= 5'd7;
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maxScanline <= 5'd7;
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maxScanpix <= 5'd7;
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maxScanpix <= 5'd7;
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.ld_n(1'b1),
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.ld_n(1'b1),
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.d(6'd0),
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.d(6'd0),
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.q(bcnt)
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.q(bcnt)
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);
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);
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wire blink_en = (cursorPos==txtAddr+2) && (scanline[4:0] >= cursorStart) && (scanline[4:0] <= cursorEnd);
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wire blink_en = (cursorPos+2==txtAddr) && (scanline[4:0] >= cursorStart) && (scanline[4:0] <= cursorEnd);
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VT151 ub2
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VT151 ub2
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(
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(
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.e_n(!blink_en),
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.e_n(!blink_en),
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.s(rBlink),
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.s(rBlink),
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.i4(1'b1), .i5(1'b0), .i6(bcnt[4]), .i7(bcnt[5]),
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.i4(1'b1), .i5(1'b0), .i6(bcnt[4]), .i7(bcnt[5]),
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.z(blink),
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.z(blink),
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.z_n()
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.z_n()
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);
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);
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// These tables map a five bit color code to an eight bit color value.
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// These tables map a five bit color code to an 24 bit color value.
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rtfColorROM ucm1 (.clk(vclk), .ce(nhp & ld_shft), .code(txtBkCode1), .color(bkColor24) );
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rtfColorROM ucm1 (.clk(vclk), .ce(nhp & ld_shft), .code(txtBkCode1), .color(bkColor24) );
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rtfColorROM ucm2 (.clk(vclk), .ce(nhp & ld_shft), .code(txtFgCode1), .color(fgColor24) );
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rtfColorROM ucm2 (.clk(vclk), .ce(nhp & ld_shft), .code(txtFgCode1), .color(fgColor24) );
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always @(posedge vclk)
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always @(posedge vclk)
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if (nhp & ld_shft)
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if (nhp & ld_shft)
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bgt <= {1'b0,txtBkCode1}==txtTcCode;
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bgt <= {1'b0,txtBkCode1}==txtTcCode;
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// - this means we must adapt the blanking signal by shifting the blanking window
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// - this means we must adapt the blanking signal by shifting the blanking window
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// three character times.
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// three character times.
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wire bpix = hctr[1] ^ scanline[4];// ^ blink;
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wire bpix = hctr[1] ^ scanline[4];// ^ blink;
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always @(posedge vclk)
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always @(posedge vclk)
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if (nhp)
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if (nhp)
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iblank <= (row >= numRows) || (col >= numCols + 3) || (col < 3);
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iblank <= (row >= numRows) || (col >= numCols + 2) || (col < 2);
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// Choose between input RGB and controller generated RGB
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// Choose between input RGB and controller generated RGB
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// Select between foreground and background colours.
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// Select between foreground and background colours.
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always @(posedge vclk)
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always @(posedge vclk)
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