URL
https://opencores.org/ocsvn/rv01_riscv_core/rv01_riscv_core/trunk
[/] [rv01_riscv_core/] [trunk/] [VHDL/] [RV01_cpu_2w_p6.vhd] - Diff between revs 2 and 4
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Rev 4 |
| Line 718... |
Line 718... |
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RES_o : out SDWORD_T -- result
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RES_o : out SDWORD_T -- result
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);
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);
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end component;
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end component;
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component RV01_PIPE_A_RMX_X2 is
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generic(
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NW : natural := 2
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);
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port(
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OPA_V_i : in std_logic;
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OPB_V_i : in std_logic;
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OPA_i : in SDWORD_T;
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OPB_i : in SDWORD_T;
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INSTR_i : in DEC_INSTR_T;
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IX3_V_i : in std_logic_vector(NW-1 downto 0);
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IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
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IX3_RES0_i : in SDWORD_T;
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IX3_RES1_i : in SDWORD_T;
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OPA_V_o : out std_logic;
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OPB_V_o : out std_logic;
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OPA_o : out SDWORD_T;
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OPB_o : out SDWORD_T
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);
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end component;
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component RV01_PSTLLOG_2W_P6 is
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component RV01_PSTLLOG_2W_P6 is
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generic(
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generic(
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DXE : std_logic := '1';
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DXE : std_logic := '1';
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SIMULATION_ONLY : std_logic := '0'
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SIMULATION_ONLY : std_logic := '0'
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);
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);
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