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Simply RISC S1 Core - List of T1 accesses
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Fetches from SSI OpenBoot PROM (section RED_SEC)
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=========================================
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================================================
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fff0000020: 03 00 00 00 sethi %hi(0), %g1
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fff0000024: 05 00 01 00 sethi %hi(0x40000), %g2
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fff0000028: 82 10 60 00 mov %g1, %g1
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fff000002c: 84 10 a0 c0 or %g2, 0xc0, %g2
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fff0000030: 83 28 70 20 sllx %g1, 0x20, %g1
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fff0000034: 84 10 80 01 or %g2, %g1, %g2
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fff0000038: 81 c0 80 00 jmp %g2
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fff000003c: 01 00 00 00 nop
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Fetches from RAM Bank 3 (section RED_EXT_SEC)
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=============================================
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00000400c0: b5 80 20 05 wr %g0, 5, %asr26
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00000400c4: a2 10 20 00 clr %l1
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00000400c8: 82 10 20 a9 mov 0xa9, %g1
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00000400cc: 83 28 70 20 sllx %g1, 0x20, %g1
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00000400d0: e2 70 60 00 stx %l1, [ %g1 ]
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00000400d4: e2 70 60 40 stx %l1, [ %g1 + 0x40 ]
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00000400d8: e2 70 60 80 stx %l1, [ %g1 + 0x80 ]
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00000400dc: e2 70 60 c0 stx %l1, [ %g1 + 0xc0 ]
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00000400e0: a2 10 20 00 clr %l1
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00000400e4: 82 10 20 10 mov 0x10, %g1
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00000400e8: e2 f0 48 40 stxa %l1, [ %g1 ] (66)
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00000400ec: a2 10 20 03 mov 3, %l1
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00000400f0: e2 f0 08 a0 stxa %l1, [ %g0 ] (69)
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00000400f4: a3 48 00 00 rdhpr %hpstate, %l1
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00000400f8: 81 9c 68 20 wrhpr %l1, 0x820, %hpstate
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00000400fc: 87 80 20 25 wr %g0, 0x25, %asi
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Fetches from RAM Bank 0 (section RED_EXT_SEC)
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=============================================
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0000040100: c0 f0 23 c0 stxa %g0, [ 0x3c0 ] %asi
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0000040104: c0 f0 23 c8 stxa %g0, [ 0x3c8 ] %asi
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0000040108: c0 f0 23 d0 stxa %g0, [ 0x3d0 ] %asi
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000004010c: c0 f0 23 d8 stxa %g0, [ 0x3d8 ] %asi
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*** Here the SPARC Core of the S1 sends a dirty request and hangs ***
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*** The following fetches are seen only in the original T1 sims (RAM Bank may vary) ***
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0000040110: c0 f0 23 e0 stxa %g0, [ 0x3e0 ] %asi
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0000040114: c0 f0 23 e8 stxa %g0, [ 0x3e8 ] %asi
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0000040118: c0 f0 23 f0 stxa %g0, [ 0x3f0 ] %asi
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000004011c: c0 f0 23 f8 stxa %g0, [ 0x3f8 ] %asi
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0000040120: 8f 90 20 00 wrpr 0, %tl
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0000040124: a1 90 20 00 wrpr 0, %gl
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0000040128: 8d 80 20 00 wr %g0, 0, %fprs
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000004012c: 85 80 20 00 wr %g0, 0, %ccr
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0000040130: 87 80 20 00 wr %g0, 0, %asi
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0000040134: 84 10 20 00 clr %g2
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0000040138: 89 90 80 00 wrpr %g2, %tick
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000004013c: 84 10 20 00 clr %g2
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0000040140: b1 80 80 00 mov %g2, %asr24
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0000040144: 84 10 20 01 mov 1, %g2
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0000040148: 85 28 b0 3f sllx %g2, 0x3f, %g2
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000004014c: af 80 80 00 mov %g2, %asr23
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0000040150: b3 80 80 00 mov %g2, %asr25
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0000040154: bf 98 80 00 wrhpr %g2, %hstick_cmpr
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0000040158: 81 80 00 00 mov %g0, %y
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000004015c: 91 90 20 0f wrpr 0xf, %pil
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0000040160: 93 90 20 00 wrpr 0, %cwp
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0000040164: 95 90 20 06 wrpr 6, %cansave
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0000040168: 97 90 20 00 wrpr 0, %canrestore
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000004016c: 9b 90 20 00 wrpr 0, %otherwin
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0000040170: 99 90 20 07 wrpr 7, %cleanwin
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0000040174: 9d 90 20 07 wrpr 7, %wstate
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0000040178: 82 10 20 18 mov 0x18, %g1
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000004017c: c0 f0 0a 01 stxa %g0, [ %g0 + %g1 ] (80)
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0000040180: c0 f0 0b 01 stxa %g0, [ %g0 + %g1 ] (88)
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0000040184: a2 10 20 03 mov 3, %l1
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0000040188: e2 f0 09 60 stxa %l1, [ %g0 ] (75)
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000004018c: a2 10 20 03 mov 3, %l1
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0000040190: 82 10 20 aa mov 0xaa, %g1
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0000040194: 83 28 70 20 sllx %g1, 0x20, %g1
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0000040198: e2 70 60 00 stx %l1, [ %g1 ]
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000004019c: e2 70 60 40 stx %l1, [ %g1 + 0x40 ]
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00000401a0: e2 70 60 80 stx %l1, [ %g1 + 0x80 ]
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00000401a4: e2 70 60 c0 stx %l1, [ %g1 + 0xc0 ]
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00000401a8: a3 46 80 00 rd %asr26, %l1
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00000401ac: 03 00 00 07 sethi %hi(0x1c00), %g1
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00000401b0: 82 10 63 00 or %g1, 0x300, %g1 ! 1f00
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00000401b4: a2 0c 40 01 and %l1, %g1, %l1
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00000401b8: a3 34 70 08 srlx %l1, 8, %l1
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00000401bc: 03 00 00 00 sethi %hi(0), %g1
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00000401c0: 05 00 01 30 sethi %hi(0x4c000), %g2
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00000401c4: 82 10 60 00 mov %g1, %g1
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00000401c8: 84 10 a0 00 mov %g2, %g2
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00000401cc: 83 28 70 20 sllx %g1, 0x20, %g1
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00000401d0: 84 10 80 01 or %g2, %g1, %g2
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00000401d4: a3 2c 70 03 sllx %l1, 3, %l1
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00000401d8: c4 58 80 11 ldx [ %g2 + %l1 ], %g2
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00000401dc: 82 10 20 80 mov 0x80, %g1
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00000401e0: c4 f0 4b 00 stxa %g2, [ %g1 ] (88)
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00000401e4: 2f 00 02 00 sethi %hi(0x80000), %l7
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00000401e8: 8b 9d c0 00 wrhpr %l7, %htba
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00000401ec: 21 00 00 00 sethi %hi(0), %l0
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00000401f0: 03 00 01 30 sethi %hi(0x4c000), %g1
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00000401f4: a0 14 20 00 mov %l0, %l0
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00000401f8: 82 10 61 40 or %g1, 0x140, %g1
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00000401fc: a1 2c 30 20 sllx %l0, 0x20, %l0
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0000040200: 82 10 40 10 or %g1, %l0, %g1
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0000040204: 85 28 b0 07 sllx %g2, 7, %g2
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0000040208: 82 00 40 02 add %g1, %g2, %g1
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000004020c: e2 58 40 00 ldx [ %g1 ], %l1
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0000040210: e2 f0 06 e0 stxa %l1, [ %g0 ] (55)
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0000040214: e2 58 60 08 ldx [ %g1 + 8 ], %l1
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0000040218: e2 f0 07 e0 stxa %l1, [ %g0 ] (63)
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000004021c: e2 58 60 10 ldx [ %g1 + 0x10 ], %l1
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0000040220: e2 f0 06 a0 stxa %l1, [ %g0 ] (53)
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0000040224: e2 58 60 20 ldx [ %g1 + 0x20 ], %l1
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0000040228: e2 f0 06 c0 stxa %l1, [ %g0 ] (54)
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000004022c: e2 58 60 18 ldx [ %g1 + 0x18 ], %l1
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0000040230: e2 f0 07 a0 stxa %l1, [ %g0 ] (61)
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0000040234: e2 58 60 28 ldx [ %g1 + 0x28 ], %l1
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0000040238: e2 f0 07 c0 stxa %l1, [ %g0 ] (62)
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000004023c: e2 58 60 40 ldx [ %g1 + 0x40 ], %l1
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0000040240: e2 f0 06 60 stxa %l1, [ %g0 ] (51)
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0000040244: e2 58 60 48 ldx [ %g1 + 0x48 ], %l1
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0000040248: e2 f0 07 60 stxa %l1, [ %g0 ] (59)
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000004024c: e2 58 60 50 ldx [ %g1 + 0x50 ], %l1
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0000040250: e2 f0 06 20 stxa %l1, [ %g0 ] (49)
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0000040254: e2 58 60 60 ldx [ %g1 + 0x60 ], %l1
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0000040258: e2 f0 06 40 stxa %l1, [ %g0 ] (50)
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000004025c: e2 58 60 58 ldx [ %g1 + 0x58 ], %l1
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0000040260: e2 f0 07 20 stxa %l1, [ %g0 ] (57)
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0000040264: e2 58 60 68 ldx [ %g1 + 0x68 ], %l1
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0000040268: e2 f0 07 40 stxa %l1, [ %g0 ] (58)
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000004026c: 94 10 20 80 mov 0x80, %o2
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0000040270: c0 f2 8a e0 stxa %g0, [ %o2 ] (87)
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0000040274: c0 f2 8b e0 stxa %g0, [ %o2 ] (95)
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0000040278: a2 10 20 08 mov 8, %l1
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000004027c: c0 f4 44 20 stxa %g0, [ %l1 ] (33)
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0000040280: a2 10 20 10 mov 0x10, %l1
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0000040284: c0 f4 44 20 stxa %g0, [ %l1 ] (33)
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0000040288: a2 10 20 0f mov 0xf, %l1
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000004028c: e2 f0 08 a0 stxa %l1, [ %g0 ] (69)
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0000040290: 03 00 00 00 sethi %hi(0), %g1
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0000040294: 05 00 05 10 sethi %hi(0x144000), %g2
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0000040298: 82 10 60 00 mov %g1, %g1
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000004029c: 84 10 a0 00 mov %g2, %g2
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00000402a0: 83 28 70 20 sllx %g1, 0x20, %g1
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00000402a4: 84 10 80 01 or %g2, %g1, %g2
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00000402a8: 87 48 00 00 rdhpr %hpstate, %g3
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00000402ac: 8f 90 20 01 wrpr 1, %tl
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00000402b0: 88 10 20 00 clr %g4
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00000402b4: 83 99 00 00 wrhpr %g4, %htstate
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00000402b8: 8f 90 20 00 wrpr 0, %tl
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00000402bc: 90 10 20 00 clr %o0
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00000402c0: 81 c0 80 00 jmp %g2
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00000402c4: 81 98 28 00 wrhpr 0x800, %hpstate
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00000402c8: 01 00 00 00 nop
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00000402cc: 01 00 00 00 nop
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00000402d0: 82 10 20 0f mov 0xf, %g1 ! f
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00000402d4: c2 f0 08 a0 stxa %g1, [ %g0 ] (69)
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00000402d8: c0 f0 08 60 stxa %g0, [ %g0 ] (67)
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00000402dc: 83 48 00 00 rdhpr %hpstate, %g1
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This is the list of the first accesses performed by
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the SPARC Core in the core1_mini test-suite of the
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OpenSPARC T1.
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- receive packet 1700....0010001 (INT_RET)
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- following requests go to region 4, base addr FFF0000020 (SSI ROM)
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- request packet C2018FFF0000020...00 (ROM Addr 20 -> 1 Byte?)
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- receive packet 111040300000005000100821060008410A0C0 (A-Type)
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- request packet C2008FFF0000024...00 (ROM Addr 24)
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- receive packet 111040300000005000100821060008410A0C0 (A-Type)
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- request packet C2008FFF0000028...00 (ROM Addr 28)
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- receive packet 111040300000005000100821060008410A0C0 (A-Type)
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- request packet C2010FFF000002C...00 (ROM Addr 2C)
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- receive packet 111040300000005000100821060008410A0C0 (A-Type)
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- request packet C2010FFF0000030...00 (ROM Addr 30)
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- receive packet 11104832870208410800181C0800001000000 (B-Type)
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- request packet C2008FFF0000034...00 (ROM Addr 34)
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- receive packet 11104832870208410800181C0800001000000 (B-Type)
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- request packet C2018FFF0000038...00 (ROM Addr 38)
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- receive packet 11104832870208410800181C0800001000000 (B-Type)
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- request packet C2000FFF000003C...00 (ROM Addr 3C)
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- receive packet 11104832870208410800181C0800001000000 (B-Type)
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- now we have some requests to region 3
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- request packet C200800000400C0...00 (RAM Bank 3 Addr 400C0)
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- very long pause (maybe PLL?) and then receive 2 consecutive packets
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- receive packet 11900B5802005A2102000821020A983287020 (C-Type)
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- receive packet 11102E2706000E2706040E2706080E27060C0 (D-Type)
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- request packet C201000000400C0...00 (RAM Bank 3 Addr 400C0)
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- a bit long pause and receive the same two consecutive packets
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- receive packet 11900B5802005A2102000821020A983287020 (C-Type)
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- receive packet 11102E2706000E2706040E2706080E27060C0 (D-Type)
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- now we are at 4900 ns, it is enough for now
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- after some other accesses to Bank 3 then they are everywhere in RAM
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And here are some notes about the memory map:
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@0000008000 // Section '.RED_EXT_SEC', segment 'text' - Was PA 0000040000 YES 40000-402C0 (2) RAM3012
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@0000009800 // Section '.RED_EXT_SEC', segment 'data' - Was PA 000004c000 YES 4C000-4C1A0 (5) RAM01
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@0000010000 // Section '.HTRAPS', segment 'text' - Was PA 0000080000 YES 80C80-843A0 (7) RAM2
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@0000011800 // Section '.HTRAPS', segment 'data' - Was PA 000008c000 NO (ZEROES)
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// MMU is useless?!?
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@0000200000 // TSB 'part_0_i_ctx_zero_ps0_tsb' - Was PA 0001000000
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@0000200034 // from compressed 0x0000000001000000 - Was PA 00010001a0
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@0000200038 // from compressed 0x0000000001000000 - Was PA 00010001c0
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@0000200120 // from compressed 0x0000000001000000 - Was PA 0001000900
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@000020012C // from compressed 0x0000000001000000 - Was PA 0001000960
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@0000200144 // from compressed 0x0000000001000000 - Was PA 0001000a20
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@0000200148 // from compressed 0x0000000001000000 - Was PA 0001000a40
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@0000400000 // TSB 'part_0_i_ctx_nonzero_ps0_tsb' - Was PA 0002000000
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@0000400004 // from compressed 0x0000000002000000 - Was PA 0002000020
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@0000400034 // from compressed 0x0000000002000000 - Was PA 00020001a0
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@0000400038 // from compressed 0x0000000002000000 - Was PA 00020001c0
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@0000400144 // from compressed 0x0000000002000000 - Was PA 0002000a20
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@0000400148 // from compressed 0x0000000002000000 - Was PA 0002000a40
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@0000A00000 // TSB 'part_0_d_ctx_zero_ps0_tsb' - Was PA 0005000000
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@0000A0012C // from compressed 0x0000000005000000 - Was PA 0005000960
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@0000A00138 // from compressed 0x0000000005000000 - Was PA 00050009c0
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@0000A00434 // from compressed 0x0000000005000000 - Was PA 00050021a0
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@0000A00438 // from compressed 0x0000000005000000 - Was PA 00050021c0
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@0000C00000 // TSB 'part_0_d_ctx_nonzero_ps0_tsb' - Was PA 0006000000
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@0000C00434 // from compressed 0x0000000006000000 - Was PA 00060021a0
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@0000C00438 // from compressed 0x0000000006000000 - Was PA 00060021c0
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@0008200000 // TSB_LINK 'part_0_tsb_link' - Was PA 0041000000
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@0200024000 // Section '.TRAPS', segment 'text' - Was PA 1000120000 YES 1000122400-10001225C0 (10) RAM31
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@0200025800 // Section '.TRAPS', segment 'data' - Was PA 100012c000 NO (ZEROES)
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@0200028800 // Section '.HPRIV_RESET', segment 'text' - Was PA 1000144000 YES 1000144000-1000144020 (8) RAM0
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@0220306800 // Section '.KERNEL', segment 'text' - Was PA 1101834000 YES 1101834000-1101834080 (9) RAM012
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@0220386800 // Section '.KERNEL', segment 'data' - Was PA 1101c34000 YES 1101C34020-1101C34028 (11) RAM0
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@0226000000 // Section '.MAIN', segment 'text' - Was PA 1130000000 YES 1130000000-1130000080 (12) RAM012
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@022E000000 // Section '.MAIN', segment 'data' - Was PA 1170000000 NO (EMPTY)
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@022F004000 // Section '.USER_HEAP', segment 'data' - Was PA 1178020000 NO (EMPTY)
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@022F006000 // Section '.MAIN', segment 'bss' - Was PA 1178030000 NO (EMPTY)
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// SSI ROM
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@1FFE000000 // Section '.RED_SEC', segment 'text' - Was PA fff0000000 YES FFF0000020-FFF000003C (1) I/O
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@1FFE002000 // Section '.RED_SEC', segment 'data' - Was PA fff0010000 NO (ONLY 1 WORD)
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// Accessed but missing in mem.image
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PA 0000000000-0000000400 (6)
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PA A900000000-A9000000C0 (3) RAM0123
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PA AA00000000-AA000000C0 (4) RAM0123
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