| Line 68... |
Line 68... |
wire[63:0] tmp_rd; // Temporary read data
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wire[63:0] tmp_rd; // Temporary read data
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wire[63:0] tmp_wd; // Temporary write data
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wire[63:0] tmp_wd; // Temporary write data
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integer i; // Index
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integer i; // Index
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// Initialization
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// Initialization
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`ifdef DEBUG
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`ifdef SIMPLY_RISC_DEBUG
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initial begin
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initial begin
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$display("INFO: MEMH %m: Memory Harness with Wishbone Slave interface starting...");
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$display("INFO: MEMH %m: Memory Harness with Wishbone Slave interface starting...");
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$display("INFO: MEMH %m: %0d Address Bits / %0d Doublewords / %0d Bytes Total Memory", addr_bits, addr_max+1, (addr_max+1)*8);
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$display("INFO: MEMH %m: %0d Address Bits / %0d Doublewords / %0d Bytes Total Memory", addr_bits, addr_max+1, (addr_max+1)*8);
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for(i=0; i<=addr_max; i=i+1) mem[i] = memdefaultcontent;
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for(i=0; i<=addr_max; i=i+1) mem[i] = memdefaultcontent;
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$readmemh(memfilename, mem);
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$readmemh(memfilename, mem);
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| Line 102... |
Line 102... |
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// Return the data (ignore the byte select for reads)
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// Return the data (ignore the byte select for reads)
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wbs_data_o = tmp_rd;
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wbs_data_o = tmp_rd;
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// Write a comment
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// Write a comment
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`ifdef DEBUG
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`ifdef SIMPLY_RISC_DEBUG
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if(wbs_sel_i) $display("INFO: MEMH %m: R @ %t ns, AD=%X SEL=%X DAT=%X", $time, wbs_addr_i, wbs_sel_i, wbs_data_o);
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if(wbs_sel_i) $display("INFO: MEMH %m: R @ %t ns, AD=%X SEL=%X DAT=%X", $time, wbs_addr_i, wbs_sel_i, wbs_data_o);
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`endif
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`endif
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// Write cycle
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// Write cycle
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end else if(wbs_cycle_i & wbs_strobe_i & wbs_we_i) begin
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end else if(wbs_cycle_i & wbs_strobe_i & wbs_we_i) begin
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| Line 119... |
Line 119... |
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// Store the data
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// Store the data
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mem[wbs_addr_i[addr_bits+2:3]] = tmp_wd;
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mem[wbs_addr_i[addr_bits+2:3]] = tmp_wd;
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// Write a comment
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// Write a comment
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`ifdef DEBUG
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`ifdef SIMPLY_RISC_DEBUG
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if(wbs_sel_i) $display("INFO: MEMH %m: W @ %t ns, AD=%X SEL=%X DAT=%X", $time, wbs_addr_i, wbs_sel_i, tmp_wd);
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if(wbs_sel_i) $display("INFO: MEMH %m: W @ %t ns, AD=%X SEL=%X DAT=%X", $time, wbs_addr_i, wbs_sel_i, tmp_wd);
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`endif
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`endif
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// No read/write cycle
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// No read/write cycle
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end else begin
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end else begin
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