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[/] [s1_core/] [trunk/] [hdl/] [behav/] [testbench/] [testbench.v] - Diff between revs 105 and 113

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Rev 105 Rev 113
Line 35... Line 35... 
  wire[(`WB_DATA_WIDTH-1):0] wb_datain;        // Data In
 
  wire[(`WB_DATA_WIDTH-1):0] wb_datain;        // Data In
 
 
 
 
 
  // Wishbone Master outputs / Wishbone Slave inputs
 
  // Wishbone Master outputs / Wishbone Slave inputs
 
  wire wb_cycle;                               // Cycle Start
 
  wire wb_cycle;                               // Cycle Start
 
  wire wb_strobe;                              // Strobe Request
 
  wire wb_strobe;                              // Strobe Request
 
  wire wb_we_o;                                // Write Enable
 
  wire wb_we;                                  // Write Enable
 
  wire[`WB_ADDR_WIDTH-1:0] wb_addr;            // Address Bus
 
  wire[`WB_ADDR_WIDTH-1:0] wb_addr;            // Address Bus
 
  wire[`WB_DATA_WIDTH-1:0] wb_dataout;         // Data Out
 
  wire[`WB_DATA_WIDTH-1:0] wb_dataout;         // Data Out
 
  wire[`WB_DATA_WIDTH/8-1:0] wb_sel;           // Select Output
 
  wire[`WB_DATA_WIDTH/8-1:0] wb_sel;           // Select Output
 
 
 
 
 
  // Separate Cycle, Strobe and Ack wires for ROM and RAM memory harnesses
 
  // Separate Cycle, Strobe and Ack wires for ROM and RAM memory harnesses

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