| Line 17... |
Line 17... |
* This block implements the top-level of the S1 Core.
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* This block implements the top-level of the S1 Core.
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* It is just a schematic with four instances:
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* It is just a schematic with four instances:
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* 1) one single SPARC Core of the OpenSPARC T1;
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* 1) one single SPARC Core of the OpenSPARC T1;
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* 2) a SPARC Core to Wishbone Master bridge;
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* 2) a SPARC Core to Wishbone Master bridge;
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* 3) a Reset Controller;
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* 3) a Reset Controller;
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* 4) an Interrupt Controller.
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* 4) an Interrupt Controller;
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*
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* 5) a Floating-Point Unit from the OpenSPARC SoC.
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*/
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*/
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`include "s1_defs.h"
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`include "s1_defs.h"
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module s1_top (
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module s1_top (
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sys_clock_i, sys_reset_i, sys_irq_i,
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wbm_ack_i, wbm_data_i,
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wbm_cycle_o, wbm_strobe_o, wbm_we_o, wbm_addr_o, wbm_data_o, wbm_sel_o
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);
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/*
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/*
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* Inputs
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* Inputs
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*/
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*/
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// System inputs
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// System inputs
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input sys_clock_i; // System Clock
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input sys_clock_i, // System Clock
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input sys_reset_i; // System Reset
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input sys_reset_i, // System Reset
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input[63:0] sys_irq_i; // Interrupt Requests
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input[63:0] sys_irq_i, // Interrupt Requests
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// Wishbone Interconnect Master Interface inputs
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// Wishbone Interconnect Master Interface inputs
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input wbm_ack_i; // Ack
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input wbm_ack_i, // Ack
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input[(`WB_DATA_WIDTH-1):0] wbm_data_i; // Data In
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input[(`WB_DATA_WIDTH-1):0] wbm_data_i, // Data In
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/*
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/*
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* Outputs
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* Outputs
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*/
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*/
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// Wishbone Interconnect Master Interface outputs
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// Wishbone Interconnect Master Interface outputs
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output wbm_cycle_o; // Cycle Start
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output wbm_cycle_o, // Cycle Start
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output wbm_strobe_o; // Strobe Request
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output wbm_strobe_o, // Strobe Request
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output wbm_we_o; // Write Enable
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output wbm_we_o, // Write Enable
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output[`WB_ADDR_WIDTH-1:0] wbm_addr_o; // Address Bus
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output[`WB_ADDR_WIDTH-1:0] wbm_addr_o, // Address Bus
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output[`WB_DATA_WIDTH-1:0] wbm_data_o; // Data Out
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output[`WB_DATA_WIDTH-1:0] wbm_data_o, // Data Out
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output[`WB_DATA_WIDTH/8-1:0] wbm_sel_o; // Select Output
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output[`WB_DATA_WIDTH/8-1:0] wbm_sel_o // Select Output
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);
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/*
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/*
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* Wires
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* Wires
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*/
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*/
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| Line 84... |
Line 80... |
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// cpx interface
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// cpx interface
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wire [4:0] pcx_spc_grant_px; // pcx to processor grant info
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wire [4:0] pcx_spc_grant_px; // pcx to processor grant info
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wire cpx_spc_data_rdy_cx2; // cpx data inflight to sparc
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wire cpx_spc_data_rdy_cx2; // cpx data inflight to sparc
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wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2; // cpx to sparc data packet
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wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2; // cpx to sparc data packet
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wire wbm_spc_stall; // Stall requests
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wire wbm_spc_resume; // Resume requests
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wire [3:0] const_cpuid;
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wire [3:0] const_cpuid;
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wire [7:0] const_maskid; // To ifu of sparc_ifu.v
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wire [7:0] const_maskid; // To ifu of sparc_ifu.v
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// sscan
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// sscan
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| Line 136... |
Line 130... |
wire sys_reset_final;
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wire sys_reset_final;
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// Interrupt Source from the interrupt controller to the bridge
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// Interrupt Source from the interrupt controller to the bridge
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wire[5:0] sys_interrupt_source;
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wire[5:0] sys_interrupt_source;
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// FIFO
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reg [4:0] pcx_spc_grant_px_fifo;
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`ifdef DMITRY
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// Floating-Point Unit
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wire fp_req;
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wire [123:0] fp_pcx;
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wire [ 7:0] fp_rdy;
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wire [144:0] fp_cpx;
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`endif
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/*
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/*
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* SPARC Core module instance
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* SPARC Core module instance
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*/
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*/
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sparc sparc_0 (
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sparc sparc_0 (
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| Line 158... |
Line 163... |
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// Wires connected to SPARC Core inputs
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// Wires connected to SPARC Core inputs
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.pcx_spc_grant_px(pcx_spc_grant_px),
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.pcx_spc_grant_px(pcx_spc_grant_px),
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.cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),
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.cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),
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.cpx_spc_data_cx2(cpx_spc_data_cx2),
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.cpx_spc_data_cx2(cpx_spc_data_cx2),
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.wbm_spc_stall(wbm_spc_stall),
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.wbm_spc_resume(wbm_spc_resume),
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.const_cpuid(const_cpuid),
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.const_cpuid(const_cpuid),
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.const_maskid(const_maskid),
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.const_maskid(const_maskid),
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.ctu_tck(ctu_tck),
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.ctu_tck(ctu_tck),
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.ctu_sscan_se(ctu_sscan_se),
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.ctu_sscan_se(ctu_sscan_se),
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.ctu_sscan_snap(ctu_sscan_snap),
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.ctu_sscan_snap(ctu_sscan_snap),
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| Line 195... |
Line 198... |
);
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);
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/*
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/*
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* SPARC Core to Wishbone Master bridge
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* SPARC Core to Wishbone Master bridge
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*/
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*/
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`ifdef DMITRY
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os2wb os2wb_0 (
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// Top-level system inputs
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.clk(sys_clock_i),
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.rstn(~sys_reset_final),
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spc2wbm spc2wbm_0 (
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// Bridge inputs connected to SPARC Core outputs
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.pcx_req(spc_pcx_req_pq),
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.pcx_atom(spc_pcx_atom_pq),
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.pcx_data(spc_pcx_data_pa),
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// Top-level system inputs
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// Bridge outputs connected to SPARC Core inputs
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.pcx_grant(pcx_spc_grant_px),
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.cpx_ready(cpx_spc_data_rdy_cx2),
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.cpx_packet(cpx_spc_data_cx2),
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// Top-level Wishbone Interconnect inputs
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.wb_data_i(wbm_data_i),
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.wb_ack(wbm_ack_i),
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// Top-level Wishbone Interconnect outputs
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.wb_cycle(wbm_cycle_o),
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.wb_strobe(wbm_strobe_o),
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.wb_we(wbm_we_o),
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.wb_sel(wbm_sel_o),
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.wb_addr(wbm_addr_o),
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.wb_data_o(wbm_data_o),
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.fp_pcx(fp_pcx),
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.fp_req(fp_req),
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.fp_cpx(fp_cpx),
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.fp_rdy(fp_rdy!=8'h00),
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.eth_int(sys_interrupt_source[0])
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);
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`else
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spc2wbm spc2wbm_0 (
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// System inputs
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.sys_clock_i(sys_clock_i),
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.sys_clock_i(sys_clock_i),
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.sys_reset_i(sys_reset_final),
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.sys_reset_i(sys_reset_final),
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.sys_interrupt_source_i(sys_interrupt_source),
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.sys_interrupt_source_i(sys_interrupt_source),
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// Bridge inputs connected to SPARC Core outputs
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// Bridge inputs connected to SPARC Core outputs
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| Line 212... |
Line 249... |
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// Bridge outputs connected to SPARC Core inputs
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// Bridge outputs connected to SPARC Core inputs
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.spc_grant_o(pcx_spc_grant_px),
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.spc_grant_o(pcx_spc_grant_px),
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.spc_ready_o(cpx_spc_data_rdy_cx2),
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.spc_ready_o(cpx_spc_data_rdy_cx2),
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.spc_packetin_o(cpx_spc_data_cx2),
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.spc_packetin_o(cpx_spc_data_cx2),
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.spc_stall_o(wbm_spc_stall),
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.spc_resume_o(wbm_spc_resume),
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// Top-level Wishbone Interconnect inputs
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// Top-level Wishbone Interconnect inputs
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.wbm_ack_i(wbm_ack_i),
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.wbm_ack_i(wbm_ack_i),
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.wbm_data_i(wbm_data_i),
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.wbm_data_i(wbm_data_i),
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| Line 226... |
Line 261... |
.wbm_strobe_o(wbm_strobe_o),
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.wbm_strobe_o(wbm_strobe_o),
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.wbm_we_o(wbm_we_o),
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.wbm_we_o(wbm_we_o),
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.wbm_addr_o(wbm_addr_o),
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.wbm_addr_o(wbm_addr_o),
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.wbm_data_o(wbm_data_o),
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.wbm_data_o(wbm_data_o),
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.wbm_sel_o(wbm_sel_o)
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.wbm_sel_o(wbm_sel_o)
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);
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);
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`endif
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/*
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* Floating-Point Unit
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*/
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`ifdef DMITRY
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fpu fpu_0 (
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.pcx_fpio_data_rdy_px2(fp_req),
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.pcx_fpio_data_px2(fp_pcx),
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.arst_l(cmp_arst_l),
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.grst_l(cmp_grst_l),
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.gclk(gclk),
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.cluster_cken(cluster_cken),
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.fp_cpx_req_cq(fp_rdy),
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.fp_cpx_data_ca(fp_cpx),
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.ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
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.global_shift_enable(global_shift_enable),
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.ctu_tst_scan_disable(ctu_tst_scan_disable),
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.ctu_tst_scanmode(ctu_tst_scanmode),
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.ctu_tst_macrotest(ctu_tst_macrotest),
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.ctu_tst_short_chain(ctu_tst_short_chain),
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.si(1'b0),
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.so()
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);
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`endif
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/*
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/*
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* Reset Controller
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* Reset Controller
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*/
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*/
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rst_ctrl rst_ctrl_0 (
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rst_ctrl rst_ctrl_0 (
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| Line 302... |
Line 362... |
assign global_shift_enable = 1'b0;
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assign global_shift_enable = 1'b0;
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assign ctu_tst_scanmode = 1'b0;
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assign ctu_tst_scanmode = 1'b0;
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assign spc_scanin0 = 1'b0;
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assign spc_scanin0 = 1'b0;
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assign spc_scanin1 = 1'b0;
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assign spc_scanin1 = 1'b0;
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/*
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The following signals are handled by the Reset Controller:
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// clk
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assign cluster_cken = ...;
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assign gclk = ...;
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// reset
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assign cmp_grst_l = ...;
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assign cmp_arst_l = ...;
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assign ctu_tst_pre_grst_l = ...;
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assign adbginit_l = ...;
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assign gdbginit_l = ...;
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*/
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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