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Line 84... |
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// cpx interface
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// cpx interface
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wire [4:0] pcx_spc_grant_px; // pcx to processor grant info
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wire [4:0] pcx_spc_grant_px; // pcx to processor grant info
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wire cpx_spc_data_rdy_cx2; // cpx data inflight to sparc
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wire cpx_spc_data_rdy_cx2; // cpx data inflight to sparc
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wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2; // cpx to sparc data packet
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wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2; // cpx to sparc data packet
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wire wbm_spc_stallreq; // Stall request
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wire wbm_spc_stall; // Stall requests
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wire wbm_spc_resume; // Resume requests
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wire [3:0] const_cpuid;
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wire [3:0] const_cpuid;
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wire [7:0] const_maskid; // To ifu of sparc_ifu.v
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wire [7:0] const_maskid; // To ifu of sparc_ifu.v
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// sscan
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// sscan
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Line 157... |
Line 158... |
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// Wires connected to SPARC Core inputs
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// Wires connected to SPARC Core inputs
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.pcx_spc_grant_px(pcx_spc_grant_px),
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.pcx_spc_grant_px(pcx_spc_grant_px),
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.cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),
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.cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),
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.cpx_spc_data_cx2(cpx_spc_data_cx2),
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.cpx_spc_data_cx2(cpx_spc_data_cx2),
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.wbm_spc_stallreq(wbm_spc_stallreq),
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.wbm_spc_stall(wbm_spc_stall),
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.wbm_spc_resume(wbm_spc_resume),
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.const_cpuid(const_cpuid),
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.const_cpuid(const_cpuid),
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.const_maskid(const_maskid),
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.const_maskid(const_maskid),
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.ctu_tck(ctu_tck),
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.ctu_tck(ctu_tck),
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.ctu_sscan_se(ctu_sscan_se),
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.ctu_sscan_se(ctu_sscan_se),
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.ctu_sscan_snap(ctu_sscan_snap),
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.ctu_sscan_snap(ctu_sscan_snap),
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Line 212... |
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// Bridge outputs connected to SPARC Core inputs
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// Bridge outputs connected to SPARC Core inputs
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.spc_grant_o(pcx_spc_grant_px),
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.spc_grant_o(pcx_spc_grant_px),
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.spc_ready_o(cpx_spc_data_rdy_cx2),
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.spc_ready_o(cpx_spc_data_rdy_cx2),
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.spc_packetin_o(cpx_spc_data_cx2),
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.spc_packetin_o(cpx_spc_data_cx2),
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.spc_stallreq_o(wbm_spc_stallreq),
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.spc_stall_o(wbm_spc_stall),
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.spc_resume_o(wbm_spc_resume),
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// Top-level Wishbone Interconnect inputs
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// Top-level Wishbone Interconnect inputs
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.wbm_ack_i(wbm_ack_i),
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.wbm_ack_i(wbm_ack_i),
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.wbm_data_i(wbm_data_i),
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.wbm_data_i(wbm_data_i),
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