| Line 38... |
Line 38... |
*/
|
*/
|
|
|
// System inputs
|
// System inputs
|
input sys_clock_i; // System Clock
|
input sys_clock_i; // System Clock
|
input sys_reset_i; // System Reset
|
input sys_reset_i; // System Reset
|
input[5:0] sys_interrupt_source_i; // Interrupt Requests
|
input[5:0] sys_interrupt_source_i; // Encoded Interrupt Source
|
|
|
// SPARC-side inputs connected to the PCX (Processor-to-Cache Xbar) outputs of the SPARC Core
|
// SPARC-side inputs connected to the PCX (Processor-to-Cache Xbar) outputs of the SPARC Core
|
input[4:0] spc_req_i; // Request
|
input[4:0] spc_req_i; // Request
|
input spc_atom_i; // Atomic Request
|
input spc_atom_i; // Atomic Request
|
input[(`PCX_WIDTH-1):0] spc_packetout_i; // Outgoing Packet
|
input[(`PCX_WIDTH-1):0] spc_packetout_i; // Outgoing Packet
|
| Line 91... |
Line 91... |
|
|
// Wishbone Master to SPARC Core info used to encode the return packet
|
// Wishbone Master to SPARC Core info used to encode the return packet
|
reg wbm2spc_valid; // Valid
|
reg wbm2spc_valid; // Valid
|
reg[(`CPX_RQ_HI-`CPX_RQ_LO):0] wbm2spc_type; // Request type
|
reg[(`CPX_RQ_HI-`CPX_RQ_LO):0] wbm2spc_type; // Request type
|
reg[(`CPX_ERR_HI-`CPX_ERR_LO):0] wbm2spc_error; // Error
|
reg[(`CPX_ERR_HI-`CPX_ERR_LO):0] wbm2spc_error; // Error
|
reg wbm2spc_rnwd_or_ncif; // Read-Not-Write Data or Non-Cacheable Instruction Fetch
|
reg wbm2spc_nc; // Non-Cacheable
|
reg[(`CPX_TH_HI-`CPX_TH_LO):0] wbm2spc_thread; // Thread
|
reg[(`CPX_TH_HI-`CPX_TH_LO):0] wbm2spc_thread; // Thread
|
reg[(`CPX_P_HI-`CPX_P_LO):0] wbm2spc_packet_id; // Packet ID
|
reg wbm2spc_way_valid; // L2 Way Valid
|
|
reg[(`CPX_WY_HI-`CPX_WY_LO):0] wbm2spc_way; // Replaced L2 Way
|
reg[(`CPX_DA_HI-`CPX_DA_LO):0] wbm2spc_data; // Load Data
|
reg[(`CPX_DA_HI-`CPX_DA_LO):0] wbm2spc_data; // Load Data
|
reg[(`CPX_IN_HI-`CPX_IN_LO):0] wbm2spc_interrupt_source; // Interrupt Source
|
reg[6:0] wbm2spc_interrupt_source; // Encoded Interrupt Source
|
reg wbm2spc_reset_not_int; // Reset and not interrupt packet
|
reg wbm2spc_interrupt_new; // New Interrupt Pending
|
reg[4:0] wbm2spc_virtual_cpu_target; // ID of virtual CPU target
|
|
reg[(`CPX_IN_HI-`CPX_IN_LO):0] wbm2spc_intsrc_or_resettype; // Interrupt Source or Reset Type
|
|
reg[(`CPX_IN_HI-`CPX_IN_LO):0] wbm2spc_new_irq; // New Interrupt Request Pending
|
|
|
|
/*
|
/*
|
* Wires
|
* Wires
|
*/
|
*/
|
|
|
// Decoded SPARC Core to Wishbone Master info
|
// Decoded SPARC Core to Wishbone Master info
|
wire spc2wbm_req; // Request
|
wire spc2wbm_req; // Request
|
wire spc2wbm_valid; // Valid
|
wire spc2wbm_valid; // Valid
|
wire[(`PCX_RQ_HI-`PCX_RQ_LO):0] spc2wbm_type; // Request type
|
wire[(`PCX_RQ_HI-`PCX_RQ_LO):0] spc2wbm_type; // Request type
|
wire spc2wbm_rnwd_or_ncif; // Read-Not-Write Data or Non-Cacheable Instruction Fetch
|
wire spc2wbm_nc; // Non-Cacheable
|
wire[(`PCX_CP_HI-`PCX_CP_LO):0] spc2wbm_cpu_id; // CPU ID
|
wire[(`PCX_CP_HI-`PCX_CP_LO):0] spc2wbm_cpu_id; // CPU ID
|
wire[(`PCX_TH_HI-`PCX_TH_LO):0] spc2wbm_thread; // Thread
|
wire[(`PCX_TH_HI-`PCX_TH_LO):0] spc2wbm_thread; // Thread
|
wire[(`PCX_BF_HI-`PCX_BF_LO):0] spc2wbm_buffer; // Buffer
|
wire spc2wbm_invalidate; // Invalidate all
|
wire[(`PCX_P_HI-`PCX_P_LO):0] spc2wbm_packet_id; // Packet ID
|
wire[(`PCX_WY_HI-`PCX_WY_LO):0] spc2wbm_way; // Replaced L1 Way
|
wire[(`PCX_SZ_HI-`PCX_SZ_LO):0] spc2wbm_size; // Load/Store size
|
wire[(`PCX_SZ_HI-`PCX_SZ_LO):0] spc2wbm_size; // Load/Store size
|
wire[(`PCX_ERR_HI-`PCX_ERR_LO):0] spc2wbm_error; // Error
|
|
wire[(`PCX_AD_HI-`PCX_AD_LO):0] spc2wbm_addr; // Address
|
wire[(`PCX_AD_HI-`PCX_AD_LO):0] spc2wbm_addr; // Address
|
wire[(`PCX_DA_HI-`PCX_DA_LO):0] spc2wbm_data; // Store Data
|
wire[(`PCX_DA_HI-`PCX_DA_LO):0] spc2wbm_data; // Store Data
|
|
|
// Return packets assembled with various fields
|
// Return packets assembled with various fields
|
wire[`CPX_WIDTH-1:0] wbm2spc_packet_dat; // Incoming Packet - Data
|
wire[`CPX_WIDTH-1:0] wbm2spc_packet; // Incoming Packet
|
wire[`CPX_WIDTH-1:0] wbm2spc_packet_int; // Incoming Packet - Interrupt
|
|
|
|
/*
|
/*
|
* Encode/decode incoming info
|
* Encode/decode incoming info
|
*
|
*
|
* Legenda: available constants for some of the PCX/CPX fields.
|
* Legenda: available constants for some of the PCX/CPX fields.
|
| Line 149... |
Line 146... |
|
|
// Decode info arriving from the SPC side
|
// Decode info arriving from the SPC side
|
assign spc2wbm_req = ( spc_req_i[4] | spc_req_i[3] | spc_req_i[2] | spc_req_i[1] | spc_req_i[0] );
|
assign spc2wbm_req = ( spc_req_i[4] | spc_req_i[3] | spc_req_i[2] | spc_req_i[1] | spc_req_i[0] );
|
assign spc2wbm_valid = spc2wbm_packet[`PCX_VLD];
|
assign spc2wbm_valid = spc2wbm_packet[`PCX_VLD];
|
assign spc2wbm_type = spc2wbm_packet[`PCX_RQ_HI:`PCX_RQ_LO];
|
assign spc2wbm_type = spc2wbm_packet[`PCX_RQ_HI:`PCX_RQ_LO];
|
assign spc2wbm_rnwd_or_ncif = spc2wbm_packet[`PCX_R];
|
assign spc2wbm_nc = spc2wbm_packet[`PCX_NC];
|
assign spc2wbm_cpu_id = spc2wbm_packet[`PCX_CP_HI:`PCX_CP_LO];
|
assign spc2wbm_cpu_id = spc2wbm_packet[`PCX_CP_HI:`PCX_CP_LO];
|
assign spc2wbm_thread = spc2wbm_packet[`PCX_TH_HI:`PCX_TH_LO];
|
assign spc2wbm_thread = spc2wbm_packet[`PCX_TH_HI:`PCX_TH_LO];
|
assign spc2wbm_buffer = spc2wbm_packet[`PCX_BF_HI:`PCX_BF_LO];
|
assign spc2wbm_invalidate = spc2wbm_packet[`PCX_INVALL];
|
assign spc2wbm_packet_id = spc2wbm_packet[`PCX_P_HI:`PCX_P_LO];
|
assign spc2wbm_way = spc2wbm_packet[`PCX_WY_HI:`PCX_WY_LO];
|
assign spc2wbm_size = spc2wbm_packet[`PCX_SZ_HI:`PCX_SZ_LO];
|
assign spc2wbm_size = spc2wbm_packet[`PCX_SZ_HI:`PCX_SZ_LO];
|
assign spc2wbm_error = spc2wbm_packet[`PCX_ERR_HI:`PCX_ERR_LO];
|
|
assign spc2wbm_addr = spc2wbm_packet[`PCX_AD_HI:`PCX_AD_LO];
|
assign spc2wbm_addr = spc2wbm_packet[`PCX_AD_HI:`PCX_AD_LO];
|
assign spc2wbm_data = spc2wbm_packet[`PCX_DA_HI:`PCX_DA_LO];
|
assign spc2wbm_data = spc2wbm_packet[`PCX_DA_HI:`PCX_DA_LO];
|
|
|
// Encode info going to the SPC side assembling return packets
|
// Encode info going to the SPC side assembling return packets
|
assign wbm2spc_packet_dat = { wbm2spc_valid, wbm2spc_type, wbm2spc_error,
|
assign wbm2spc_packet = { wbm2spc_valid, wbm2spc_type, wbm2spc_error, wbm2spc_nc,
|
wbm2spc_rnwd_or_ncif, wbm2spc_thread, 2'b00, wbm2spc_packet_id,
|
wbm2spc_thread, wbm2spc_way_valid, wbm2spc_way, 3'b100, wbm2spc_data };
|
2'b00, wbm2spc_data };
|
|
assign wbm2spc_packet_int = { wbm2spc_valid, wbm2spc_type, wbm2spc_error,
|
|
wbm2spc_rnwd_or_ncif, wbm2spc_thread, wbm2spc_interrupt_source,
|
|
111'b0, wbm2spc_reset_not_int, 3'b0, wbm2spc_virtual_cpu_target,
|
|
2'b0, wbm2spc_intsrc_or_resettype };
|
|
|
|
/*
|
/*
|
* State Machine
|
* State Machine
|
*/
|
*/
|
|
|
| Line 196... |
Line 187... |
// Prepare wakeup packet for SPARC Core, the resulting output is
|
// Prepare wakeup packet for SPARC Core, the resulting output is
|
// spc_packetin_o = `CPX_WIDTH'h1700000000000000000000000000000010001;
|
// spc_packetin_o = `CPX_WIDTH'h1700000000000000000000000000000010001;
|
wbm2spc_valid = 1;
|
wbm2spc_valid = 1;
|
wbm2spc_type = `INT_RET;
|
wbm2spc_type = `INT_RET;
|
wbm2spc_error = 0;
|
wbm2spc_error = 0;
|
wbm2spc_rnwd_or_ncif = 0;
|
wbm2spc_nc = 0;
|
wbm2spc_thread = 0;
|
wbm2spc_thread = 0;
|
wbm2spc_packet_id = 0;
|
wbm2spc_way_valid = 0;
|
wbm2spc_interrupt_source = 0;
|
wbm2spc_way = 0;
|
wbm2spc_reset_not_int = 1;
|
wbm2spc_data = 64'h10001;
|
wbm2spc_virtual_cpu_target = 0;
|
|
wbm2spc_intsrc_or_resettype = 6'b000001;
|
|
wbm2spc_new_irq = 0; // Ignored for wakeup packet
|
|
|
|
// Clear state machine
|
// Clear state machine
|
state = `STATE_WAKEUP;
|
state = `STATE_WAKEUP;
|
|
|
end else begin
|
end else begin
|
| Line 216... |
Line 204... |
// Send to the SPARC Core the wakeup packet
|
// Send to the SPARC Core the wakeup packet
|
if(state==`STATE_WAKEUP) begin
|
if(state==`STATE_WAKEUP) begin
|
|
|
// Send wakeup packet
|
// Send wakeup packet
|
spc_ready_o = 1;
|
spc_ready_o = 1;
|
spc_packetin_o = wbm2spc_packet_int;
|
spc_packetin_o = wbm2spc_packet;
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
// Display comment
|
// Display comment
|
$display("INFO: SPC2WBM: SPARC Core to Wishbone Master bridge starting...");
|
$display("INFO: SPC2WBM: SPARC Core to Wishbone Master bridge starting...");
|
$display("INFO: SPC2WBM: Wakeup packet sent to SPARC Core");
|
$display("INFO: SPC2WBM: Wakeup packet sent to SPARC Core");
|
| Line 253... |
Line 241... |
|
|
// See if the interrupt vector has changed
|
// See if the interrupt vector has changed
|
end else if(sys_interrupt_source_i!=wbm2spc_interrupt_source) begin
|
end else if(sys_interrupt_source_i!=wbm2spc_interrupt_source) begin
|
|
|
// Set the flag for next cycle
|
// Set the flag for next cycle
|
wbm2spc_new_irq = 1;
|
wbm2spc_interrupt_new = 1;
|
|
|
// Prepare the interrupt packet for the SPARC Core
|
// Prepare the interrupt packet for the SPARC Core
|
wbm2spc_valid = 1;
|
wbm2spc_valid = 1;
|
wbm2spc_type = `INT_RET;
|
wbm2spc_type = `INT_RET;
|
wbm2spc_error = 0;
|
wbm2spc_error = 0;
|
wbm2spc_rnwd_or_ncif = 0;
|
wbm2spc_nc = 0;
|
wbm2spc_thread = 0;
|
wbm2spc_thread = 0;
|
wbm2spc_packet_id = 0;
|
wbm2spc_way_valid = 0;
|
wbm2spc_interrupt_source = sys_interrupt_source_i;
|
wbm2spc_way = 0;
|
wbm2spc_reset_not_int = 0;
|
|
wbm2spc_virtual_cpu_target = 0;
|
|
wbm2spc_intsrc_or_resettype = sys_interrupt_source_i;
|
|
|
|
// Stall other requests from the SPARC Core
|
// Stall other requests from the SPARC Core
|
spc_stallreq_o = 1;
|
spc_stallreq_o = 1;
|
|
|
// Next cycle see if there's an int to be forwarded to the Core
|
// Next cycle see if there's an int to be forwarded to the Core
|
end else if(wbm2spc_interrupt_source!=6'b000000 && wbm2spc_new_irq) begin
|
end else if(wbm2spc_interrupt_source!=6'b000000 && wbm2spc_interrupt_new) begin
|
|
|
// Clean the flag
|
// Clean the flag
|
wbm2spc_new_irq = 0;
|
wbm2spc_interrupt_new = 0;
|
|
|
// Send the interrupt packet to the Core
|
// Send the interrupt packet to the Core
|
spc_ready_o = 1;
|
spc_ready_o = 1;
|
spc_packetin_o = wbm2spc_packet_int;
|
spc_packetin_o = wbm2spc_packet;
|
|
|
// Stall other requests from the SPARC Core
|
// Stall other requests from the SPARC Core
|
spc_stallreq_o = 1;
|
spc_stallreq_o = 1;
|
|
|
// Stay in this state
|
// Stay in this state
|
| Line 354... |
Line 339... |
wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2));
|
wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2));
|
else
|
else
|
// For accesses to RAM 256 bits are expected (2 ret packets)
|
// For accesses to RAM 256 bits are expected (2 ret packets)
|
wbm_sel_o = 8'b11111111;
|
wbm_sel_o = 8'b11111111;
|
|
|
end else begin
|
end else if(spc2wbm_type==`LOAD_RQ) begin
|
|
|
// For data load/store use the provided data
|
// For data load use the provided data
|
wbm_we_o = !spc2wbm_rnwd_or_ncif;
|
wbm_we_o = 0;
|
case(spc2wbm_size)
|
case(spc2wbm_size)
|
`PCX_SZ_1B: wbm_sel_o = (1'b1<<spc2wbm_addr[2:0]);
|
`PCX_SZ_1B: wbm_sel_o = (1'b1<<spc2wbm_addr[2:0]);
|
`PCX_SZ_2B: wbm_sel_o = (2'b11<<(spc2wbm_addr[2:1]<<1));
|
`PCX_SZ_2B: wbm_sel_o = (2'b11<<(spc2wbm_addr[2:1]<<1));
|
`PCX_SZ_4B: wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2));
|
`PCX_SZ_4B: wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2));
|
`PCX_SZ_8B: wbm_sel_o = 8'b11111111;
|
`PCX_SZ_8B: wbm_sel_o = 8'b11111111;
|
`PCX_SZ_16B: wbm_sel_o = 8'b11111111; // Requires a 2nd access
|
`PCX_SZ_16B: wbm_sel_o = 8'b11111111; // Requires a 2nd access
|
default: wbm_sel_o = 8'b00000000;
|
default: wbm_sel_o = 8'b00000000;
|
endcase
|
endcase
|
|
|
|
end else if(spc2wbm_type==`STORE_RQ) begin
|
|
|
|
// For data store use the provided data
|
|
wbm_we_o = 1;
|
|
case(spc2wbm_size)
|
|
`PCX_SZ_1B: wbm_sel_o = (1'b1<<spc2wbm_addr[2:0]);
|
|
`PCX_SZ_2B: wbm_sel_o = (2'b11<<(spc2wbm_addr[2:1]<<1));
|
|
`PCX_SZ_4B: wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2));
|
|
`PCX_SZ_8B: wbm_sel_o = 8'b11111111;
|
|
`PCX_SZ_16B: wbm_sel_o = 8'b11111111; // Requires a 2nd access
|
|
default: wbm_sel_o = 8'b00000000;
|
|
endcase
|
|
|
|
end else begin
|
|
|
|
wbm_we_o = 1;
|
|
wbm_sel_o = 8'b00000000;
|
|
|
end
|
end
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
// Print details of request packet
|
// Print details of request packet
|
if(spc2wbm_valid==1) $display("INFO: SPC2WBM: Request has valid bit");
|
$display("INFO: SPC2WBM: Valid bit is %X", spc2wbm_valid);
|
else $display("INFO: SPC2WBM: Request has not valid bit");
|
|
case(spc2wbm_type)
|
case(spc2wbm_type)
|
`LOAD_RQ: $display("INFO: SPC2WBM: Request of Type LOAD_RQ");
|
`LOAD_RQ: $display("INFO: SPC2WBM: Request of Type LOAD_RQ");
|
`IMISS_RQ: $display("INFO: SPC2WBM: Request of Type IMISS_RQ");
|
`IMISS_RQ: $display("INFO: SPC2WBM: Request of Type IMISS_RQ");
|
`STORE_RQ: $display("INFO: SPC2WBM: Request of Type STORE_RQ");
|
`STORE_RQ: $display("INFO: SPC2WBM: Request of Type STORE_RQ");
|
`CAS1_RQ: $display("INFO: SPC2WBM: Request of Type CAS1_RQ");
|
`CAS1_RQ: $display("INFO: SPC2WBM: Request of Type CAS1_RQ");
|
| Line 389... |
Line 391... |
`FWD_RQ: $display("INFO: SPC2WBM: Request of Type FWD_RQ");
|
`FWD_RQ: $display("INFO: SPC2WBM: Request of Type FWD_RQ");
|
`FWD_RPY: $display("INFO: SPC2WBM: Request of Type FWD_RPY");
|
`FWD_RPY: $display("INFO: SPC2WBM: Request of Type FWD_RPY");
|
`RSVD_RQ: $display("INFO: SPC2WBM: Request of Type RSVD_RQ");
|
`RSVD_RQ: $display("INFO: SPC2WBM: Request of Type RSVD_RQ");
|
default: $display("INFO: SPC2WBM: Request of Type Unknown");
|
default: $display("INFO: SPC2WBM: Request of Type Unknown");
|
endcase
|
endcase
|
if(spc2wbm_type==`IMISS_RQ) begin
|
$display("INFO: SPC2WBM: Non-Cacheable is %X", spc2wbm_nc);
|
if(spc2wbm_rnwd_or_ncif==1) $display("INFO: SPC2WBM: Request is Non-Cacheable");
|
$display("INFO: SPC2WBM: CPU-ID is %X", spc2wbm_cpu_id);
|
else $display("INFO: SPC2WBM: Request is Cacheable");
|
|
end else begin
|
|
if(spc2wbm_rnwd_or_ncif==1) $display("INFO: SPC2WBM: Request is a Read Access");
|
|
else $display("INFO: SPC2WBM: Request is a Write Access");
|
|
end
|
|
$display("INFO: SPC2WBM: CPU ID is %X", spc2wbm_cpu_id);
|
|
$display("INFO: SPC2WBM: Thread is %X", spc2wbm_thread);
|
$display("INFO: SPC2WBM: Thread is %X", spc2wbm_thread);
|
$display("INFO: SPC2WBM: Buffer is %X", spc2wbm_buffer);
|
$display("INFO: SPC2WBM: Invalidate All is %X", spc2wbm_invalidate);
|
$display("INFO: SPC2WBM: Packet ID is %X", spc2wbm_packet_id);
|
$display("INFO: SPC2WBM: Replaced L1 Way is %X", spc2wbm_way);
|
case(spc2wbm_size)
|
case(spc2wbm_size)
|
`PCX_SZ_1B: $display("INFO: SPC2WBM: Request size is 1 Byte");
|
`PCX_SZ_1B: $display("INFO: SPC2WBM: Request size is 1 Byte");
|
`PCX_SZ_2B: $display("INFO: SPC2WBM: Request size is 2 Bytes");
|
`PCX_SZ_2B: $display("INFO: SPC2WBM: Request size is 2 Bytes");
|
`PCX_SZ_4B: $display("INFO: SPC2WBM: Request size is 4 Bytes");
|
`PCX_SZ_4B: $display("INFO: SPC2WBM: Request size is 4 Bytes");
|
`PCX_SZ_8B: $display("INFO: SPC2WBM: Request size is 8 Bytes");
|
`PCX_SZ_8B: $display("INFO: SPC2WBM: Request size is 8 Bytes");
|
`PCX_SZ_16B: $display("INFO: SPC2WBM: Request size is 16 Bytes");
|
`PCX_SZ_16B: $display("INFO: SPC2WBM: Request size is 16 Bytes");
|
default: $display("INFO: SPC2WBM: Request size is Unknown");
|
default: $display("INFO: SPC2WBM: Request size is Unknown");
|
endcase
|
endcase
|
$display("INFO: SPC2WBM: Error is %X", spc2wbm_error);
|
|
$display("INFO: SPC2WBM: Address is %X", spc2wbm_addr);
|
$display("INFO: SPC2WBM: Address is %X", spc2wbm_addr);
|
$display("INFO: SPC2WBM: Data is %X", spc2wbm_data);
|
$display("INFO: SPC2WBM: Data is %X", spc2wbm_data);
|
$display("INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master");
|
$display("INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master");
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
| Line 434... |
Line 429... |
wbm_data_o = 64'b0;
|
wbm_data_o = 64'b0;
|
wbm_sel_o = 8'b0;
|
wbm_sel_o = 8'b0;
|
|
|
// Latch the data and set up the return packet for the SPARC Core
|
// Latch the data and set up the return packet for the SPARC Core
|
wbm2spc_valid = 1;
|
wbm2spc_valid = 1;
|
wbm2spc_rnwd_or_ncif = spc2wbm_rnwd_or_ncif;
|
|
if(spc2wbm_addr[3]==0)
|
|
wbm2spc_data = { wbm_data_i, 64'b0 };
|
|
else
|
|
wbm2spc_data = { 64'b0, wbm_data_i };
|
|
case(spc2wbm_type)
|
case(spc2wbm_type)
|
`IMISS_RQ: begin
|
`IMISS_RQ: begin
|
wbm2spc_type = `IFILL_RET; // I-Cache Miss
|
wbm2spc_type = `IFILL_RET; // I-Cache Miss
|
end
|
end
|
`LOAD_RQ: begin
|
`LOAD_RQ: begin
|
| Line 451... |
Line 441... |
`STORE_RQ: begin
|
`STORE_RQ: begin
|
wbm2spc_type = `ST_ACK; // Store
|
wbm2spc_type = `ST_ACK; // Store
|
end
|
end
|
endcase
|
endcase
|
wbm2spc_error = 0;
|
wbm2spc_error = 0;
|
|
wbm2spc_nc = spc2wbm_nc;
|
wbm2spc_thread = spc2wbm_thread;
|
wbm2spc_thread = spc2wbm_thread;
|
// CHECK THIS!!!!!!!
|
wbm2spc_way_valid = 0;
|
// wbm2spc_packet_id = spc2wbm_packet_id;
|
wbm2spc_way = 0;
|
if(spc2wbm_region==5'b10000) wbm2spc_packet_id = 2'b01;
|
if(spc2wbm_addr[3]==0) wbm2spc_data = { wbm_data_i, 64'b0 };
|
else wbm2spc_packet_id = 2'b00;
|
else wbm2spc_data = { 64'b0, wbm_data_i };
|
|
|
// See if other 64-bit Wishbone accesses are required
|
// See if other 64-bit Wishbone accesses are required
|
if(
|
if(
|
// Instruction miss directed to RAM expects 256 bits
|
// Instruction miss directed to RAM expects 256 bits
|
( (spc2wbm_type==`IMISS_RQ)&&(spc2wbm_region!=5'b10000) ) ||
|
( (spc2wbm_type==`IMISS_RQ)&&(spc2wbm_region!=5'b10000) ) ||
|
| Line 518... |
Line 509... |
// In the meanwhile we can return the first 128-bit packet
|
// In the meanwhile we can return the first 128-bit packet
|
end else if(state==`STATE_ACCESS3_BEGIN) begin
|
end else if(state==`STATE_ACCESS3_BEGIN) begin
|
|
|
// Return the packet to the SPARC Core
|
// Return the packet to the SPARC Core
|
spc_ready_o = 1;
|
spc_ready_o = 1;
|
spc_packetin_o = wbm2spc_packet_dat;
|
spc_packetin_o = wbm2spc_packet;
|
|
|
// Issue a third request on the Wishbone bus
|
// Issue a third request on the Wishbone bus
|
wbm_cycle_o = 1;
|
wbm_cycle_o = 1;
|
wbm_strobe_o = 1;
|
wbm_strobe_o = 1;
|
wbm_we_o = 0;
|
wbm_we_o = 0;
|
| Line 530... |
Line 521... |
wbm_data_o = 64'b0;
|
wbm_data_o = 64'b0;
|
wbm_sel_o = 8'b11111111;
|
wbm_sel_o = 8'b11111111;
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
// Print details of return packet
|
// Print details of return packet
|
if(wbm2spc_valid==1) $display("INFO: WBM2SPC: Return packet has valid bit");
|
$display("INFO: WBM2SPC: Return packet has valid bit %X", wbm2spc_valid);
|
else $display("INFO: WBM2SPC: Return packet has not valid bit");
|
|
case(wbm2spc_type)
|
case(wbm2spc_type)
|
`IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
|
`IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
|
`LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
|
`LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
|
`ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
|
`ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
|
default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
|
default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
|
endcase
|
endcase
|
if(wbm2spc_type==`IFILL_RET) begin
|
|
if(wbm2spc_rnwd_or_ncif==1) $display("INFO: WBM2SPC: Return Packet is Non-Cacheable");
|
|
else $display("INFO: WBM2SPC: Return Packet is Cacheable");
|
|
end else begin
|
|
if(spc2wbm_rnwd_or_ncif==1) $display("INFO: WBM2SPC: Return Packet is a Read Access");
|
|
else $display("INFO: WBM2SPC: Return Packet is a Write Access");
|
|
end
|
|
$display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
|
|
$display("INFO: WBM2SPC: Packet ID is %X", wbm2spc_packet_id);
|
|
$display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
|
$display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
|
|
$display("INFO: WBM2SPC: Non-Cacheable is %X", wbm2spc_nc);
|
|
$display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
|
|
$display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
|
|
$display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
|
$display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
|
$display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
|
$display("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core");
|
$display("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core");
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
// Unconditional state change
|
// Unconditional state change
|
| Line 625... |
Line 610... |
// We can start returning the packet to the SPARC Core
|
// We can start returning the packet to the SPARC Core
|
end else if(state==`STATE_PACKET_READY) begin
|
end else if(state==`STATE_PACKET_READY) begin
|
|
|
// Return the packet to the SPARC Core
|
// Return the packet to the SPARC Core
|
spc_ready_o = 1;
|
spc_ready_o = 1;
|
spc_packetin_o = wbm2spc_packet_dat;
|
spc_packetin_o = wbm2spc_packet;
|
|
|
// Unconditional state change
|
// Unconditional state change
|
state = `STATE_IDLE;
|
state = `STATE_IDLE;
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
// Print details of return packet
|
// Print details of return packet
|
if(wbm2spc_valid==1) $display("INFO: WBM2SPC: Return packet has valid bit");
|
$display("INFO: WBM2SPC: Valid bit is %X", wbm2spc_valid);
|
else $display("INFO: WBM2SPC: Return packet has not valid bit");
|
|
case(wbm2spc_type)
|
case(wbm2spc_type)
|
`IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
|
`IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
|
`LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
|
`LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
|
`ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
|
`ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
|
default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
|
default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
|
endcase
|
endcase
|
if(wbm2spc_type==`IFILL_RET) begin
|
|
if(wbm2spc_rnwd_or_ncif==1) $display("INFO: WBM2SPC: Return Packet is Non-Cacheable");
|
|
else $display("INFO: WBM2SPC: Return Packet is Cacheable");
|
|
end else begin
|
|
if(spc2wbm_rnwd_or_ncif==1) $display("INFO: WBM2SPC: Return Packet is a Read Access");
|
|
else $display("INFO: WBM2SPC: Return Packet is a Write Access");
|
|
end
|
|
$display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
|
|
$display("INFO: WBM2SPC: Packet ID is %X", wbm2spc_packet_id);
|
|
$display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
|
$display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
|
|
$display("INFO: WBM2SPC: Non-Cacheable bit is %X", wbm2spc_nc);
|
|
$display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
|
|
$display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
|
|
$display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
|
$display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
|
$display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
|
$display("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core");
|
$display("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core");
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
end
|
end
|
