| Line 84... |
Line 84... |
*/
|
*/
|
|
|
// Registers to latch requests from SPARC Core to Wishbone Master
|
// Registers to latch requests from SPARC Core to Wishbone Master
|
reg[3:0] state;
|
reg[3:0] state;
|
reg[4:0] spc2wbm_region; // Target region number (one-hot encoded)
|
reg[4:0] spc2wbm_region; // Target region number (one-hot encoded)
|
reg spc2wbm_atom;
|
reg spc2wbm_atomic; // Request is Atomic
|
reg[(`PCX_WIDTH-1):0] spc2wbm_packet; // Latched Packet
|
reg[(`PCX_WIDTH-1):0] spc2wbm_packet; // Latched Packet
|
|
|
// Wishbone Master to SPARC Core info used to encode the return packet
|
// Wishbone Master to SPARC Core info used to encode the return packet
|
reg wbm2spc_valid; // Valid
|
reg wbm2spc_valid; // Valid
|
reg[(`CPX_RQ_HI-`CPX_RQ_LO):0] wbm2spc_type; // Request type
|
reg[(`CPX_RQ_HI-`CPX_RQ_LO):0] wbm2spc_type; // Request type
|
reg[(`CPX_ERR_HI-`CPX_ERR_LO):0] wbm2spc_error; // Error
|
reg wbm2spc_miss; // L2 Miss
|
|
reg[(`CPX_ERR_HI-`CPX_ERR_LO-1):0] wbm2spc_error; // Error
|
reg wbm2spc_nc; // Non-Cacheable
|
reg wbm2spc_nc; // Non-Cacheable
|
reg[(`CPX_TH_HI-`CPX_TH_LO):0] wbm2spc_thread; // Thread
|
reg[(`CPX_TH_HI-`CPX_TH_LO):0] wbm2spc_thread; // Thread
|
reg wbm2spc_way_valid; // L2 Way Valid
|
reg wbm2spc_way_valid; // L2 Way Valid
|
reg[(`CPX_WY_HI-`CPX_WY_LO):0] wbm2spc_way; // Replaced L2 Way
|
reg[(`CPX_WY_HI-`CPX_WY_LO):0] wbm2spc_way; // Replaced L2 Way
|
|
reg wbm2spc_boot_fetch; // Fetch for Boot
|
|
reg wbm2spc_atomic; // Atomic LD/ST or 2nd IFill packet
|
|
reg wbm2spc_pfl; // PFL
|
reg[(`CPX_DA_HI-`CPX_DA_LO):0] wbm2spc_data; // Load Data
|
reg[(`CPX_DA_HI-`CPX_DA_LO):0] wbm2spc_data; // Load Data
|
reg[6:0] wbm2spc_interrupt_source; // Encoded Interrupt Source
|
reg[6:0] wbm2spc_interrupt_source; // Encoded Interrupt Source
|
reg wbm2spc_interrupt_new; // New Interrupt Pending
|
reg wbm2spc_interrupt_new; // New Interrupt Pending
|
|
|
|
|
| Line 156... |
Line 160... |
assign spc2wbm_size = spc2wbm_packet[`PCX_SZ_HI:`PCX_SZ_LO];
|
assign spc2wbm_size = spc2wbm_packet[`PCX_SZ_HI:`PCX_SZ_LO];
|
assign spc2wbm_addr = spc2wbm_packet[`PCX_AD_HI:`PCX_AD_LO];
|
assign spc2wbm_addr = spc2wbm_packet[`PCX_AD_HI:`PCX_AD_LO];
|
assign spc2wbm_data = spc2wbm_packet[`PCX_DA_HI:`PCX_DA_LO];
|
assign spc2wbm_data = spc2wbm_packet[`PCX_DA_HI:`PCX_DA_LO];
|
|
|
// Encode info going to the SPC side assembling return packets
|
// Encode info going to the SPC side assembling return packets
|
assign wbm2spc_packet = { wbm2spc_valid, wbm2spc_type, wbm2spc_error, wbm2spc_nc,
|
assign wbm2spc_packet = { wbm2spc_valid, wbm2spc_type, wbm2spc_miss, wbm2spc_error, wbm2spc_nc, wbm2spc_thread,
|
wbm2spc_thread, wbm2spc_way_valid, wbm2spc_way, 3'b100, wbm2spc_data };
|
wbm2spc_way_valid, wbm2spc_way, wbm2spc_boot_fetch, wbm2spc_atomic, wbm2spc_pfl, wbm2spc_data };
|
|
|
/*
|
/*
|
* State Machine
|
* State Machine
|
*/
|
*/
|
|
|
| Line 186... |
Line 190... |
|
|
// Prepare wakeup packet for SPARC Core, the resulting output is
|
// Prepare wakeup packet for SPARC Core, the resulting output is
|
// spc_packetin_o = `CPX_WIDTH'h1700000000000000000000000000000010001;
|
// spc_packetin_o = `CPX_WIDTH'h1700000000000000000000000000000010001;
|
wbm2spc_valid = 1;
|
wbm2spc_valid = 1;
|
wbm2spc_type = `INT_RET;
|
wbm2spc_type = `INT_RET;
|
|
wbm2spc_miss = 0;
|
wbm2spc_error = 0;
|
wbm2spc_error = 0;
|
wbm2spc_nc = 0;
|
wbm2spc_nc = 0;
|
wbm2spc_thread = 0;
|
wbm2spc_thread = 0;
|
wbm2spc_way_valid = 0;
|
wbm2spc_way_valid = 0;
|
wbm2spc_way = 0;
|
wbm2spc_way = 0;
|
|
wbm2spc_boot_fetch = 0;
|
|
wbm2spc_atomic = 0;
|
|
wbm2spc_pfl = 0;
|
wbm2spc_data = 64'h10001;
|
wbm2spc_data = 64'h10001;
|
|
|
// Clear state machine
|
// Clear state machine
|
state = `STATE_WAKEUP;
|
state = `STATE_WAKEUP;
|
|
|
| Line 232... |
Line 240... |
// Stall other requests from the SPARC Core
|
// Stall other requests from the SPARC Core
|
spc_stallreq_o = 1;
|
spc_stallreq_o = 1;
|
|
|
// Latch target region and atomicity
|
// Latch target region and atomicity
|
spc2wbm_region = spc_req_i;
|
spc2wbm_region = spc_req_i;
|
spc2wbm_atom = spc_atom_i;
|
spc2wbm_atomic = spc_atom_i;
|
|
|
// Jump to next state
|
// Jump to next state
|
state = `STATE_REQUEST_LATCHED;
|
state = `STATE_REQUEST_LATCHED;
|
|
|
// See if the interrupt vector has changed
|
// See if the interrupt vector has changed
|
| Line 246... |
Line 254... |
wbm2spc_interrupt_new = 1;
|
wbm2spc_interrupt_new = 1;
|
|
|
// Prepare the interrupt packet for the SPARC Core
|
// Prepare the interrupt packet for the SPARC Core
|
wbm2spc_valid = 1;
|
wbm2spc_valid = 1;
|
wbm2spc_type = `INT_RET;
|
wbm2spc_type = `INT_RET;
|
|
wbm2spc_miss = 0;
|
wbm2spc_error = 0;
|
wbm2spc_error = 0;
|
wbm2spc_nc = 0;
|
wbm2spc_nc = 0;
|
wbm2spc_thread = 0;
|
wbm2spc_thread = 0;
|
wbm2spc_way_valid = 0;
|
wbm2spc_way_valid = 0;
|
wbm2spc_way = 0;
|
wbm2spc_way = 0;
|
|
wbm2spc_boot_fetch = 0;
|
|
wbm2spc_atomic = 0;
|
|
wbm2spc_pfl = 0;
|
|
|
// Stall other requests from the SPARC Core
|
// Stall other requests from the SPARC Core
|
spc_stallreq_o = 1;
|
spc_stallreq_o = 1;
|
|
|
// Next cycle see if there's an int to be forwarded to the Core
|
// Next cycle see if there's an int to be forwarded to the Core
|
| Line 305... |
Line 317... |
else if(spc2wbm_region[1]==1) $display("INFO: SPC2WBM: Request to RAM Bank 1");
|
else if(spc2wbm_region[1]==1) $display("INFO: SPC2WBM: Request to RAM Bank 1");
|
else if(spc2wbm_region[2]==1) $display("INFO: SPC2WBM: Request to RAM Bank 2");
|
else if(spc2wbm_region[2]==1) $display("INFO: SPC2WBM: Request to RAM Bank 2");
|
else if(spc2wbm_region[3]==1) $display("INFO: SPC2WBM: Request to RAM Bank 3");
|
else if(spc2wbm_region[3]==1) $display("INFO: SPC2WBM: Request to RAM Bank 3");
|
else if(spc2wbm_region[4]==1) $display("INFO: SPC2WBM: Request targeted to I/O Block");
|
else if(spc2wbm_region[4]==1) $display("INFO: SPC2WBM: Request targeted to I/O Block");
|
else $display("INFO: SPC2WBM: Request to target region unknown");
|
else $display("INFO: SPC2WBM: Request to target region unknown");
|
if(spc2wbm_atom==1) $display("INFO: SPC2WBM: Request is ATOMIC");
|
if(spc2wbm_atomic==1) $display("INFO: SPC2WBM: Request is ATOMIC");
|
else $display("INFO: SPC2WBM: Request is not atomic");
|
else $display("INFO: SPC2WBM: Request is not atomic");
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
// Unconditional state change
|
// Unconditional state change
|
state = `STATE_PACKET_LATCHED;
|
state = `STATE_PACKET_LATCHED;
|
| Line 391... |
Line 403... |
`FWD_RQ: $display("INFO: SPC2WBM: Request of Type FWD_RQ");
|
`FWD_RQ: $display("INFO: SPC2WBM: Request of Type FWD_RQ");
|
`FWD_RPY: $display("INFO: SPC2WBM: Request of Type FWD_RPY");
|
`FWD_RPY: $display("INFO: SPC2WBM: Request of Type FWD_RPY");
|
`RSVD_RQ: $display("INFO: SPC2WBM: Request of Type RSVD_RQ");
|
`RSVD_RQ: $display("INFO: SPC2WBM: Request of Type RSVD_RQ");
|
default: $display("INFO: SPC2WBM: Request of Type Unknown");
|
default: $display("INFO: SPC2WBM: Request of Type Unknown");
|
endcase
|
endcase
|
$display("INFO: SPC2WBM: Non-Cacheable is %X", spc2wbm_nc);
|
$display("INFO: SPC2WBM: Non-Cacheable bit is %X", spc2wbm_nc);
|
$display("INFO: SPC2WBM: CPU-ID is %X", spc2wbm_cpu_id);
|
$display("INFO: SPC2WBM: CPU-ID is %X", spc2wbm_cpu_id);
|
$display("INFO: SPC2WBM: Thread is %X", spc2wbm_thread);
|
$display("INFO: SPC2WBM: Thread is %X", spc2wbm_thread);
|
$display("INFO: SPC2WBM: Invalidate All is %X", spc2wbm_invalidate);
|
$display("INFO: SPC2WBM: Invalidate All is %X", spc2wbm_invalidate);
|
$display("INFO: SPC2WBM: Replaced L1 Way is %X", spc2wbm_way);
|
$display("INFO: SPC2WBM: Replaced L1 Way is %X", spc2wbm_way);
|
case(spc2wbm_size)
|
case(spc2wbm_size)
|
| Line 406... |
Line 418... |
`PCX_SZ_16B: $display("INFO: SPC2WBM: Request size is 16 Bytes");
|
`PCX_SZ_16B: $display("INFO: SPC2WBM: Request size is 16 Bytes");
|
default: $display("INFO: SPC2WBM: Request size is Unknown");
|
default: $display("INFO: SPC2WBM: Request size is Unknown");
|
endcase
|
endcase
|
$display("INFO: SPC2WBM: Address is %X", spc2wbm_addr);
|
$display("INFO: SPC2WBM: Address is %X", spc2wbm_addr);
|
$display("INFO: SPC2WBM: Data is %X", spc2wbm_data);
|
$display("INFO: SPC2WBM: Data is %X", spc2wbm_data);
|
$display("INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master");
|
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
// Unconditional state change
|
// Unconditional state change
|
state = `STATE_REQUEST_GRANTED;
|
state = `STATE_REQUEST_GRANTED;
|
|
|
| Line 420... |
Line 431... |
|
|
// Wait until Wishbone access completes
|
// Wait until Wishbone access completes
|
if(wbm_ack_i==1) begin
|
if(wbm_ack_i==1) begin
|
|
|
// Clear previously modified outputs
|
// Clear previously modified outputs
|
if(spc2wbm_atom==0) wbm_cycle_o = 0;
|
if(spc2wbm_atomic==0) wbm_cycle_o = 0;
|
wbm_strobe_o = 0;
|
wbm_strobe_o = 0;
|
wbm_we_o = 0;
|
wbm_we_o = 0;
|
wbm_addr_o = 64'b0;
|
wbm_addr_o = 64'b0;
|
wbm_data_o = 64'b0;
|
wbm_data_o = 64'b0;
|
wbm_sel_o = 8'b0;
|
wbm_sel_o = 8'b0;
|
| Line 432... |
Line 443... |
// Latch the data and set up the return packet for the SPARC Core
|
// Latch the data and set up the return packet for the SPARC Core
|
wbm2spc_valid = 1;
|
wbm2spc_valid = 1;
|
case(spc2wbm_type)
|
case(spc2wbm_type)
|
`IMISS_RQ: begin
|
`IMISS_RQ: begin
|
wbm2spc_type = `IFILL_RET; // I-Cache Miss
|
wbm2spc_type = `IFILL_RET; // I-Cache Miss
|
|
wbm2spc_atomic = 0;
|
end
|
end
|
`LOAD_RQ: begin
|
`LOAD_RQ: begin
|
wbm2spc_type = `LOAD_RET; // Load
|
wbm2spc_type = `LOAD_RET; // Load
|
|
wbm2spc_atomic = spc2wbm_atomic;
|
end
|
end
|
`STORE_RQ: begin
|
`STORE_RQ: begin
|
wbm2spc_type = `ST_ACK; // Store
|
wbm2spc_type = `ST_ACK; // Store
|
|
wbm2spc_atomic = spc2wbm_atomic;
|
end
|
end
|
endcase
|
endcase
|
|
wbm2spc_miss = 0;
|
wbm2spc_error = 0;
|
wbm2spc_error = 0;
|
wbm2spc_nc = spc2wbm_nc;
|
wbm2spc_nc = spc2wbm_nc;
|
wbm2spc_thread = spc2wbm_thread;
|
wbm2spc_thread = spc2wbm_thread;
|
wbm2spc_way_valid = 0;
|
wbm2spc_way_valid = 0;
|
wbm2spc_way = 0;
|
wbm2spc_way = 0;
|
|
if(spc2wbm_region==5'b10000) wbm2spc_boot_fetch = 1;
|
|
else wbm2spc_boot_fetch = 0;
|
|
wbm2spc_pfl = 0;
|
if(spc2wbm_addr[3]==0) wbm2spc_data = { wbm_data_i, 64'b0 };
|
if(spc2wbm_addr[3]==0) wbm2spc_data = { wbm_data_i, 64'b0 };
|
else wbm2spc_data = { 64'b0, wbm_data_i };
|
else wbm2spc_data = { 64'b0, wbm_data_i };
|
|
|
// See if other 64-bit Wishbone accesses are required
|
// See if other 64-bit Wishbone accesses are required
|
if(
|
if(
|
| Line 484... |
Line 502... |
|
|
// Wait until Wishbone access completes
|
// Wait until Wishbone access completes
|
if(wbm_ack_i==1) begin
|
if(wbm_ack_i==1) begin
|
|
|
// Clear previously modified outputs
|
// Clear previously modified outputs
|
if(spc2wbm_atom==0) wbm_cycle_o = 0;
|
if(spc2wbm_atomic==0) wbm_cycle_o = 0;
|
wbm_strobe_o = 0;
|
wbm_strobe_o = 0;
|
wbm_we_o = 0;
|
wbm_we_o = 0;
|
wbm_addr_o = 64'b0;
|
wbm_addr_o = 64'b0;
|
wbm_data_o = 64'b0;
|
wbm_data_o = 64'b0;
|
wbm_sel_o = 8'b0;
|
wbm_sel_o = 8'b0;
|
| Line 521... |
Line 539... |
wbm_data_o = 64'b0;
|
wbm_data_o = 64'b0;
|
wbm_sel_o = 8'b11111111;
|
wbm_sel_o = 8'b11111111;
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
// Print details of return packet
|
// Print details of return packet
|
$display("INFO: WBM2SPC: Return packet has valid bit %X", wbm2spc_valid);
|
$display("INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE ***");
|
|
$display("INFO: WBM2SPC: Valid bit is %X", wbm2spc_valid);
|
case(wbm2spc_type)
|
case(wbm2spc_type)
|
`IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
|
`IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
|
`LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
|
`LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
|
`ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
|
`ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
|
default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
|
default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
|
endcase
|
endcase
|
|
$display("INFO: WBM2SPC: L2 Miss is %X", wbm2spc_miss);
|
$display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
|
$display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
|
$display("INFO: WBM2SPC: Non-Cacheable is %X", wbm2spc_nc);
|
$display("INFO: WBM2SPC: Non-Cacheable bit is %X", wbm2spc_nc);
|
$display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
|
$display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
|
$display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
|
$display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
|
$display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
|
$display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
|
|
$display("INFO: WBM2SPC: Fetch for Boot is %X", wbm2spc_boot_fetch);
|
|
$display("INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is %X", wbm2spc_atomic);
|
|
$display("INFO: WBM2SPC: PFL is %X", wbm2spc_pfl);
|
$display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
|
$display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
|
$display("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core");
|
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
// Unconditional state change
|
// Unconditional state change
|
state = `STATE_ACCESS3_END;
|
state = `STATE_ACCESS3_END;
|
|
|
| Line 551... |
Line 573... |
|
|
// Wait until Wishbone access completes
|
// Wait until Wishbone access completes
|
if(wbm_ack_i==1) begin
|
if(wbm_ack_i==1) begin
|
|
|
// Clear previously modified outputs
|
// Clear previously modified outputs
|
if(spc2wbm_atom==0) wbm_cycle_o = 0;
|
if(spc2wbm_atomic==0) wbm_cycle_o = 0;
|
wbm_strobe_o = 0;
|
wbm_strobe_o = 0;
|
wbm_we_o = 0;
|
wbm_we_o = 0;
|
wbm_addr_o = 64'b0;
|
wbm_addr_o = 64'b0;
|
wbm_data_o = 64'b0;
|
wbm_data_o = 64'b0;
|
wbm_sel_o = 8'b0;
|
wbm_sel_o = 8'b0;
|
| Line 589... |
Line 611... |
|
|
// Wait until Wishbone access completes
|
// Wait until Wishbone access completes
|
if(wbm_ack_i==1) begin
|
if(wbm_ack_i==1) begin
|
|
|
// Clear previously modified outputs
|
// Clear previously modified outputs
|
if(spc2wbm_atom==0) wbm_cycle_o = 0;
|
if(spc2wbm_atomic==0) wbm_cycle_o = 0;
|
wbm_strobe_o = 0;
|
wbm_strobe_o = 0;
|
wbm_we_o = 0;
|
wbm_we_o = 0;
|
wbm_addr_o = 64'b0;
|
wbm_addr_o = 64'b0;
|
wbm_data_o = 64'b0;
|
wbm_data_o = 64'b0;
|
wbm_sel_o = 8'b0;
|
wbm_sel_o = 8'b0;
|
|
|
// Latch the data and set up the return packet for the SPARC Core
|
// Latch the data and set up the return packet for the SPARC Core
|
|
wbm2spc_atomic = 1;
|
wbm2spc_data[63:0] = wbm_data_i;
|
wbm2spc_data[63:0] = wbm_data_i;
|
|
|
// Jump to next state
|
// Jump to next state
|
state = `STATE_PACKET_READY;
|
state = `STATE_PACKET_READY;
|
|
|
| Line 617... |
Line 640... |
// Unconditional state change
|
// Unconditional state change
|
state = `STATE_IDLE;
|
state = `STATE_IDLE;
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
// Print details of return packet
|
// Print details of return packet
|
|
$display("INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE ***");
|
$display("INFO: WBM2SPC: Valid bit is %X", wbm2spc_valid);
|
$display("INFO: WBM2SPC: Valid bit is %X", wbm2spc_valid);
|
case(wbm2spc_type)
|
case(wbm2spc_type)
|
`IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
|
`IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
|
`LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
|
`LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
|
`ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
|
`ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
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default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
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default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
|
endcase
|
endcase
|
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$display("INFO: WBM2SPC: L2 Miss is %X", wbm2spc_miss);
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$display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
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$display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
|
$display("INFO: WBM2SPC: Non-Cacheable bit is %X", wbm2spc_nc);
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$display("INFO: WBM2SPC: Non-Cacheable bit is %X", wbm2spc_nc);
|
$display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
|
$display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
|
$display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
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$display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
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$display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
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$display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
|
|
$display("INFO: WBM2SPC: Fetch for Boot is %X", wbm2spc_boot_fetch);
|
|
$display("INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is %X", wbm2spc_atomic);
|
|
$display("INFO: WBM2SPC: PFL is %X", wbm2spc_pfl);
|
$display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
|
$display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
|
$display("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core");
|
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
end
|
end
|
end
|
end
|
end
|
end
|
