URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [rtl/] [s1_top/] [spc2wbm.v] - Diff between revs 51 and 73

Rev 51	Rev 73
Line 103...	Line 103...
`reg wbm2spc_pfl; // PFL`	`reg wbm2spc_pfl; // PFL`
reg[(`CPX_DA_HI-`CPX_DA_LO):0] wbm2spc_data; // Load Data	reg[(`CPX_DA_HI-`CPX_DA_LO):0] wbm2spc_data; // Load Data
`reg[6:0] wbm2spc_interrupt_source; // Encoded Interrupt Source`	`reg[6:0] wbm2spc_interrupt_source; // Encoded Interrupt Source`
`reg wbm2spc_interrupt_new; // New Interrupt Pending`	`reg wbm2spc_interrupt_new; // New Interrupt Pending`


`/*`	`/*`
`* Wires`	`* Wires`
`*/`	`*/`

`// Decoded SPARC Core to Wishbone Master info`	`// Decoded SPARC Core to Wishbone Master info`
Line 200...	Line 199...
`wbm2spc_way <= 0;`	`wbm2spc_way <= 0;`
`wbm2spc_boot_fetch <= 0;`	`wbm2spc_boot_fetch <= 0;`
`wbm2spc_atomic <= 0;`	`wbm2spc_atomic <= 0;`
`wbm2spc_pfl <= 0;`	`wbm2spc_pfl <= 0;`
`wbm2spc_data <= 64'h10001;`	`wbm2spc_data <= 64'h10001;`

`// EDIT vvvv (uinitialized variables)`
`wbm2spc_interrupt_source <= 7'h0;`	`wbm2spc_interrupt_source <= 7'h0;`
`wbm2spc_interrupt_new <= 1'b0;`	`wbm2spc_interrupt_new <= 1'b0;`
`// EDIT ^^^^`

`// Clear state machine`	`// Clear state machine`
state <= `STATE_WAKEUP;	state <= `STATE_WAKEUP;

`end else begin`	`end else begin`