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Line 24... |
*/
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*/
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`include "s1_defs.h"
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`include "s1_defs.h"
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module spc2wbm (
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module spc2wbm (
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sys_clock_i, sys_reset_i, sys_interrupt_source_i,
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spc_req_i, spc_atom_i, spc_packetout_i,
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spc_grant_o, spc_ready_o, spc_packetin_o, spc_stallreq_o,
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wbm_ack_i, wbm_data_i,
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wbm_cycle_o, wbm_strobe_o, wbm_we_o, wbm_addr_o, wbm_data_o, wbm_sel_o
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);
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/*
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/*
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* Inputs
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* Inputs
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*/
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*/
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// System inputs
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// System inputs
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input sys_clock_i; // System Clock
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input sys_clock_i, // System Clock
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input sys_reset_i; // System Reset
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input sys_reset_i, // System Reset
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input[5:0] sys_interrupt_source_i; // Encoded Interrupt Source
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input[5:0] sys_interrupt_source_i, // Encoded Interrupt Source
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// SPARC-side inputs connected to the PCX (Processor-to-Cache Xbar) outputs of the SPARC Core
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// SPARC-side inputs connected to the PCX (Processor-to-Cache Xbar) outputs of the SPARC Core
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input[4:0] spc_req_i; // Request
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input[4:0] spc_req_i, // Request
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input spc_atom_i; // Atomic Request
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input spc_atom_i, // Atomic Request
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input[(`PCX_WIDTH-1):0] spc_packetout_i; // Outgoing Packet
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input[(`PCX_WIDTH-1):0] spc_packetout_i, // Outgoing Packet
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// Wishbone Master interface inputs
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// Wishbone Master interface inputs
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input wbm_ack_i; // Ack
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input wbm_ack_i, // Ack
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input[(`WB_DATA_WIDTH-1):0] wbm_data_i; // Data In
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input[(`WB_DATA_WIDTH-1):0] wbm_data_i, // Data In
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/*
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/*
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* Registered Outputs
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* Outputs
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*/
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*/
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// SPARC-side outputs connected to the CPX (Cache-to-Processor Xbar) inputs of the SPARC Core
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// SPARC-side outputs connected to the CPX (Cache-to-Processor Xbar) inputs of the SPARC Core
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output[4:0] spc_grant_o; // Grant
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output reg[4:0] spc_grant_o, // Grant
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reg[4:0] spc_grant_o; // Grant
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output reg spc_ready_o, // Ready
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output spc_ready_o; // Ready
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output reg[`CPX_WIDTH-1:0] spc_packetin_o, // Incoming Packet
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reg spc_ready_o; // Ready
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output reg spc_stall_o, // Stall Requests
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output[`CPX_WIDTH-1:0] spc_packetin_o; // Incoming Packet
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output reg spc_resume_o, // Resume Requests
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reg[`CPX_WIDTH-1:0] spc_packetin_o; // Incoming Packet
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output spc_stallreq_o; // Stall Request
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reg spc_stallreq_o; // Stall Request
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// Wishbone Master interface outputs
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// Wishbone Master interface outputs
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output wbm_cycle_o; // Cycle Start
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output reg wbm_cycle_o, // Cycle Start
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reg wbm_cycle_o; // Cycle Start
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output reg wbm_strobe_o, // Strobe Request
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output wbm_strobe_o; // Strobe Request
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output reg wbm_we_o, // Write Enable
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reg wbm_strobe_o; // Strobe Request
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output reg[`WB_ADDR_WIDTH-1:0] wbm_addr_o, // Address Bus
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output wbm_we_o; // Write Enable
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output reg[`WB_DATA_WIDTH-1:0] wbm_data_o, // Data Out
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reg wbm_we_o; // Write Enable
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output reg[`WB_DATA_WIDTH/8-1:0] wbm_sel_o // Select Output
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output[`WB_ADDR_WIDTH-1:0] wbm_addr_o; // Address Bus
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reg[`WB_ADDR_WIDTH-1:0] wbm_addr_o; // Address Bus
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);
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output[`WB_DATA_WIDTH-1:0] wbm_data_o; // Data Out
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reg[`WB_DATA_WIDTH-1:0] wbm_data_o; // Data Out
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output[`WB_DATA_WIDTH/8-1:0] wbm_sel_o; // Select Output
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reg[`WB_DATA_WIDTH/8-1:0] wbm_sel_o; // Select Output
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/*
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/*
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* Registers
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* Registers
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*/
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*/
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| Line 175... |
Line 163... |
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// Clear outputs going to SPARC Core inputs
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// Clear outputs going to SPARC Core inputs
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spc_grant_o <= 5'b00000;
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spc_grant_o <= 5'b00000;
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spc_ready_o <= 0;
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spc_ready_o <= 0;
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spc_packetin_o <= 0;
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spc_packetin_o <= 0;
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spc_stallreq_o <= 0;
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spc_stall_o <= 0;
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spc_resume_o <= 0;
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// Clear Wishbone Master interface outputs
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// Clear Wishbone Master interface outputs
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wbm_cycle_o <= 0;
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wbm_cycle_o <= 0;
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wbm_strobe_o <= 0;
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wbm_strobe_o <= 0;
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wbm_we_o <= 0;
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wbm_we_o <= 0;
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| Line 239... |
Line 228... |
// Clear previously modified outputs
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// Clear previously modified outputs
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spc_ready_o <= 0;
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spc_ready_o <= 0;
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spc_packetin_o <= 0;
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spc_packetin_o <= 0;
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// Stall other requests from the SPARC Core
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// Stall other requests from the SPARC Core
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spc_stallreq_o <= 1;
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spc_stall_o <= 1;
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// Latch target region and atomicity
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// Latch target region and atomicity
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spc2wbm_region <= spc_req_i;
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spc2wbm_region <= spc_req_i;
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spc2wbm_atomic <= spc_atom_i;
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spc2wbm_atomic <= spc_atom_i;
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Line 256... |
wbm2spc_way <= 0;
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wbm2spc_way <= 0;
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wbm2spc_boot_fetch <= 0;
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wbm2spc_boot_fetch <= 0;
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wbm2spc_atomic <= 0;
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wbm2spc_atomic <= 0;
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wbm2spc_pfl <= 0;
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wbm2spc_pfl <= 0;
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// Stall other requests from the SPARC Core
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spc_stallreq_o <= 1;
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// Next cycle see if there's an int to be forwarded to the Core
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// Next cycle see if there's an int to be forwarded to the Core
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end else if(wbm2spc_interrupt_source!=6'b000000 && wbm2spc_interrupt_new) begin
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end else if(wbm2spc_interrupt_source!=6'b000000 && wbm2spc_interrupt_new) begin
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// Clean the flag
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// Clean the flag
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wbm2spc_interrupt_new <= 0;
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wbm2spc_interrupt_new <= 0;
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// Send the interrupt packet to the Core
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// Send the interrupt packet to the Core
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spc_ready_o <= 1;
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spc_ready_o <= 1;
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spc_packetin_o <= wbm2spc_packet;
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spc_packetin_o <= wbm2spc_packet;
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// Stall other requests from the SPARC Core
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spc_stallreq_o <= 1;
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// Stay in this state
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// Stay in this state
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state <= `STATE_IDLE;
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state <= `STATE_IDLE;
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// Nothing to do, stay idle
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// Nothing to do, stay idle
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end else begin
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end else begin
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// Clear previously modified outputs
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// Clear previously modified outputs
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spc_ready_o <= 0;
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spc_ready_o <= 0;
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spc_packetin_o <= 0;
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spc_packetin_o <= 0;
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spc_stallreq_o <= 0;
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// Clear stall/resume signals
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spc_stall_o <= 0;
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spc_resume_o <= 0;
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// Stay in this state
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// Stay in this state
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state <= `STATE_IDLE;
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state <= `STATE_IDLE;
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end
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end
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Line 297... |
spc2wbm_packet <= spc_packetout_i;
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spc2wbm_packet <= spc_packetout_i;
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// Grant the request to the SPARC Core
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// Grant the request to the SPARC Core
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spc_grant_o <= spc2wbm_region;
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spc_grant_o <= spc2wbm_region;
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// Clear the stall signal
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spc_stall_o <= 0;
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// synopsys translate_off
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// synopsys translate_off
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// Print details of SPARC Core request
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// Print details of SPARC Core request
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`ifdef DEBUG
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`ifdef DEBUG
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$display("INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE ***");
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$display("INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE ***");
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if(spc2wbm_region[0]==1) $display("INFO: SPC2WBM: Request to RAM Bank 0");
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if(spc2wbm_region[0]==1) $display("INFO: SPC2WBM: Request to RAM Bank 0");
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Line 633... |
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// Return the packet to the SPARC Core
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// Return the packet to the SPARC Core
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spc_ready_o <= 1;
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spc_ready_o <= 1;
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spc_packetin_o <= wbm2spc_packet;
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spc_packetin_o <= wbm2spc_packet;
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// Resume requests
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spc_resume_o <= 1;
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// Unconditional state change
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// Unconditional state change
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state <= `STATE_IDLE;
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state <= `STATE_IDLE;
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// synopsys translate_off
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// synopsys translate_off
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// Print details of return packet
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// Print details of return packet
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