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//`include "iop.h"
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//`include "iop.h"
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//`include "fabric.h"
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//`include "fabric.h"
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_DCD
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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output [7:0] dcd_fuse_repair_value; //data out for redundancy register
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output [7:0] dcd_fuse_repair_value; //data out for redundancy register
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output [1:0] dcd_fuse_repair_en; //enable bits out
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output [1:0] dcd_fuse_repair_en; //enable bits out
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// Memory declaration.
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// Memory declaration.
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`ifdef DEFINE_0IN
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wire [143:0] temp_w0a;
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wire [143:0] temp_w1a;
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wire [143:0] temp_w2a;
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wire [143:0] temp_w3a;
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`else
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reg [143:0] w0 [127:0]/* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ; // way0, byte0. Data+Parity.
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reg [143:0] w0 [127:0]/* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ; // way0, byte0. Data+Parity.
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reg [143:0] w1 [127:0]/* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ; // way0, byte0. Data+Parity.
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reg [143:0] w1 [127:0]/* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ; // way0, byte0. Data+Parity.
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reg [143:0] w2 [127:0]/* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ; // way0, byte0. Data+Parity.
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reg [143:0] w2 [127:0]/* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ; // way0, byte0. Data+Parity.
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reg [143:0] w3 [127:0]/* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ; // way0, byte0. Data+Parity.
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reg [143:0] w3 [127:0]/* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ; // way0, byte0. Data+Parity.
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Line 144... |
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reg [143:0] temp_w0;
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reg [143:0] temp_w0;
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reg [143:0] temp_w1;
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reg [143:0] temp_w1;
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reg [143:0] temp_w2;
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reg [143:0] temp_w2;
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reg [143:0] temp_w3;
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reg [143:0] temp_w3;
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`endif
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reg [10:3] dcache_rwaddr_m ;
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reg [10:3] dcache_rwaddr_m ;
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reg [10:3] dcache_raddr_m ;
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reg [10:3] dcache_raddr_m ;
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reg dcache_rvld_m ;
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reg dcache_rvld_m ;
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reg wvld_m ;
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reg wvld_m ;
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reg [143:0] dcache_wdata_m ;
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reg [143:0] dcache_wdata_m ;
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end
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end
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assign dcache_wvld_m = wvld_m & ~rst_tri_en ;
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assign dcache_wvld_m = wvld_m & ~rst_tri_en ;
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`ifdef DEFINE_0IN
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wire [3:0] dc_we = dcache_wvld_m ? dcache_wr_rway_m : 4'b0;
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dc_data dc_data0 ( .nclk(~clk), .adr(dcache_rwaddr_m[10:4]),
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.we(dc_we [0] ), .wm(way_mask [143:0]),
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.din(dcache_wdata_m[143:0]), .dout(temp_w0a[143:0]) );
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dc_data dc_data1 ( .nclk(~clk), .adr(dcache_rwaddr_m[10:4]),
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.we(dc_we [1] ), .wm(way_mask [143:0]),
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.din(dcache_wdata_m[143:0]), .dout(temp_w1a[143:0]) );
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dc_data dc_data2 ( .nclk(~clk), .adr(dcache_rwaddr_m[10:4]),
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.we(dc_we [2] ), .wm(way_mask [143:0]),
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.din(dcache_wdata_m[143:0]), .dout(temp_w2a[143:0]) );
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dc_data dc_data3 ( .nclk(~clk), .adr(dcache_rwaddr_m[10:4]),
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.we(dc_we [3] ), .wm(way_mask [143:0]),
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.din(dcache_wdata_m[143:0]), .dout(temp_w3a[143:0]) );
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`else
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//=========================================================================================
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//=========================================================================================
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// generate wordlines
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// generate wordlines
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//=========================================================================================
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//=========================================================================================
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// Generate at posedge of clk.
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// Generate at posedge of clk.
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rw_wdline[ctr] = 1'b0;
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rw_wdline[ctr] = 1'b0;
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end
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end
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end
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end
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*/
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*/
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`ifdef FPGA_SYN_DCD
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`else
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always @ (clk or dcache_rwaddr_m or dcache_wvld_m or dcache_rvld_m)
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begin
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if (clk) begin
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for (ctr=8'h00;ctr<128;ctr=ctr+1)
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begin
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if (({1'b0,dcache_rwaddr_m[10:4]} == ctr) &
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(dcache_rvld_m | dcache_wvld_m))
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rw_wdline[ctr] = 1'b1;
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else
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rw_wdline[ctr] = 1'b0;
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end
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end
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end
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// JC modified end
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`endif
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//=========================================================================================
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//=========================================================================================
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// Read from Memory.
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// Read from Memory.
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//=========================================================================================
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//=========================================================================================
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`ifdef FPGA_SYN_DCD
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always @(posedge clk) begin
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always @(posedge clk) begin
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temp_w0a_reg[143:0] = w0[dcache_raddr_e[10:4]];
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temp_w0a_reg[143:0] = w0[dcache_raddr_e[10:4]];
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temp_w1a_reg[143:0] = w1[dcache_raddr_e[10:4]];
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temp_w1a_reg[143:0] = w1[dcache_raddr_e[10:4]];
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temp_w2a_reg[143:0] = w2[dcache_raddr_e[10:4]];
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temp_w2a_reg[143:0] = w2[dcache_raddr_e[10:4]];
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temp_w3a_reg[143:0] = w3[dcache_raddr_e[10:4]];
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temp_w3a_reg[143:0] = w3[dcache_raddr_e[10:4]];
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end
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end
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`else
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// Read
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always @ (negedge clk)
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begin
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for (i=0;i<128;i=i+1)
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begin
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if (rw_wdline[i] & dcache_rvld_m)
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begin
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temp_w0a_reg[143:0] <= w0[i];
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temp_w1a_reg[143:0] <= w1[i];
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temp_w2a_reg[143:0] <= w2[i];
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temp_w3a_reg[143:0] <= w3[i];
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end
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end
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end
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`endif
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//removed stablizer, zero out without read
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//removed stablizer, zero out without read
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assign temp_w0a[143:0] = dcache_rvld_m? temp_w0a_reg[143:0]: 144'b0;
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assign temp_w0a[143:0] = dcache_rvld_m? temp_w0a_reg[143:0]: 144'b0;
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assign temp_w1a[143:0] = dcache_rvld_m? temp_w1a_reg[143:0]: 144'b0;
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assign temp_w1a[143:0] = dcache_rvld_m? temp_w1a_reg[143:0]: 144'b0;
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assign temp_w2a[143:0] = dcache_rvld_m? temp_w2a_reg[143:0]: 144'b0;
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assign temp_w2a[143:0] = dcache_rvld_m? temp_w2a_reg[143:0]: 144'b0;
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assign temp_w3a[143:0] = dcache_rvld_m? temp_w3a_reg[143:0]: 144'b0;
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assign temp_w3a[143:0] = dcache_rvld_m? temp_w3a_reg[143:0]: 144'b0;
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`endif
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// Prior to SA, column mux (64(D)+8(P))x4 bits. Assume parity is
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// Prior to SA, column mux (64(D)+8(P))x4 bits. Assume parity is
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// at the end of the 144b line. Entry is wX||Parity
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// at the end of the 144b line. Entry is wX||Parity
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// Select either upper or lower 64b from each of the 4 ways.
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// Select either upper or lower 64b from each of the 4 ways.
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| Line 569... |
Line 569... |
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always @ (negedge clk)
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always @ (negedge clk)
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begin
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begin
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`ifdef FPGA_SYN_DCD
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if(dcache_wvld_m & dcache_wr_rway_m[0]) begin
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if(dcache_wvld_m & dcache_wr_rway_m[0]) begin
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w0[dcache_rwaddr_m[10:4]] = (temp_w0a_reg[143:0] & way_mask_inv[143:0]) |
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w0[dcache_rwaddr_m[10:4]] = (temp_w0a_reg[143:0] & way_mask_inv[143:0]) |
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(dcache_wdata_m[143:0] & way_mask[143:0]) ;
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(dcache_wdata_m[143:0] & way_mask[143:0]) ;
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end
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end
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Line 588... |
if(dcache_wvld_m & dcache_wr_rway_m[3]) begin
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if(dcache_wvld_m & dcache_wr_rway_m[3]) begin
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w3[dcache_rwaddr_m[10:4]] = (temp_w3a_reg[143:0] & way_mask_inv[143:0]) |
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w3[dcache_rwaddr_m[10:4]] = (temp_w3a_reg[143:0] & way_mask_inv[143:0]) |
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(dcache_wdata_m[143:0] & way_mask[143:0]) ;
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(dcache_wdata_m[143:0] & way_mask[143:0]) ;
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end
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end
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`else // !`ifdef FPGA_SYN_DCD
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for (j=0;j<128;j=j+1)
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begin
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if (rw_wdline[j] & dcache_wvld_m & dcache_wr_rway_m[0])
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begin
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// read
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temp_w0[143:0] = w0[j];
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// modify & write
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w0[j] = (temp_w0[143:0] & way_mask_inv[143:0]) |
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(dcache_wdata_m[143:0] & way_mask[143:0]) ;
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end
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if (rw_wdline[j] & dcache_wvld_m & dcache_wr_rway_m[1])
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begin
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// read
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temp_w1[143:0] = w1[j];
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// modify & write
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w1[j] = (temp_w1[143:0] & way_mask_inv[143:0]) |
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(dcache_wdata_m[143:0] & way_mask[143:0]) ;
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end
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if (rw_wdline[j] & dcache_wvld_m & dcache_wr_rway_m[2])
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begin
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// read
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temp_w2[143:0] = w2[j];
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// modify & write
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w2[j] = (temp_w2[143:0] & way_mask_inv[143:0]) |
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(dcache_wdata_m[143:0] & way_mask[143:0]) ;
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end
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if (rw_wdline[j] & dcache_wvld_m & dcache_wr_rway_m[3])
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begin
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// read
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temp_w3[143:0] = w3[j];
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// modify & write.
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w3[j] = (temp_w3[143:0] & way_mask_inv[143:0]) |
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(dcache_wdata_m[143:0] & way_mask[143:0]) ;
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end
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end
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`endif // !`ifdef FPGA_SYN_DCD
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// !`ifdef FPGA_SYN_DCD
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end // always @ (negedge clk)
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end // always @ (negedge clk)
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endmodule
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endmodule
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