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// Description: This is the floating point register file. It has one R/W port that is
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// Description: This is the floating point register file. It has one R/W port that is
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// 78 bits (64 bits data, 14 bits ecc) wide.
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// 78 bits (64 bits data, 14 bits ecc) wide.
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*/
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*/
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_FRF
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`endif
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module bw_r_frf (/*AUTOARG*/
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module bw_r_frf (/*AUTOARG*/
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// Outputs
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// Outputs
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so, frf_dp_data,
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so, frf_dp_data,
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// Inputs
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// Inputs
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output so;
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output so;
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output [77:0] frf_dp_data;
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output [77:0] frf_dp_data;
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wire [7:0] regfile_index;
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wire [7:0] regfile_index;
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//XST WA CR436004
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//XST WA CR436004
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wire [7:0] regfile_index_low;
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(* keep = "yes" *) wire [7:0] regfile_index_low;
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wire [7:0] regfile_index_high;
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(* keep = "yes" *) wire [7:0] regfile_index_high;
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//
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//
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`ifdef FPGA_SYN_FRF
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reg [38:0] regfile_high [127:0];
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reg [38:0] regfile_high [127:0];
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reg [38:0] regfile_low [127:0];
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reg [38:0] regfile_low [127:0];
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`else
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reg [38:0] regfile [255:0];
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`endif
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reg rst_tri_en_negedge;
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reg rst_tri_en_negedge;
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wire [77:0] read_data;
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wire [77:0] read_data;
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wire ren_d1;
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wire ren_d1;
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wire [6:0] addr_d1;
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wire [6:0] addr_d1;
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assign sehold_write_data[77:0] = (sehold)? write_data_d1[77:0]: dp_frf_data[77:0];
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assign sehold_write_data[77:0] = (sehold)? write_data_d1[77:0]: dp_frf_data[77:0];
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assign sehold_cntl_data[9:0] = (sehold)? {addr_d1[6:0],wen_d1[1:0], ren_d1}:
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assign sehold_cntl_data[9:0] = (sehold)? {addr_d1[6:0],wen_d1[1:0], ren_d1}:
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{ctl_frf_addr[6:0],ctl_frf_wen[1:0],ctl_frf_ren};
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{ctl_frf_addr[6:0],ctl_frf_wen[1:0],ctl_frf_ren};
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// All inputs go through flop
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// All inputs go through flop
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dff #(39) datain_dff1(.din(sehold_write_data[77:39]), .clk(rclk), .q(write_data_d1[77:39]),
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dff_s #(39) datain_dff1(.din(sehold_write_data[77:39]), .clk(rclk), .q(write_data_d1[77:39]),
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.se(real_se), .si({cntl_scan_data[0],write_scan_data_lo[38:1]}),
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.se(real_se), .si({cntl_scan_data[0],write_scan_data_lo[38:1]}),
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.so(write_scan_data_hi[38:0]));
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.so(write_scan_data_hi[38:0]));
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dff #(39) datain_dff2(.din(sehold_write_data[38:0]), .clk(rclk), .q(write_data_d1[38:0]),
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dff_s #(39) datain_dff2(.din(sehold_write_data[38:0]), .clk(rclk), .q(write_data_d1[38:0]),
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.se(real_se), .si(write_scan_data_hi[38:0]), .so(write_scan_data_lo[38:0]));
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.se(real_se), .si(write_scan_data_hi[38:0]), .so(write_scan_data_lo[38:0]));
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dff #(10) controlin_dff(.din(sehold_cntl_data[9:0]),
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dff_s #(10) controlin_dff(.din(sehold_cntl_data[9:0]),
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.q({addr_d1[6:0],wen_d1[1:0],ren_d1}),
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.q({addr_d1[6:0],wen_d1[1:0],ren_d1}),
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.clk(rclk), .se(real_se), .si({si,cntl_scan_data[9:1]}), .so(cntl_scan_data[9:0]));
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.clk(rclk), .se(real_se), .si({si,cntl_scan_data[9:1]}), .so(cntl_scan_data[9:0]));
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// Read logic
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// Read logic
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`ifdef FPGA_SYN_FRF
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assign read_data[77:0] = (~ren_d1)? 78'b0:
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assign read_data[77:0] = (~ren_d1)? 78'b0:
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(wen_d1[1]|wen_d1[0])? {78{1'bx}}:
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(wen_d1[1]|wen_d1[0])? {78{1'bx}}:
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{regfile_high[regfile_index_high[7:1]],regfile_low[regfile_index_low[7:1]]};
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{regfile_high[regfile_index_high[7:1]],regfile_low[regfile_index_low[7:1]]};
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`else
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assign read_data[77:0] = (~ren_d1)? 78'b0:
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(wen_d1[1]|wen_d1[0])? {78{1'bx}}:
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{regfile[regfile_index_high],regfile[regfile_index_low]};
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`endif
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dff_s #(39) dataout_dff1(.din(read_data[77:39]), .clk(rclk), .q(frf_dp_data[77:39]),
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dff #(39) dataout_dff1(.din(read_data[77:39]), .clk(rclk), .q(frf_dp_data[77:39]),
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.se(real_se), .si(read_scan_data_lo[38:0]), .so(read_scan_data_hi[38:0]));
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.se(real_se), .si(read_scan_data_lo[38:0]), .so(read_scan_data_hi[38:0]));
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dff #(39) dataout_dff2(.din(read_data[38:0]), .clk(rclk), .q(frf_dp_data[38:0]),
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dff_s #(39) dataout_dff2(.din(read_data[38:0]), .clk(rclk), .q(frf_dp_data[38:0]),
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.se(real_se), .si({read_scan_data_hi[37:0],write_scan_data_lo[0]}),
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.se(real_se), .si({read_scan_data_hi[37:0],write_scan_data_lo[0]}),
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.so(read_scan_data_lo[38:0]));
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.so(read_scan_data_lo[38:0]));
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assign so = read_scan_data_hi[38];
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assign so = read_scan_data_hi[38];
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always @ (posedge rclk) begin
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always @ (posedge rclk) begin
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// Write port
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// Write port
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// write is gated by rst_tri_en
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// write is gated by rst_tri_en
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`ifdef FPGA_SYN_FRF
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if (wen_d1[0] & ~ren_d1 & ~rst_tri_en_negedge) begin
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if (wen_d1[0] & ~ren_d1 & ~rst_tri_en_negedge) begin
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regfile_low[regfile_index_low[7:1]] <= write_data_d1[38:0];
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regfile_low[regfile_index_low[7:1]] <= write_data_d1[38:0];
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end
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end
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if (wen_d1[1] & ~ren_d1 & ~rst_tri_en_negedge) begin
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if (wen_d1[1] & ~ren_d1 & ~rst_tri_en_negedge) begin
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regfile_high[regfile_index_high[7:1]] <= write_data_d1[77:39];
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regfile_high[regfile_index_high[7:1]] <= write_data_d1[77:39];
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end
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end
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`else
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if (wen_d1[0] & ~ren_d1 & ~rst_tri_en_negedge) begin
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regfile[regfile_index_low] <= write_data_d1[38:0];
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end
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if (wen_d1[1] & ~ren_d1 & ~rst_tri_en_negedge) begin
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regfile[regfile_index_high] <= write_data_d1[77:39];
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end
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`endif
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end
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end
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always @ (negedge rclk) begin
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always @ (negedge rclk) begin
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// latch rst_tri_en
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// latch rst_tri_en
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rst_tri_en_negedge <= rst_tri_en;
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rst_tri_en_negedge <= rst_tri_en;
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end
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end
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