Line 41... |
Line 41... |
////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_IDCT
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`endif
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`ifdef FPGA_SYN_IDCT
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module bw_r_idct(rdtag_w0_y, rdtag_w1_y, rdtag_w2_y, rdtag_w3_y, so, rclk, se,
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module bw_r_idct(rdtag_w0_y, rdtag_w1_y, rdtag_w2_y, rdtag_w3_y, so, rclk, se,
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si, reset_l, sehold, rst_tri_en, index0_x, index1_x, index_sel_x,
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si, reset_l, sehold, rst_tri_en, index0_x, index1_x, index_sel_x,
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dec_wrway_x, rdreq_x, wrreq_x, wrtag_w0_y, wrtag_w1_y, wrtag_w2_y,
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dec_wrway_x, rdreq_x, wrreq_x, wrtag_w0_y, wrtag_w1_y, wrtag_w2_y,
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wrtag_w3_y, adj);
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wrtag_w3_y, adj);
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Line 101... |
Line 101... |
end
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end
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bw_r_idct_array ictag_ary_00(
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bw_r_idct_array ictag_ary_00(
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.we (we[0]),
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.we (we[0]),
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.clk (clk),
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.clk (clk),
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.way (2'b00),
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.rd_data(rdtag_w0_y),
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.rd_data(rdtag_w0_y),
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.wr_data(wrtag_w0_y),
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.wr_data(wrtag_w0_y),
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.addr (index_y));
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.addr (index_y),
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.dec_wrway_y (dec_wrway_y));
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bw_r_idct_array ictag_ary_01(
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bw_r_idct_array ictag_ary_01(
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.we (we[1]),
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.we (we[1]),
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.clk (clk),
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.clk (clk),
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.way (2'b01),
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.rd_data(rdtag_w1_y),
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.rd_data(rdtag_w1_y),
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.wr_data(wrtag_w1_y),
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.wr_data(wrtag_w1_y),
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.addr (index_y));
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.addr (index_y),
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.dec_wrway_y (dec_wrway_y));
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bw_r_idct_array ictag_ary_10(
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bw_r_idct_array ictag_ary_10(
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.we (we[2]),
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.we (we[2]),
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.clk (clk),
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.clk (clk),
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.way(2'b10),
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.rd_data(rdtag_w2_y),
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.rd_data(rdtag_w2_y),
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.wr_data(wrtag_w2_y),
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.wr_data(wrtag_w2_y),
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.addr (index_y));
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.addr (index_y),
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.dec_wrway_y (dec_wrway_y));
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bw_r_idct_array ictag_ary_11(
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bw_r_idct_array ictag_ary_11(
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.we (we[3]),
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.we (we[3]),
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.clk (clk),
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.clk (clk),
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.way(2'b11),
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.rd_data(rdtag_w3_y),
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.rd_data(rdtag_w3_y),
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.wr_data(wrtag_w3_y),
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.wr_data(wrtag_w3_y),
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.addr (index_y));
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.addr (index_y),
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.dec_wrway_y (dec_wrway_y));
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endmodule
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endmodule
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module bw_r_idct_array(we, clk, rd_data, wr_data, addr);
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module bw_r_idct_array(we, clk, rd_data, wr_data, addr,dec_wrway_y,way);
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input we;
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input we;
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input clk;
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input clk;
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input [32:0] wr_data;
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input [32:0] wr_data;
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input [6:0] addr;
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input [6:0] addr;
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input [3:0] dec_wrway_y;
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input [1:0] way;
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output [32:0] rd_data;
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output [32:0] rd_data;
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reg [32:0] rd_data;
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reg [32:0] rd_data;
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reg [32:0] array[127:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [32:0] array[511:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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integer i;
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initial begin
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`ifdef DO_MEM_INIT
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// Add the memory init file in the database
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$readmemb("/import/dtg-data11/sandeep/niagara/design/sys/iop/srams/rtl/mem_init_idct.txt",array);
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`endif
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end
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always @(negedge clk) begin
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always @(negedge clk) begin
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if (we) array[addr] <= wr_data;
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if (we)
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else rd_data <= array[addr];
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begin
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array[addr] <= wr_data;
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end
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else
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rd_data <= array[addr];
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end
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end
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endmodule
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endmodule
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`else
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module bw_r_idct(/*AUTOARG*/
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// Outputs
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rdtag_w0_y, rdtag_w1_y, rdtag_w2_y, rdtag_w3_y, so,
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// Inputs
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rclk, se, si, reset_l, sehold, rst_tri_en, index0_x, index1_x,
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index_sel_x, dec_wrway_x, rdreq_x, wrreq_x, wrtag_w0_y,
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wrtag_w1_y, wrtag_w2_y, wrtag_w3_y, adj
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);
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input rclk,
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se,
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si,
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reset_l; // active LOW reset
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input sehold;
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input rst_tri_en;
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input [6:0] index0_x; // read/write address0
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input [6:0] index1_x; // read/write address1
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input index_sel_x; // selects between index1 and index0
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input [3:0] dec_wrway_x; // way -- functions as a write enable
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// per 33b
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input rdreq_x, // read enable
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wrreq_x; // write enable
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// Don't use rdreq and wrreq to gate off the clock, since these are
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// critical. A separate power down signal can be supplied if
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// needed.
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input [32:0] wrtag_w0_y; // write data, not flopped
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input [32:0] wrtag_w1_y; //
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input [32:0] wrtag_w2_y; //
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input [32:0] wrtag_w3_y; //
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input [3:0] adj;
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output [32:0] rdtag_w0_y; // read data split into 4 ports
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output [32:0] rdtag_w1_y; // not flopped
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output [32:0] rdtag_w2_y; //
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output [32:0] rdtag_w3_y; //
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output so;
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// Declarations
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// local signals
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`ifdef DEFINE_0IN
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`else
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reg [32:0] ictag_ary [511:0];
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reg [131:0] rdtag_bl_y,
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rdtag_sa_y;
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`endif
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wire clk;
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reg [6:0] index_y;
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reg rdreq_y,
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wrreq_y;
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reg [3:0] dec_wrway_y;
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wire [6:0] index_x;
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//----------------
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// Code start here
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//----------------
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assign clk = rclk;
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//-------------------------
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// 2:1 mux on address input
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//-------------------------
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// address inputs are critical and this mux needs to be merged with
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// the receiving flop.
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assign index_x = index_sel_x ? index1_x :
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index0_x;
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//------------------------
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// input flops from x to y
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//------------------------
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// these need to be scannable
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always @ (posedge clk)
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begin
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if (~sehold)
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begin
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rdreq_y <= rdreq_x;
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wrreq_y <= wrreq_x;
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index_y <= index_x;
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dec_wrway_y <= dec_wrway_x;
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end
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end
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`ifdef DEFINE_0IN
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wire [131:0] wm = { {33{(dec_wrway_y[3])}},{33{(dec_wrway_y[2])}},{33{(dec_wrway_y[1])}},{33{(dec_wrway_y[0])}} };
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wire we = wrreq_y & ~se;
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l1_tag l1_tag ( .nclk(~clk), .adr(index_y[6:0]), .we(we), .wm(wm),
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.din ({wrtag_w3_y,wrtag_w2_y,wrtag_w1_y,wrtag_w0_y}),
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.dout({rdtag_w3_y,rdtag_w2_y,rdtag_w1_y,rdtag_w0_y}) );
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`else
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//----------------------------------------------------------------------
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// Read Operation
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//----------------------------------------------------------------------
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always @(/*AUTOSENSE*/ /*memory or*/ index_y or rdreq_y or reset_l
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or wrreq_y)
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begin
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if (rdreq_y & reset_l)
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begin
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if (wrreq_y) // rd_wr conflict
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begin
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rdtag_bl_y = {132{1'bx}};
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end
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else // no write, read only
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begin
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rdtag_bl_y[32:0] = ictag_ary[{index_y,2'b00}]; // way0
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rdtag_bl_y[65:33] = ictag_ary[{index_y,2'b01}]; // way1
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rdtag_bl_y[98:66] = ictag_ary[{index_y,2'b10}]; // way2
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rdtag_bl_y[131:99] = ictag_ary[{index_y,2'b11}];// way3
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end
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end
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else // no read
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begin
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rdtag_bl_y = {132{1'bx}};
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end
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end // always @ (...
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// SA latch -- to make 0in happy
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always @ (/*AUTOSENSE*/clk or rdreq_y or rdtag_bl_y or reset_l)
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begin
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if (rdreq_y & ~clk & reset_l)
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begin
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rdtag_sa_y <= rdtag_bl_y;
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end
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end
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// Output is held the same if there is no read. This is not a
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// hard requirement, please let me know if the output has to
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// be something else for ease of implementation.
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// Output behavior during reset is currently not coded.
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// Functionally there is no preference, though it should be
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// unchanging to keep the power low.
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// Final Output
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assign rdtag_w0_y = rdtag_sa_y[32:0];
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assign rdtag_w1_y = rdtag_sa_y[65:33];
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assign rdtag_w2_y = rdtag_sa_y[98:66];
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assign rdtag_w3_y = rdtag_sa_y[131:99];
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//----------------------------------------------------------------------
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// Write Operation
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//----------------------------------------------------------------------
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// Writes should be blocked off during scan shift.
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always @ (negedge clk)
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begin
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if (wrreq_y & reset_l & ~rst_tri_en)
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begin
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if (dec_wrway_y[0])
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ictag_ary[{index_y, 2'b00}] = wrtag_w0_y;
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if (dec_wrway_y[1])
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ictag_ary[{index_y, 2'b01}] = wrtag_w1_y;
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if (dec_wrway_y[2])
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ictag_ary[{index_y, 2'b10}] = wrtag_w2_y;
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if (dec_wrway_y[3])
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ictag_ary[{index_y, 2'b11}] = wrtag_w3_y;
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end
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end
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// TBD: Need to model rd-wr contention
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`endif
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//******************************************************
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// The stuff below is not part of the main functionality
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// and has no representation in the actual circuit.
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//******************************************************
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// synopsys translate_off
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//-----------------------
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// Contention Monitor
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//-----------------------
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`ifdef INNO_MUXEX
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`else
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always @ (negedge clk)
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begin
|
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if (rdreq_y & wrreq_y & reset_l)
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begin
|
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// 0in <fire -message "FATAL ERROR: rd and wr contention in idct"
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//$error("IDtag Contention", "ERROR rd and wr contention in idct");
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end
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end // always @ (negedge clk)
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`endif
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//--------------------------------
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// // For dump_cache.v
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// //--------------------------------
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// //fake to make dump_cache.v happy
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// reg [29:0] w0 [127:0];
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// reg [29:0] w1 [127:0];
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// reg [29:0] w2 [127:0];
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// reg [29:0] w3 [127:0];
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//
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// always @ (negedge clk)
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// begin
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// if (wrreq_y & ~se)
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// begin
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// if (rdreq_y) begin // rd/wr contention
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// case (dec_wrway_y)
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// 4'b0001 : w0[index_y[6:0]] ={30{1'bx}};
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// 4'b0010 : w1[index_y[6:0]] ={30{1'bx}};
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// 4'b0100 : w2[index_y[6:0]] ={30{1'bx}};
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// 4'b1000 : w3[index_y[6:0]] ={30{1'bx}};
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// endcase // case(wrway_y)
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// end
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// else begin
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// case (dec_wrway_y)
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// 4'b0001 : w0[index_y[6:0]] = wrtag_w0_y[29:0];
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// 4'b0010 : w1[index_y[6:0]] = wrtag_w1_y[29:0];
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// 4'b0100 : w2[index_y[6:0]] = wrtag_w2_y[29:0];
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// 4'b1000 : w3[index_y[6:0]] = wrtag_w3_y[29:0];
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// endcase // case(wrway_y)
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// end
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// end
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// end
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// synopsys translate_on
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endmodule // bw_r_idct
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`endif
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No newline at end of file
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No newline at end of file
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