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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [bw_r_irf_register.v] - Diff between revs 105 and 113

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Rev 105 Rev 113
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// You should have received a copy of the GNU General Public
 
// You should have received a copy of the GNU General Public
 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
 
 
`ifdef FPGA_SYN_1THREAD
 
 
 
 
 
 
 
`ifdef FPGA_SYN_SAVE_BRAM
 
 
 
 
 
 
 
 
 
 
 
module bw_r_irf_register(clk, wren, save, save_addr, restore, restore_addr, wr_data, rd_data);
 
 
 
        input           clk;
 
 
 
        input           wren;
 
 
 
        input           save;
 
 
 
        input   [2:0]    save_addr;
 
 
 
        input           restore;
 
 
 
        input   [2:0]    restore_addr;
 
 
 
        input   [71:0]   wr_data;
 
 
 
        output  [71:0]   rd_data;
 
 
 
`ifdef FPGA_SYN_ALTERA
 
 
 
    reg [35:0]   window[15:0]/* synthesis syn_ramstyle = block_ram*/; //  syn_ramstyle = no_rw_check */;
 
 
 
`else
 
 
 
    reg [35:0]   window[15:0]/* synthesis syn_ramstyle = block_ram  syn_ramstyle = no_rw_check */;
 
 
 
`endif
 
 
 
reg     [71:0]   onereg;
 
 
 
 
 
 
 
  initial onereg = 72'h0;
 
 
 
 
 
 
 
  assign rd_data = onereg;
 
 
 
 
 
 
 
  reg [71:0] restore_data;
 
 
 
  wire [71:0] wrdata = restore ? restore_data : wr_data;
 
 
 
 
 
 
 
  wire wr_en = wren | restore;
 
 
 
 
 
 
 
  always @(posedge clk) begin
 
 
 
    if(wr_en) onereg <= wrdata;
 
 
 
  end
 
 
 
 
 
 
 
  wire [2:0] addr = save ? save_addr : restore_addr;
 
 
 
 
 
 
 
  wire [3:0] addr1 = {1'b1, addr};
 
 
 
  wire [3:0] addr0 = {1'b0, addr};
 
 
 
 
 
 
 
  always @(negedge clk) begin
 
 
 
    if(save) window[addr1] <= wren ? wr_data[71:36] : rd_data[71:36];
 
 
 
    else restore_data[71:36] <= window[addr1];
 
 
 
  end
 
 
 
 
 
 
 
  always @(negedge clk) begin
 
 
 
    if(save) window[addr0] <= wren ? wr_data[35:0] : rd_data[35:0];
 
 
 
    else restore_data[35:0] <= window[addr0];
 
 
 
  end
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
`else
 
 
 
 
 
 
 
 
 
 
 
module bw_r_irf_register(clk, wren, save, save_addr, restore, restore_addr, wr_data, rd_data);
 
 
 
        input           clk;
 
 
 
        input           wren;
 
 
 
        input           save;
 
 
 
        input   [2:0]    save_addr;
 
 
 
        input           restore;
 
 
 
        input   [2:0]    restore_addr;
 
 
 
        input   [71:0]   wr_data;
 
 
 
        output  [71:0]   rd_data;
 
 
 
`ifdef FPGA_SYN_ALTERA
 
 
 
    reg [71:0]   window[7:0]/* synthesis syn_ramstyle = block_ram*/; //  syn_ramstyle = no_rw_check */;
 
 
 
`else
 
 
 
reg     [71:0]   window[7:0]/* synthesis syn_ramstyle = block_ram  syn_ramstyle = no_rw_check */;
 
 
 
`endif
 
 
 
reg     [71:0]   onereg;
 
 
 
 
 
 
 
reg     [2:0]    rd_addr;
 
 
 
reg     [2:0]    wr_addr;
 
 
 
reg             save_d;
 
 
 
`ifdef FPGA_SYN_ALTERA
 
 
 
    integer k;
 
 
 
 
 
 
 
    initial
 
 
 
    begin
 
 
 
        for (k = 0; k < 8 ; k = k + 1)
 
 
 
        begin
 
 
 
            window[k] = 72'h0;
 
 
 
        end
 
 
 
    end
 
 
 
`endif
 
 
 
 
 
 
 
  initial
 
 
 
      begin
 
 
 
          onereg = 72'b0;
 
 
 
          wr_addr = 3'h0;
 
 
 
          rd_addr = 3'h0;
 
 
 
      end
 
 
 
 
 
 
 
  always @(negedge clk) begin
 
 
 
    rd_addr = restore_addr;
 
 
 
  end
 
 
 
 
 
 
 
  always @(posedge clk) begin
 
 
 
    wr_addr <= save_addr;
 
 
 
  end
 
 
 
  always @(posedge clk) begin
 
 
 
    save_d <= save;
 
 
 
  end
 
 
 
 
 
 
 
  assign rd_data = onereg;
 
 
 
 
 
 
 
  wire [71:0] restore_data = window[rd_addr];
 
 
 
  wire [71:0] wrdata = restore ? restore_data : wr_data;
 
 
 
 
 
 
 
  wire wr_en = wren | (restore & (wr_addr != rd_addr));
 
 
 
 
 
 
 
  always @(posedge clk) begin
 
 
 
    if(wr_en) onereg <= wrdata;
 
 
 
  end
 
 
 
 
 
 
 
  always @(negedge clk) begin
 
 
 
    if(save_d) window[wr_addr] <= rd_data;
 
 
 
  end
 
 
 
 
 
 
 
endmodule
 
 
 
 
 
 
 
`endif
 
 
 
 
 
 
 
`else
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
module bw_r_irf_register(clk, wrens, save, save_addr, restore, restore_addr, wr_data0, wr_data1, wr_data2, wr_data3, rd_thread, rd_data);
 
module bw_r_irf_register(clk, wrens, save, save_addr, restore, restore_addr, wr_data0, wr_data1, wr_data2, wr_data3, rd_thread, rd_data);
 
        input           clk;
 
        input           clk;
 
        input   [3:0]    wrens;
 
        input   [3:0]    wrens;
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        input   [71:0]   wr_data1;
 
        input   [71:0]   wr_data1;
 
        input   [71:0]   wr_data2;
 
        input   [71:0]   wr_data2;
 
        input   [71:0]   wr_data3;
 
        input   [71:0]   wr_data3;
 
        input   [1:0]    rd_thread;
 
        input   [1:0]    rd_thread;
 
        output  [71:0]   rd_data;
 
        output  [71:0]   rd_data;
 
 
 
`ifdef FPGA_SYN_ALTERA
 
 
 
    reg [71:0]   window[31:0]/* synthesis syn_ramstyle = block_ram*/; //  syn_ramstyle = no_rw_check */;
 
 
 
`else
 
reg     [71:0]   window[31:0]/* synthesis syn_ramstyle = block_ram  syn_ramstyle = no_rw_check */;
 
reg     [71:0]   window[31:0]/* synthesis syn_ramstyle = block_ram  syn_ramstyle = no_rw_check */;
 
 
 
`endif
 
reg     [71:0]   reg_th0, reg_th1, reg_th2, reg_th3;
 
reg     [71:0]   reg_th0, reg_th1, reg_th2, reg_th3;
 
 
 
 
 
reg     [4:0]    rd_addr;
 
reg     [4:0]    rd_addr;
 
reg     [4:0]    wr_addr;
 
reg     [4:0]    wr_addr;
 
reg             save_d;
 
reg             save_d;
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                  1'b1: y = x1;
 
                  1'b1: y = x1;
 
                endcase
 
                endcase
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
`endif
 
 
 
 
 
 
 
 
 
 
 
 
 
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