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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_32x152
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`endif
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`ifdef FPGA_SYN_32x152
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module bw_r_rf32x152b(dout, so, rd_en, rd_adr, wr_en, wr_adr, din, si, se,
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module bw_r_rf32x152b(dout, so, rd_en, rd_adr, wr_en, wr_adr, din, si, se,
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sehold, rclk, rst_tri_en, reset_l);
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sehold, rclk, rst_tri_en, reset_l);
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Line 79... |
end
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end
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end
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end
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endmodule
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endmodule
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`else
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module bw_r_rf32x152b (/*AUTOARG*/
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// Outputs
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dout, so,
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// Inputs
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rd_en, rd_adr, wr_en, wr_adr, din,
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si, se, sehold, rclk, rst_tri_en, reset_l);
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parameter NUMENTRIES = 32 ; // number of entries in dfq
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input [4:0] rd_adr; // read adr.
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input rd_en; // read pointer
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input wr_en; // write pointer vld
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input [4:0] wr_adr; // write adr.
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input [151:0] din; // wr data
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input rclk; // clock
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input reset_l; // active low reset
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input rst_tri_en; // reset and scan
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input sehold; // scan hold
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input si; // scan in
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input se; // scan enable
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output [151:0] dout ; // data read out
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output so ; // scan out
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wire [151:0] dout;
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wire clk;
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wire wr_vld;
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reg [151:0] dfq_mem [NUMENTRIES-1:0];
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reg [151:0] local_dout;
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// reg so;
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integer i,j;
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//
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// added for atpg support
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wire [4:0] sehold_rd_adr; // output of sehold mux - read adr.
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wire sehold_rd_en; // output of sehold mux - read pointer
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wire sehold_wr_en; // output of sehold mux - write pointer vld
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wire [4:0] sehold_wr_adr; // output of sehold mux - write adr.
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wire [151:0] sehold_din; // wr data
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wire [4:0] rd_adr_d1; // flopped read adr.
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wire rd_en_d1; // flopped read pointer
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wire wr_en_d1; // flopped write pointer vld
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wire [4:0] wr_adr_d1; // flopped write adr.
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wire [151:0] din_d1; // flopped wr data
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//
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// creating local clock
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assign clk=rclk;
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//
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//=========================================================================================
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// support for atpg pattern generation
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//=========================================================================================
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//
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// read controls
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dp_mux2es #(6) mux_sehold_rd_ctrl (
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.in0 ({rd_adr[4:0], rd_en}),
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.in1 ({rd_adr_d1[4:0], rd_en_d1}),
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.sel (sehold),
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.dout ({sehold_rd_adr[4:0],sehold_rd_en})
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);
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dff_s #(6) dff_rd_ctrl_d1(
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.din ({sehold_rd_adr[4:0], sehold_rd_en}),
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.q ({rd_adr_d1[4:0], rd_en_d1}),
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.clk (clk),
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.se (se),
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.si (),
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.so ()
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);
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//
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// write controls
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dp_mux2es #(6) mux_sehold_wr_ctrl (
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.in0 ({wr_adr[4:0], wr_en}),
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.in1 ({wr_adr_d1[4:0], wr_en_d1}),
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.sel (sehold),
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.dout ({sehold_wr_adr[4:0],sehold_wr_en})
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);
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dff_s #(6) dff_wr_ctrl_d1(
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.din ({sehold_wr_adr[4:0], sehold_wr_en}),
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.q ({wr_adr_d1[4:0], wr_en_d1}),
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.clk (clk),
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.se (se),
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.si (),
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.so ()
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);
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//
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// write data
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dp_mux2es #(152) mux_sehold_din (
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.in0 (din[151:0]),
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.in1 (din_d1[151:0]),
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.sel (sehold),
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.dout (sehold_din[151:0])
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);
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dff_s #(152) dff_din_d1(
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.din (sehold_din[151:0]),
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.q (din_d1[151:0]),
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.clk (clk),
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.se (se),
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.si (),
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.so ()
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);
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//
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// diable write to register file during reset or scan
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assign wr_vld = sehold_wr_en & ~rst_tri_en & reset_l;
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// always @ (posedge clk)
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// begin
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// so <= 1'bx;
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// end
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//=========================================================================================
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// generate wordlines
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//=========================================================================================
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// Word-Line Generation skipped. Implicit in read and write.
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//=========================================================================================
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// write or read to/from memory
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//=========================================================================================
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always @ ( posedge clk )
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begin
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if (wr_vld)
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dfq_mem[sehold_wr_adr] = sehold_din[151:0] ;
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end
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always @ ( posedge clk )
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begin
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if (sehold_rd_en)
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begin
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if (wr_vld & (sehold_wr_adr[4:0] == sehold_rd_adr[4:0]) )
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local_dout[151:0] <= 152'hx;
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else
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for (j=0;j<NUMENTRIES;j=j+1)
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begin
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if (sehold_rd_adr[4:0] == j)
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local_dout[151:0] <= dfq_mem[j] ;
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end
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end
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end
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always @ ( ~reset_l )
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begin
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local_dout[151:0] <=
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152'hxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ;
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end
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assign dout[151:0] = local_dout[151:0];
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// Error Checking : Termination Conditions
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always @ (posedge clk)
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begin
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if ((rd_en == 1'bx) | // wr is undefined, thus terminate
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(sehold_rd_en & (sehold_rd_adr[4:0] == 5'hxx)) & reset_l) // check outside reset.
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if (sehold_rd_adr[4:0] == 5'hxx)
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begin
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`ifdef INNO_MUXEX
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`else
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`ifdef DEFINE_0IN
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// 0in <fire -message "rf32x152b_error, read pointer error (X)"
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$display("rf32x152b_error"," read pointer error (X) %h ", rd_adr[4:0]);
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`else
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`ifdef MODELSIM
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$display("rf32x152b_error"," read pointer error (X) %h ", rd_adr[4:0]);
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`else
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$error("rf32x152b_error"," read pointer error (X) %h ", rd_adr[4:0]);
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`endif
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`endif
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`endif
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end
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if ((wr_vld == 1'bx) | // wr is undefined, thus terminate
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(wr_vld & (sehold_wr_adr[4:0] == 5'hxx)) & reset_l) // check outside reset.
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begin
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`ifdef INNO_MUXEX
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`else
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`ifdef DEFINE_0IN
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// 0in <fire -message "rf32x152b_error, write error (X)"
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$display("rf32x152b_error"," write error (X) %h ", wr_adr[4:0]);
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`else
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`ifdef MODELSIM
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$display("rf32x152b_error"," write error (X) %h ", wr_adr[4:0]);
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`else
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$error("rf32x152b_error"," write error (X) %h ", wr_adr[4:0]);
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`endif
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`endif
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`endif
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end
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end
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endmodule
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`endif
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No newline at end of file
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No newline at end of file
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