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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [lsu_dcdp.v] - Diff between revs 105 and 113

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Line 16... Line 16... 
// You should have received a copy of the GNU General Public
 
// You should have received a copy of the GNU General Public
 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
`define SIMPLY_RISC_SCANIN .si(0)
 
 
 
`else
 
 
 
`define SIMPLY_RISC_SCANIN .si()
 
 
 
`endif
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
/*
 
/*
 
//      Description:    LSU Data Cache Data Path
 
//      Description:    LSU Data Cache Data Path
 
//                      - Final Way-Select Mux.
 
//                      - Final Way-Select Mux.
 
//                      - Alignment, Sign-Extension, Endianness.
 
//                      - Alignment, Sign-Extension, Endianness.
 
*/
 
*/
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Global header file includes
 
// Global header file includes
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// system level definition file which contains the /*
 
`include        "sys.h" // system level definition file which contains the 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: sys.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
// -*- verilog -*-
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
// Description:         Global header file that contain definitions that
 
 
 
//                      are common/shared at the systme level
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
//
 
 
 
// Setting the time scale
 
 
 
// If the timescale changes, JP_TIMESCALE may also have to change.
 
 
 
`timescale      1ps/1ps
 
 
 
 
 
 
 
//
 
 
 
// JBUS clock
 
 
 
// =========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Defines
 
 
 
// ==================
 
 
 
 
 
 
 
// Reliable Link
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Objects
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Reliable Link
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Congestion
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Acknowledge
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Request
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Message
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Acknowledge Types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Request Types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Frame
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Packet Type
 
 
 
// ===============
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Data Packet Format
 
 
 
// ======================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Size encoding for the UCB_SIZE_HI/LO field
 
 
 
// 000 - byte
 
 
 
// 001 - half-word
 
 
 
// 010 - word
 
 
 
// 011 - double-word
 
 
 
// 111 - quad-word
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Interrupt Packet Format
 
 
 
// ===========================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define UCB_THR_HI             9      // (6) cpu/thread ID shared with
 
 
 
//`define UCB_THR_LO             4             data packet format
 
 
 
//`define UCB_PKT_HI             3      // (4) packet type shared with
 
 
 
//`define UCB_PKT_LO             0      //     data packet format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// FCRAM Bus Widths
 
 
 
// ================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// ENET clock periods
 
 
 
// ==================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBus Bridge defines
 
 
 
// =================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PCI Device Address Configuration
 
 
 
// ================================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                                        // time scale definition
 
                                        // time scale definition
 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Local header file includes / local defines
 
// Local header file includes / local defines
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
Line 854... Line 582... 
assign ld_data_msb_w0_m[7:0] = dcache_rdata_msb_w0_m[7:0];
 
assign ld_data_msb_w0_m[7:0] = dcache_rdata_msb_w0_m[7:0];
 
assign ld_data_msb_w1_m[7:0] = dcache_rdata_msb_w1_m[7:0];
 
assign ld_data_msb_w1_m[7:0] = dcache_rdata_msb_w1_m[7:0];
 
assign ld_data_msb_w2_m[7:0] = dcache_rdata_msb_w2_m[7:0];
 
assign ld_data_msb_w2_m[7:0] = dcache_rdata_msb_w2_m[7:0];
 
assign ld_data_msb_w3_m[7:0] = dcache_rdata_msb_w3_m[7:0];
 
assign ld_data_msb_w3_m[7:0] = dcache_rdata_msb_w3_m[7:0];
 
 
 
 
 
dff #(32) ld_data_msb_stgg (
 
dff_s #(32) ld_data_msb_stgg (
 
        .din    ({ld_data_msb_w0_m[7:0], ld_data_msb_w1_m[7:0], ld_data_msb_w2_m[7:0], ld_data_msb_w3_m[7:0]}),
 
        .din    ({ld_data_msb_w0_m[7:0], ld_data_msb_w1_m[7:0], ld_data_msb_w2_m[7:0], ld_data_msb_w3_m[7:0]}),
 
        .q      ({ld_data_msb_w0_g[7:0], ld_data_msb_w1_g[7:0], ld_data_msb_w2_g[7:0], ld_data_msb_w3_g[7:0]}),
 
        .q      ({ld_data_msb_w0_g[7:0], ld_data_msb_w1_g[7:0], ld_data_msb_w2_g[7:0], ld_data_msb_w3_g[7:0]}),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
   wire [3:0] dcache_alt_rsel_way_m;
 
   wire [3:0] dcache_alt_rsel_way_m;
 
   wire       dcache_alt_mx_sel_m;
 
   wire       dcache_alt_mx_sel_m;
 
 
 
 
 
dff #(5) dcache_alt_stgm  (
 
dff_s #(5) dcache_alt_stgm  (
 
        .din    ({lsu_bist_rsel_way_e[3:0],  dcache_alt_mx_sel_e}),
 
        .din    ({lsu_bist_rsel_way_e[3:0],  dcache_alt_mx_sel_e}),
 
        .q      ({dcache_alt_rsel_way_m[3:0], dcache_alt_mx_sel_m}),
 
        .q      ({dcache_alt_rsel_way_m[3:0], dcache_alt_mx_sel_m}),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
   wire [3:0] dcache_alt_rsel_way_g;
 
   wire [3:0] dcache_alt_rsel_way_g;
 
   wire       dcache_alt_mx_sel_g;
 
   wire       dcache_alt_mx_sel_g;
 
 
 
 
 
dff #(5) dcache_alt_stgg  (
 
dff_s #(5) dcache_alt_stgg  (
 
        .din    ({dcache_alt_rsel_way_m[3:0],  dcache_alt_mx_sel_m}),
 
        .din    ({dcache_alt_rsel_way_m[3:0],  dcache_alt_mx_sel_m}),
 
        .q      ({dcache_alt_rsel_way_g[3:0],  dcache_alt_mx_sel_g}),
 
        .q      ({dcache_alt_rsel_way_g[3:0],  dcache_alt_mx_sel_g}),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
   wire [3:0] cache_way_mx_sel;
 
   wire [3:0] cache_way_mx_sel;
 
 
 
 
 
   assign     cache_way_mx_sel [3:0] = dcache_alt_mx_sel_g ? dcache_alt_rsel_way_g[3:0] : cache_way_hit_buf2[3:0];
 
   assign     cache_way_mx_sel [3:0] = dcache_alt_mx_sel_g ? dcache_alt_rsel_way_g[3:0] : cache_way_hit_buf2[3:0];
 
 
 
 
Line 902... Line 630... 
 
 
 
 
   wire       signed_ldst_byte_g;
 
   wire       signed_ldst_byte_g;
 
   wire       signed_ldst_hw_g;
 
   wire       signed_ldst_hw_g;
 
   wire       signed_ldst_w_g;
 
   wire       signed_ldst_w_g;
 
 
 
 
 
dff #(3) ldst_size_stgg(
 
dff_s #(3) ldst_size_stgg(
 
 .din    ({signed_ldst_byte_m, signed_ldst_hw_m, signed_ldst_w_m}),
 
 .din    ({signed_ldst_byte_m, signed_ldst_hw_m, signed_ldst_w_m}),
 
 .q      ({signed_ldst_byte_g, signed_ldst_hw_g, signed_ldst_w_g}),
 
 .q      ({signed_ldst_byte_g, signed_ldst_hw_g, signed_ldst_w_g}),
 
 .clk    (clk),
 
 .clk    (clk),
 
 .se     (se),       .si (),          .so ()
 
 .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
);
 
);
 
 
 
 
 
wire [7:0] morphed_addr_g;
 
wire [7:0] morphed_addr_g;
 
 
 
 
 
dff #(8) stgg_morphadd(
 
dff_s #(8) stgg_morphadd(
 
        .din    (morphed_addr_m[7:0]),
 
        .din    (morphed_addr_m[7:0]),
 
        .q      (morphed_addr_g[7:0]),
 
        .q      (morphed_addr_g[7:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
   wire       sign_bit_w0_g, sign_bit_w1_g, sign_bit_w2_g, sign_bit_w3_g;
 
   wire       sign_bit_w0_g, sign_bit_w1_g, sign_bit_w2_g, sign_bit_w3_g;
 
 
 
 
 
assign  sign_bit_w0_g =
 
assign  sign_bit_w0_g =
Line 975... Line 703... 
 
 
 
 
//dff #(4) ssign_bit_stgg (
 
//dff #(4) ssign_bit_stgg (
 
//        .din    ({sign_bit_w0_m, sign_bit_w1_m, sign_bit_w2_m, sign_bit_w3_m}),
 
//        .din    ({sign_bit_w0_m, sign_bit_w1_m, sign_bit_w2_m, sign_bit_w3_m}),
 
//        .q      ({sign_bit_w0_g, sign_bit_w1_g, sign_bit_w2_g, sign_bit_w3_g}),
 
//        .q      ({sign_bit_w0_g, sign_bit_w1_g, sign_bit_w2_g, sign_bit_w3_g}),
 
//        .clk    (clk),
 
//        .clk    (clk),
 
//        .se     (se),       .si (),          .so ()
 
//        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
//        );
 
//        );
 
 
 
 
 
// byte0 never requires sign or zero extension.
 
// byte0 never requires sign or zero extension.
 
//w0
 
//w0
 
//   wire [3:1] lsu_byp_byte_zero_extend_w0;
 
//   wire [3:1] lsu_byp_byte_zero_extend_w0;
Line 1170... Line 898... 
   (cache_way_mx_sel[2] ?  lsu_byp_byte_sign_extend_w2[7:1] : 7'b0) |
 
   (cache_way_mx_sel[2] ?  lsu_byp_byte_sign_extend_w2[7:1] : 7'b0) |
 
   (cache_way_mx_sel[3] ?  lsu_byp_byte_sign_extend_w3[7:1] : 7'b0) ;
 
   (cache_way_mx_sel[3] ?  lsu_byp_byte_sign_extend_w3[7:1] : 7'b0) ;
 
 
 
 
 
 
 
 
 
 
 
 
 
dff #(37) stgg_mergesel(
 
dff_s #(37) stgg_mergesel(
 
        .din    ({
 
        .din    ({
 
         merge7_sel_byte0_m, merge7_sel_byte7_m,
 
         merge7_sel_byte0_m, merge7_sel_byte7_m,
 
         merge6_sel_byte1_m, merge6_sel_byte6_m,
 
         merge6_sel_byte1_m, merge6_sel_byte6_m,
 
         merge5_sel_byte2_m, merge5_sel_byte5_m,
 
         merge5_sel_byte2_m, merge5_sel_byte5_m,
 
         merge4_sel_byte3_m, merge4_sel_byte4_m,
 
         merge4_sel_byte3_m, merge4_sel_byte4_m,
Line 1210... Line 938... 
         merge1_sel_byte4, merge1_sel_byte5,
 
         merge1_sel_byte4, merge1_sel_byte5,
 
         merge1_sel_byte6, merge1_sel_byte7,
 
         merge1_sel_byte6, merge1_sel_byte7,
 
         merge0_sel_byte_1h,merge1_sel_byte_1h, merge1_sel_byte_2h
 
         merge0_sel_byte_1h,merge1_sel_byte_1h, merge1_sel_byte_2h
 
                }),
 
                }),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
 
 
 
 
assign  lsu_exu_dfill_data_w2[63:0] = align_byte[63:0] ;
 
assign  lsu_exu_dfill_data_w2[63:0] = align_byte[63:0] ;
 
assign  lsu_ffu_ld_data[63:0] = align_byte[63:0] ;
 
assign  lsu_ffu_ld_data[63:0] = align_byte[63:0] ;

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