Subversion Repositories s1_core

// You should have received a copy of the GNU General Public

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// 

// ========== Copyright Header End ============================================

// ========== Copyright Header End ============================================

/////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////

/*

/*

//  Description:  LSU Data Cache Control and Minor Datapath

//  Description:  LSU Data Cache Control and Minor Datapath

//      - Tag Comparison - hit/miss.

//      - Tag Comparison - hit/miss.

*/

*/

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

// Global header file includes

// Global header file includes

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

          // time scale definition

          // time scale definition

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

// Local header file includes / local defines

// Local header file includes / local defines

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

module lsu_dctl ( /*AUTOARG*/

module lsu_dctl ( /*AUTOARG*/

   // Outputs

   // Outputs

   lsu_tlu_nucleus_ctxt_m, lsu_quad_word_access_g, so, dctl_rst_l,

   lsu_tlu_nucleus_ctxt_m, lsu_quad_word_access_g, so, dctl_rst_l,

   lsu_tlu_wsr_inst_e, lsu_l2fill_fpld_e, dva_vld_m_bf,

   lsu_tlu_wsr_inst_e, lsu_l2fill_fpld_e, dva_vld_m_bf,

output      lsu_ld_miss_wb ;  // load misses in d$.

output      lsu_ld_miss_wb ;  // load misses in d$.

//output      lsu_ld_hit_wb ;   // load hits in d$.

//output      lsu_ld_hit_wb ;   // load hits in d$.

output      lsu_dtlb_bypass_e ; // dtlb is bypassed

output      lsu_dtlb_bypass_e ; // dtlb is bypassed

output      tlb_ldst_cam_vld ;

output      tlb_ldst_cam_vld ;

//output      stxa_internal ;   // internal stxa, stg g 

//output      stxa_internal ;   // internal stxa, stg g 

output      ldxa_internal ;   // internal ldxa, stg g

output      ldxa_internal ;   // internal ldxa, stg g

wire  [3:0]  pend_atm_ld_ue ;

wire  [3:0]  pend_atm_ld_ue ;

wire [2:0]   lsu_byp_misc_addr_m ;   // lower 3bits of addr for ldxa/raw etc

wire [2:0]   lsu_byp_misc_addr_m ;   // lower 3bits of addr for ldxa/raw etc

wire [1:0]   lsu_byp_misc_sz_m ;     // size for ldxa/raw etc

wire [1:0]   lsu_byp_misc_sz_m ;     // size for ldxa/raw etc

//==========================================================

//==========================================================

//RESET, CLK

//RESET, CLK

//==========================================================     

//==========================================================     

   wire       reset;

   wire       reset;

   wire       dbb_reset_l;

   wire       dbb_reset_l;

   wire       clk;

   wire       clk;

    dffrl_async rstff(.din (grst_l),

    dffrl_async rstff(.din (grst_l),

                        .q   (dbb_reset_l),

                        .q   (dbb_reset_l),

                        .rst_l (arst_l));

                        .rst_l (arst_l));

   assign  reset  =  ~dbb_reset_l;

   assign  reset  =  ~dbb_reset_l;

   assign dctl_rst_l = dbb_reset_l;

   assign dctl_rst_l = dbb_reset_l;

   assign clk = rclk;

   assign clk = rclk;

wire      lsu_bist_wvld_e ;           // bist writes to cache

wire      lsu_bist_wvld_e ;           // bist writes to cache

wire            lsu_bist_rvld_e ;                 // bist reads dcache

wire            lsu_bist_rvld_e ;                 // bist reads dcache

   .din ({mbist_dcache_write, mbist_dcache_read}),

   .din ({mbist_dcache_write, mbist_dcache_read}),

   .q   ({lsu_bist_wvld_e,    lsu_bist_rvld_e  }),

   .q   ({lsu_bist_wvld_e,    lsu_bist_rvld_e  }),

   .clk (clk),

   .clk (clk),

);

);

//===========================================================

//===========================================================

//from lsu_excpctl

//from lsu_excpctl

//wire          lsu_flush_pipe_w ;      // flush - local to lsu

//wire          lsu_flush_pipe_w ;      // flush - local to lsu

//wire    lsu_l2fill_bendian_g;

//wire    lsu_l2fill_bendian_g;

wire memref_e;

wire memref_e;

  .din (ifu_lsu_memref_d),

  .din (ifu_lsu_memref_d),

  .q   (memref_e),

  .q   (memref_e),

  .clk (clk),

  .clk (clk),

);

);

//=================================================================================================

//=================================================================================================

// SHADOW SCAN

// SHADOW SCAN

//=================================================================================================

//=================================================================================================

                ctu_sscan_tid[1] & (tlb_ld_inst1 | tlb_st_inst1) |

                ctu_sscan_tid[1] & (tlb_ld_inst1 | tlb_st_inst1) |

                        ctu_sscan_tid[2] & (tlb_ld_inst2 | tlb_st_inst2) |

                        ctu_sscan_tid[2] & (tlb_ld_inst2 | tlb_st_inst2) |

                ctu_sscan_tid[3] & (tlb_ld_inst3 | tlb_st_inst3) ;

                ctu_sscan_tid[3] & (tlb_ld_inst3 | tlb_st_inst3) ;

  .din ({sscan_data_14,sscan_data_13}),

  .din ({sscan_data_14,sscan_data_13}),

  .q   (lsu_sscan_data[14:13]),

  .q   (lsu_sscan_data[14:13]),

  .clk (clk),

  .clk (clk),

);

);

//=========================================================================================

//=========================================================================================

//  INST_VLD_W GENERATION

//  INST_VLD_W GENERATION

//=========================================================================================

//=========================================================================================

wire    lsu_inst_vld_w ;

wire    lsu_inst_vld_w ;

assign  flush_w_inst_vld_m =

assign  flush_w_inst_vld_m =

        ifu_tlu_inst_vld_m &

        ifu_tlu_inst_vld_m &

        ~(dctl_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w

        ~(dctl_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w

        .din    (flush_w_inst_vld_m),

        .din    (flush_w_inst_vld_m),

        .q      (lsu_inst_vld_w),

        .q      (lsu_inst_vld_w),

        .clk    (clk),

        .clk    (clk),

        );

        );

// Specifically for qctl2. Does not include flush-pipe, but does include ifu's flush.

// Specifically for qctl2. Does not include flush-pipe, but does include ifu's flush.

wire    ld_vld ;

wire    ld_vld ;

   wire ifu_lsu_flush_w;

   wire ifu_lsu_flush_w;

   wire ifu_tlu_flush_fd_w_q, ifu_tlu_flush_fd2_w_q, ifu_tlu_flush_fd3_w_q;

   wire ifu_tlu_flush_fd_w_q, ifu_tlu_flush_fd2_w_q, ifu_tlu_flush_fd3_w_q;

        .din    ({ifu_tlu_flush_m,ifu_tlu_flush_m,     ifu_tlu_flush_m,      ifu_tlu_flush_m}     ),

        .din    ({ifu_tlu_flush_m,ifu_tlu_flush_m,     ifu_tlu_flush_m,      ifu_tlu_flush_m}     ),

        .q      ({ifu_lsu_flush_w,ifu_tlu_flush_fd_w_q,ifu_tlu_flush_fd2_w_q,ifu_tlu_flush_fd3_w_q}),

        .q      ({ifu_lsu_flush_w,ifu_tlu_flush_fd_w_q,ifu_tlu_flush_fd2_w_q,ifu_tlu_flush_fd3_w_q}),

        .clk    (clk),

        .clk    (clk),

        );

        );

bw_u1_buf_30x UZfix_ifu_tlu_flush_fd_w  ( .a(ifu_tlu_flush_fd_w_q),  .z(ifu_tlu_flush_fd_w)  );

bw_u1_buf_30x UZfix_ifu_tlu_flush_fd_w  ( .a(ifu_tlu_flush_fd_w_q),  .z(ifu_tlu_flush_fd_w)  );

bw_u1_buf_30x UZfix_ifu_tlu_flush_fd2_w ( .a(ifu_tlu_flush_fd2_w_q), .z(ifu_tlu_flush_fd2_w) );

bw_u1_buf_30x UZfix_ifu_tlu_flush_fd2_w ( .a(ifu_tlu_flush_fd2_w_q), .z(ifu_tlu_flush_fd2_w) );

bw_u1_buf_30x UZfix_ifu_tlu_flush_fd3_w ( .a(ifu_tlu_flush_fd3_w_q), .z(ifu_tlu_flush_fd3_w) );

bw_u1_buf_30x UZfix_ifu_tlu_flush_fd3_w ( .a(ifu_tlu_flush_fd3_w_q), .z(ifu_tlu_flush_fd3_w) );

//=========================================================================================

//=========================================================================================

//  TLB Control 

//  TLB Control 

//=========================================================================================

//=========================================================================================

wire    alt_space_e ;

wire    alt_space_e ;

        .din    (ifu_lsu_alt_space_d),

        .din    (ifu_lsu_alt_space_d),

        .q      (alt_space_e),

        .q      (alt_space_e),

        .clk    (clk),

        .clk    (clk),

        );

        );

//Atomics require translation.

//Atomics require translation.

assign tlb_ldst_cam_vld =

assign tlb_ldst_cam_vld =

  memref_e &

  memref_e &

      //(thread3_e & memref_e) ;

      //(thread3_e & memref_e) ;

assign  altspace_ldst_e   = memref_e &  alt_space_e ;

assign  altspace_ldst_e   = memref_e &  alt_space_e ;

assign  non_altspace_ldst_e = memref_e & ~alt_space_e ;

assign  non_altspace_ldst_e = memref_e & ~alt_space_e ;

        .din    ({altspace_ldst_e,non_altspace_ldst_e}),

        .din    ({altspace_ldst_e,non_altspace_ldst_e}),

        .q      ({altspace_ldst_m,non_altspace_ldst_m}),

        .q      ({altspace_ldst_m,non_altspace_ldst_m}),

        .clk    (clk),

        .clk    (clk),

        );

        );

        .din    ({altspace_ldst_m,non_altspace_ldst_m}),

        .din    ({altspace_ldst_m,non_altspace_ldst_m}),

        .q      ({altspace_ldst_g,non_altspace_ldst_g}),

        .q      ({altspace_ldst_g,non_altspace_ldst_g}),

        .clk    (clk),

        .clk    (clk),

        );

        );

wire    [3:0]    tl_zero_d1 ;

wire    [3:0]    tl_zero_d1 ;

        .din    (tlu_lsu_tl_zero[3:0]),

        .din    (tlu_lsu_tl_zero[3:0]),

        .q      (tl_zero_d1[3:0]),

        .q      (tl_zero_d1[3:0]),

        .clk    (clk),

        .clk    (clk),

        );

        );

mux4ds  #(1) trap_level_zero_mux (

mux4ds  #(1) trap_level_zero_mux (

        .in0    (tl_zero_d1[0]),

        .in0    (tl_zero_d1[0]),

        .in1    (tl_zero_d1[1]),

        .in1    (tl_zero_d1[1]),

        .sel3   (thread3_e),

        .sel3   (thread3_e),

        .dout   (thread_tl_zero)

        .dout   (thread_tl_zero)

);

);

wire    thread_tl_zero_m ;

wire    thread_tl_zero_m ;

        .din    (thread_tl_zero),

        .din    (thread_tl_zero),

        .q      (thread_tl_zero_m),

        .q      (thread_tl_zero_m),

        .clk    (clk),

        .clk    (clk),

        );

        );

assign  lsu_nonalt_nucl_access_m = non_altspace_ldst_m & ~thread_tl_zero_m ;

assign  lsu_nonalt_nucl_access_m = non_altspace_ldst_m & ~thread_tl_zero_m ;

//tmp

//tmp

   wire thread_default;

   wire thread_default;

   assign thread_default = ~(thread_pctxt | thread_sctxt | thread_actxt);

   assign thread_default = ~(thread_pctxt | thread_sctxt | thread_actxt);

wire    [3:0]    pstate_am ;

wire    [3:0]    pstate_am ;

        .din    (tlu_lsu_pstate_am[3:0]),

        .din    (tlu_lsu_pstate_am[3:0]),

        .q      (pstate_am[3:0]),

        .q      (pstate_am[3:0]),

        .clk    (clk),

        .clk    (clk),

        );

        );

//assign  lsu_dtlb_addr_mask_l_e = 

//assign  lsu_dtlb_addr_mask_l_e = 

//  thread0_e ? ~pstate_am[0] :

//  thread0_e ? ~pstate_am[0] :

//    thread1_e ? ~pstate_am[1] :

//    thread1_e ? ~pstate_am[1] :

assign  admp_write = lsu_dtlb_dmp_vld_e & tlb_demap_actxt ;

assign  admp_write = lsu_dtlb_dmp_vld_e & tlb_demap_actxt ;

wire admp_rst ;

wire admp_rst ;

assign  admp_rst = reset | lsu_dtlb_wr_vld_e ;

assign  admp_rst = reset | lsu_dtlb_wr_vld_e ;

wire    local_dtlb_wr_vld_g ;

wire    local_dtlb_wr_vld_g ;

        .din    (admp_write),

        .din    (admp_write),

        .q      (local_dtlb_wr_vld_g),

        .q      (local_dtlb_wr_vld_g),

        .clk    (clk),

        .clk    (clk),

        .en     (admp_write),   .rst    (admp_rst),

        .en     (admp_write),   .rst    (admp_rst),

        );

        );

wire    dtlb_wr_init_d1,dtlb_wr_init_d2,dtlb_wr_init_d3 ;

wire    dtlb_wr_init_d1,dtlb_wr_init_d2,dtlb_wr_init_d3 ;

// Handshake between tlu and lsu needs to be fine-tuned !!!

// Handshake between tlu and lsu needs to be fine-tuned !!!