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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [lsu_dctldp.v] - Diff between revs 105 and 113

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Line 16... Line 16... 
// You should have received a copy of the GNU General Public
 
// You should have received a copy of the GNU General Public
 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
`define SIMPLY_RISC_SCANIN .si(0)
 
 
 
`else
 
 
 
`define SIMPLY_RISC_SCANIN .si()
 
 
 
`endif
 
/////////////////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////////////////
 
 
 
 
 
//FPGA_SYN enables all FPGA related modifications
 
//FPGA_SYN enables all FPGA related modifications
 
 
 
`ifdef FPGA_SYN
 
 
 
`define FPGA_SYN_CLK_EN
 
 
 
`define FPGA_SYN_CLK_DFF
 
 
 
`endif
 
 
 
 
 
module lsu_dctldp (/*AUTOARG*/
 
module lsu_dctldp (/*AUTOARG*/
 
   // Outputs
 
   // Outputs
 
   so, asi_d, lsu_excpctl_asi_state_m, lsu_dctl_asi_state_m,
 
   so, asi_d, lsu_excpctl_asi_state_m, lsu_dctl_asi_state_m,
 
   lsu_spu_asi_state_e, lsu_tlu_rsr_data_e, lsu_asi_state,
 
   lsu_spu_asi_state_e, lsu_tlu_rsr_data_e, lsu_asi_state,
Line 261... Line 266... 
   assign     clk = rclk;
 
   assign     clk = rclk;
 
 
 
 
 
/********************* ASI state ***********************/
 
/********************* ASI state ***********************/
 
   wire [7:0]  tlu_lsu_asi_g;
 
   wire [7:0]  tlu_lsu_asi_g;
 
 
 
 
 
dff #(8) asi_stgw (
 
dff_s #(8) asi_stgw (
 
        .din    (tlu_lsu_asi_m[7:0]),
 
        .din    (tlu_lsu_asi_m[7:0]),
 
        .q      (tlu_lsu_asi_g[7:0]),
 
        .q      (tlu_lsu_asi_g[7:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
   wire [7:0]  exu_tlu_wsr_data_w;
 
   wire [7:0]  exu_tlu_wsr_data_w;
 
 
 
 
 
dff #(8) ff_wsr_data_w (
 
dff_s #(8) ff_wsr_data_w (
 
        .din    (exu_tlu_wsr_data_m[7:0]),
 
        .din    (exu_tlu_wsr_data_m[7:0]),
 
        .q      (exu_tlu_wsr_data_w[7:0]),
 
        .q      (exu_tlu_wsr_data_w[7:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
   wire [7:0]  asi_wr_din;
 
   wire [7:0]  asi_wr_din;
 
 
 
 
 
assign  asi_wr_din[7:0] = tlu_lsu_asi_update_g ? tlu_lsu_asi_g[7:0] : exu_tlu_wsr_data_w[7:0] ;
 
assign  asi_wr_din[7:0] = tlu_lsu_asi_update_g ? tlu_lsu_asi_g[7:0] : exu_tlu_wsr_data_w[7:0] ;
Line 287... Line 292... 
   wire [7:0] asi_state0;
 
   wire [7:0] asi_state0;
 
   wire [7:0] lsu_asi_reg0;
 
   wire [7:0] lsu_asi_reg0;
 
 
 
 
 
   wire       asi0_state_clk;
 
   wire       asi0_state_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf asi0_state_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~asi_state_wr_thrd[0]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (asi0_state_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(8) asi0_state_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(8) asi0_state_ff (
 
 
 
        .din    (asi_wr_din[7:0]),
 
        .din    (asi_wr_din[7:0]),
 
        .q      (asi_state0[7:0]),
 
        .q      (asi_state0[7:0]),
 
        .en (~(~asi_state_wr_thrd[0])), .clk(clk),
 
        .en (~(~asi_state_wr_thrd[0])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(8) asi0_state_ff (
 
 
 
        .din    (asi_wr_din[7:0]),
 
 
 
        .q      (asi_state0[7:0]),
 
 
 
        .clk    (asi0_state_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_asi_reg0[7:0] = asi_state0[7:0] ;
 
assign  lsu_asi_reg0[7:0] = asi_state0[7:0] ;
 
 
 
 
 
// ASI - Thread1
 
// ASI - Thread1
 
   wire [7:0] asi_state1;
 
   wire [7:0] asi_state1;
 
   wire [7:0] lsu_asi_reg1;
 
   wire [7:0] lsu_asi_reg1;
 
 
 
 
 
   wire       asi1_state_clk;
 
   wire       asi1_state_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf asi1_state_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~asi_state_wr_thrd[1]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (asi1_state_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(8) asi1_state_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(8) asi1_state_ff (
 
 
 
        .din    (asi_wr_din[7:0]),
 
        .din    (asi_wr_din[7:0]),
 
        .q      (asi_state1[7:0]),
 
        .q      (asi_state1[7:0]),
 
        .en (~(~asi_state_wr_thrd[1])), .clk(clk),
 
        .en (~(~asi_state_wr_thrd[1])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(8) asi1_state_ff (
 
 
 
        .din    (asi_wr_din[7:0]),
 
 
 
        .q      (asi_state1[7:0]),
 
 
 
        .clk    (asi1_state_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_asi_reg1[7:0] = asi_state1[7:0] ;
 
assign  lsu_asi_reg1[7:0] = asi_state1[7:0] ;
 
 
 
 
 
// ASI - Thread2
 
// ASI - Thread2
 
   wire [7:0] asi_state2;
 
   wire [7:0] asi_state2;
 
   wire [7:0] lsu_asi_reg2;
 
   wire [7:0] lsu_asi_reg2;
 
 
 
 
 
   wire       asi2_state_clk;
 
   wire       asi2_state_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf asi2_state_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~asi_state_wr_thrd[2]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (asi2_state_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(8) asi2_state_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(8) asi2_state_ff (
 
 
 
        .din    (asi_wr_din[7:0]),
 
        .din    (asi_wr_din[7:0]),
 
        .q      (asi_state2[7:0]),
 
        .q      (asi_state2[7:0]),
 
        .en (~(~asi_state_wr_thrd[2])), .clk(clk),
 
        .en (~(~asi_state_wr_thrd[2])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(8) asi2_state_ff (
 
 
 
        .din    (asi_wr_din[7:0]),
 
 
 
        .q      (asi_state2[7:0]),
 
 
 
        .clk    (asi2_state_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_asi_reg2[7:0] = asi_state2[7:0] ;
 
assign  lsu_asi_reg2[7:0] = asi_state2[7:0] ;
 
 
 
 
 
// ASI - Thread3
 
// ASI - Thread3
 
   wire [7:0] asi_state3;
 
   wire [7:0] asi_state3;
 
   wire [7:0] lsu_asi_reg3;
 
   wire [7:0] lsu_asi_reg3;
 
 
 
 
 
   wire       asi3_state_clk;
 
   wire       asi3_state_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf asi3_state_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~asi_state_wr_thrd[3]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (asi3_state_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(8) asi3_state_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(8) asi3_state_ff (
 
 
 
        .din    (asi_wr_din[7:0]),
 
        .din    (asi_wr_din[7:0]),
 
        .q      (asi_state3[7:0]),
 
        .q      (asi_state3[7:0]),
 
        .en (~(~asi_state_wr_thrd[3])), .clk(clk),
 
        .en (~(~asi_state_wr_thrd[3])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(8) asi3_state_ff (
 
 
 
        .din    (asi_wr_din[7:0]),
 
 
 
        .q      (asi_state3[7:0]),
 
 
 
        .clk    (asi3_state_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_asi_reg3[7:0] = asi_state3[7:0] ;
 
assign  lsu_asi_reg3[7:0] = asi_state3[7:0] ;
 
 
 
 
 
   wire [7:0] asi_state;
 
   wire [7:0] asi_state;
 
 
 
 
Line 436... Line 441... 
assign  asi_d[7:0] = ifu_lsu_imm_asi_vld_d ?
 
assign  asi_d[7:0] = ifu_lsu_imm_asi_vld_d ?
 
                     ifu_lsu_imm_asi_d[7:0] : asi_state[7:0];
 
                     ifu_lsu_imm_asi_d[7:0] : asi_state[7:0];
 
 
 
 
 
wire  [7:0] asi_state_e, asi_state_m ;
 
wire  [7:0] asi_state_e, asi_state_m ;
 
 
 
 
 
dff #(8) asistate_stge (
 
dff_s #(8) asistate_stge (
 
        .din    (asi_d[7:0]),
 
        .din    (asi_d[7:0]),
 
        .q      (asi_state_e[7:0]),
 
        .q      (asi_state_e[7:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
// Make rsr_data independent of imm_asi.
 
// Make rsr_data independent of imm_asi.
 
dff #(8) rdasi_stge (
 
dff_s #(8) rdasi_stge (
 
        .din    (asi_state[7:0]),
 
        .din    (asi_state[7:0]),
 
        .q      (lsu_tlu_rsr_data_e[7:0]),
 
        .q      (lsu_tlu_rsr_data_e[7:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
//assign lsu_tlu_rsr_data_e[7:0] =  asi_state_e[7:0] ;
 
//assign lsu_tlu_rsr_data_e[7:0] =  asi_state_e[7:0] ;
 
 
 
 
 
assign  lsu_spu_asi_state_e[7:0] = asi_state_e[7:0] ;
 
assign  lsu_spu_asi_state_e[7:0] = asi_state_e[7:0] ;
 
 
 
 
 
dff #(8) asistate_stgm (
 
dff_s #(8) asistate_stgm (
 
        .din    (asi_state_e[7:0]),
 
        .din    (asi_state_e[7:0]),
 
        .q      (asi_state_m[7:0]),
 
        .q      (asi_state_m[7:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
assign  lsu_excpctl_asi_state_m[7:0] = asi_state_m[7:0] ;
 
assign  lsu_excpctl_asi_state_m[7:0] = asi_state_m[7:0] ;
 
assign  lsu_dctl_asi_state_m[7:0]    = asi_state_m[7:0] ;
 
assign  lsu_dctl_asi_state_m[7:0]    = asi_state_m[7:0] ;
 
 
 
 
 
   wire [7:0] lsu_asi_state;
 
   wire [7:0] lsu_asi_state;
 
dff #(8) asistate_stgg (
 
dff_s #(8) asistate_stgg (
 
        .din    (asi_state_m[7:0]),
 
        .din    (asi_state_m[7:0]),
 
        .q      (lsu_asi_state[7:0]),
 
        .q      (lsu_asi_state[7:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
 
 
 
 
/*********************context************************/
 
/*********************context************************/
 
wire  [12:0]  pctxt_state0,pctxt_state1;
 
wire  [12:0]  pctxt_state0,pctxt_state1;
Line 483... Line 488... 
wire  [12:0]  sctxt_state2,sctxt_state3;
 
wire  [12:0]  sctxt_state2,sctxt_state3;
 
 
 
 
 
// PRIMARY CONTEXT - Thread0
 
// PRIMARY CONTEXT - Thread0
 
   wire       pctxt0_state_clk;
 
   wire       pctxt0_state_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf pctxt0_state_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~pctxt_state_wr_thrd[0]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (pctxt0_state_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(13) pctxt_state0_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(13) pctxt_state0_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
        .din    (st_rs3_data_g[12:0]),
 
        .q      (pctxt_state0[12:0]),
 
        .q      (pctxt_state0[12:0]),
 
        .en (~(~pctxt_state_wr_thrd[0])), .clk(clk),
 
        .en (~(~pctxt_state_wr_thrd[0])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(13) pctxt_state0_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
 
 
        .q      (pctxt_state0[12:0]),
 
 
 
        .clk    (pctxt0_state_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_t0_pctxt_state[12:0] = pctxt_state0[12:0] ;
 
assign  lsu_t0_pctxt_state[12:0] = pctxt_state0[12:0] ;
 
 
 
 
 
// PRIMARY CONTEXT - Thread1
 
// PRIMARY CONTEXT - Thread1
 
   wire       pctxt1_state_clk;
 
   wire       pctxt1_state_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf pctxt1_state_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~pctxt_state_wr_thrd[1]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (pctxt1_state_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(13) pctxt_state1_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(13) pctxt_state1_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
        .din    (st_rs3_data_g[12:0]),
 
        .q      (pctxt_state1[12:0]),
 
        .q      (pctxt_state1[12:0]),
 
        .en (~(~pctxt_state_wr_thrd[1])), .clk(clk),
 
        .en (~(~pctxt_state_wr_thrd[1])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(13) pctxt_state1_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
 
 
        .q      (pctxt_state1[12:0]),
 
 
 
        .clk    (pctxt1_state_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_t1_pctxt_state[12:0] = pctxt_state1[12:0] ;
 
assign  lsu_t1_pctxt_state[12:0] = pctxt_state1[12:0] ;
 
 
 
 
 
// PRIMARY CONTEXT - Thread2
 
// PRIMARY CONTEXT - Thread2
 
   wire       pctxt2_state_clk;
 
   wire       pctxt2_state_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf pctxt2_state_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~pctxt_state_wr_thrd[2]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (pctxt2_state_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(13) pctxt_state2_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(13) pctxt_state2_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
        .din    (st_rs3_data_g[12:0]),
 
        .q      (pctxt_state2[12:0]),
 
        .q      (pctxt_state2[12:0]),
 
        .en (~(~pctxt_state_wr_thrd[2])), .clk(clk),
 
        .en (~(~pctxt_state_wr_thrd[2])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(13) pctxt_state2_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
 
 
        .q      (pctxt_state2[12:0]),
 
 
 
        .clk    (pctxt2_state_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_t2_pctxt_state[12:0] = pctxt_state2[12:0] ;
 
assign  lsu_t2_pctxt_state[12:0] = pctxt_state2[12:0] ;
 
 
 
 
 
// PRIMARY CONTEXT - Thread3
 
// PRIMARY CONTEXT - Thread3
 
   wire       pctxt3_state_clk;
 
   wire       pctxt3_state_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf pctxt3_state_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~pctxt_state_wr_thrd[3]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (pctxt3_state_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(13) pctxt_state3_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(13) pctxt_state3_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
        .din    (st_rs3_data_g[12:0]),
 
        .q      (pctxt_state3[12:0]),
 
        .q      (pctxt_state3[12:0]),
 
        .en (~(~pctxt_state_wr_thrd[3])), .clk(clk),
 
        .en (~(~pctxt_state_wr_thrd[3])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(13) pctxt_state3_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
 
 
        .q      (pctxt_state3[12:0]),
 
 
 
        .clk    (pctxt3_state_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_t3_pctxt_state[12:0] = pctxt_state3[12:0] ;
 
assign  lsu_t3_pctxt_state[12:0] = pctxt_state3[12:0] ;
 
 
 
 
 
// SECONDARY CONTEXT - Thread0
 
// SECONDARY CONTEXT - Thread0
 
   wire       sctxt0_state_clk;
 
   wire       sctxt0_state_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf sctxt0_state_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~sctxt_state_wr_thrd[0]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (sctxt0_state_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(13) sctxt_state0_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(13) sctxt_state0_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
        .din    (st_rs3_data_g[12:0]),
 
        .q      (sctxt_state0[12:0]),
 
        .q      (sctxt_state0[12:0]),
 
        .en (~(~sctxt_state_wr_thrd[0])), .clk(clk),
 
        .en (~(~sctxt_state_wr_thrd[0])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(13) sctxt_state0_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
 
 
        .q      (sctxt_state0[12:0]),
 
 
 
        .clk    (sctxt0_state_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
// SECONDARY CONTEXT - Thread1
 
// SECONDARY CONTEXT - Thread1
 
   wire       sctxt1_state_clk;
 
   wire       sctxt1_state_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf sctxt1_state_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~sctxt_state_wr_thrd[1]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (sctxt1_state_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(13) sctxt_state1_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(13) sctxt_state1_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
        .din    (st_rs3_data_g[12:0]),
 
        .q      (sctxt_state1[12:0]),
 
        .q      (sctxt_state1[12:0]),
 
        .en (~(~sctxt_state_wr_thrd[1])), .clk(clk),
 
        .en (~(~sctxt_state_wr_thrd[1])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(13) sctxt_state1_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
 
 
        .q      (sctxt_state1[12:0]),
 
 
 
        .clk    (sctxt1_state_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
// SECONDARY CONTEXT - Thread2
 
// SECONDARY CONTEXT - Thread2
 
   wire       sctxt2_state_clk;
 
   wire       sctxt2_state_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf sctxt2_state_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~sctxt_state_wr_thrd[2]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (sctxt2_state_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(13) sctxt_state2_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(13) sctxt_state2_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
        .din    (st_rs3_data_g[12:0]),
 
        .q      (sctxt_state2[12:0]),
 
        .q      (sctxt_state2[12:0]),
 
        .en (~(~sctxt_state_wr_thrd[2])), .clk(clk),
 
        .en (~(~sctxt_state_wr_thrd[2])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(13) sctxt_state2_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
 
 
        .q      (sctxt_state2[12:0]),
 
 
 
        .clk    (sctxt2_state_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
// SECONDARY CONTEXT - Thread3
 
// SECONDARY CONTEXT - Thread3
 
   wire       sctxt3_state_clk;
 
   wire       sctxt3_state_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf sctxt3_state_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~sctxt_state_wr_thrd[3]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (sctxt3_state_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(13) sctxt_state3_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
 
 
        .q      (sctxt_state3[12:0]),
 
 
 
        .en (~(~sctxt_state_wr_thrd[3])), .clk(clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`else
 
 
 
dff_s #(13) sctxt_state3_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
 
 
        .q      (sctxt_state3[12:0]),
 
 
 
        .clk    (sctxt3_state_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
 
 
wire  [12:0]  current_pctxt_e,current_sctxt_e ;
 
 
 
wire  [12:0]  current_pctxt_m ;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(13) sctxt_state3_ff (
 
 
 
        .din    (st_rs3_data_g[12:0]),
 
 
 
        .q      (sctxt_state3[12:0]),
 
 
 
        .en (~(~sctxt_state_wr_thrd[3])), .clk(clk),
 
 
 
        .se     (se),       .si (),          .so ()
 
 
 
        );
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
wire  [12:0]  current_pctxt_e,current_sctxt_e ;
 
 
 
wire  [12:0]  current_pctxt_m ;
 
 
 
 
 
 
 
wire  [12:0]  current_ctxt_e,current_ctxt_m ;
 
wire  [12:0]  current_ctxt_e,current_ctxt_m ;
 
 
 
 
 
mux4ds #(13) current_pctxt_e_mux (
 
mux4ds #(13) current_pctxt_e_mux (
 
   .in0 (pctxt_state0[12:0]),
 
   .in0 (pctxt_state0[12:0]),
Line 791... Line 796... 
   .sel3(thread3_e),
 
   .sel3(thread3_e),
 
   .dout(itrap_pctxt_e[12:0])
 
   .dout(itrap_pctxt_e[12:0])
 
   );
 
   );
 
 
 
 
 
// Create current ctxt for tlu purpose.
 
// Create current ctxt for tlu purpose.
 
dff #(26) cctxt_stgm (
 
dff_s #(26) cctxt_stgm (
 
        .din    ({current_ctxt_e[12:0],itrap_pctxt_e[12:0]}),
 
        .din    ({current_ctxt_e[12:0],itrap_pctxt_e[12:0]}),
 
        .q      ({current_ctxt_m[12:0],current_pctxt_m[12:0]}),
 
        .q      ({current_ctxt_m[12:0],current_pctxt_m[12:0]}),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
assign  lsu_tlu_dside_ctxt_m[12:0] = current_ctxt_m[12:0] ;
 
assign  lsu_tlu_dside_ctxt_m[12:0] = current_ctxt_m[12:0] ;
 
assign  lsu_tlu_pctxt_m[12:0] = current_pctxt_m[12:0] ;
 
assign  lsu_tlu_pctxt_m[12:0] = current_pctxt_m[12:0] ;
 
 
 
 
Line 838... Line 843... 
   wire [2:0] pid_state_din;
 
   wire [2:0] pid_state_din;
 
   assign     pid_state_din[2:0] = {3{rst_l}} & st_rs3_data_g[2:0];
 
   assign     pid_state_din[2:0] = {3{rst_l}} & st_rs3_data_g[2:0];
 
 
 
 
 
   wire       pid_state0_clk;
 
   wire       pid_state0_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf pid_state0_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~pid_state_wr_en[0]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (pid_state0_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(3) pid0_state (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(3) pid0_state (
 
 
 
        .din    (pid_state_din[2:0]),
 
        .din    (pid_state_din[2:0]),
 
        .q      (pid_state0[2:0]),
 
        .q      (pid_state0[2:0]),
 
        .en (~(~pid_state_wr_en[0])), .clk(clk),
 
        .en (~(~pid_state_wr_en[0])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(3) pid0_state (
 
 
 
        .din    (pid_state_din[2:0]),
 
 
 
        .q      (pid_state0[2:0]),
 
 
 
        .clk    (pid_state0_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_pid_state0[2:0] = pid_state0[2:0] ;
 
assign  lsu_pid_state0[2:0] = pid_state0[2:0] ;
 
 
 
 
 
// Thread1
 
// Thread1
 
   wire       pid_state1_clk;
 
   wire       pid_state1_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf pid_state1_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~pid_state_wr_en[1]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (pid_state1_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(3) pid1_state (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(3) pid1_state (
 
 
 
        .din    (pid_state_din[2:0]),
 
        .din    (pid_state_din[2:0]),
 
        .q      (pid_state1[2:0]),
 
        .q      (pid_state1[2:0]),
 
        .en (~(~pid_state_wr_en[1])), .clk(clk),
 
        .en (~(~pid_state_wr_en[1])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(3) pid1_state (
 
 
 
        .din    (pid_state_din[2:0]),
 
 
 
        .q      (pid_state1[2:0]),
 
 
 
        .clk    (pid_state1_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_pid_state1[2:0] = pid_state1[2:0] ;
 
assign  lsu_pid_state1[2:0] = pid_state1[2:0] ;
 
 
 
 
 
// Thread2
 
// Thread2
 
   wire       pid_state2_clk;
 
   wire       pid_state2_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf pid_state2_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~pid_state_wr_en[2]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (pid_state2_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(3) pid2_state (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(3) pid2_state (
 
 
 
        .din    (pid_state_din[2:0]),
 
        .din    (pid_state_din[2:0]),
 
        .q      (pid_state2[2:0]),
 
        .q      (pid_state2[2:0]),
 
        .en (~(~pid_state_wr_en[2])), .clk(clk),
 
        .en (~(~pid_state_wr_en[2])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(3) pid2_state (
 
 
 
        .din    (pid_state_din[2:0]),
 
 
 
        .q      (pid_state2[2:0]),
 
 
 
        .clk    (pid_state2_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_pid_state2[2:0] = pid_state2[2:0] ;
 
assign  lsu_pid_state2[2:0] = pid_state2[2:0] ;
 
 
 
 
 
// Thread3
 
// Thread3
 
   wire       pid_state3_clk;
 
   wire       pid_state3_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf pid_state3_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~pid_state_wr_en[3]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (pid_state3_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(3) pid3_state (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(3) pid3_state (
 
 
 
        .din    (pid_state_din[2:0]),
 
        .din    (pid_state_din[2:0]),
 
        .q      (pid_state3[2:0]),
 
        .q      (pid_state3[2:0]),
 
        .en (~(~pid_state_wr_en[3])), .clk(clk),
 
        .en (~(~pid_state_wr_en[3])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(3) pid3_state (
 
 
 
        .din    (pid_state_din[2:0]),
 
 
 
        .q      (pid_state3[2:0]),
 
 
 
        .clk    (pid_state3_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_pid_state3[2:0] = pid_state3[2:0] ;
 
assign  lsu_pid_state3[2:0] = pid_state3[2:0] ;
 
 
 
 
 
wire [2:0] cam_pid_e ;
 
wire [2:0] cam_pid_e ;
 
// Hypervisor related cam inputs
 
// Hypervisor related cam inputs
Line 1038... Line 1043... 
   wire [9:0] lsu_ctl_reg0_din;
 
   wire [9:0] lsu_ctl_reg0_din;
 
   assign      lsu_ctl_reg0_din[9:0] = {10{~lctl_rst[0]}} & lsu_ctl_reg_din[9:0];
 
   assign      lsu_ctl_reg0_din[9:0] = {10{~lctl_rst[0]}} & lsu_ctl_reg_din[9:0];
 
 
 
 
 
   wire        lsu_ctl_state0_clk;
 
   wire        lsu_ctl_state0_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf lsu_ctl_state0_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~lsu_ctl_state_wr_en[0]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (lsu_ctl_state0_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(10) lsu_ctl_reg0_ff2 (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(10) lsu_ctl_reg0_ff2 (
 
 
 
        .din    (lsu_ctl_reg0_din[9:0]),
 
        .din    (lsu_ctl_reg0_din[9:0]),
 
        .q      (lsu_ctl_reg0[13:4]),
 
        .q      (lsu_ctl_reg0[13:4]),
 
        .en (~(~lsu_ctl_state_wr_en[0])), .clk(clk),
 
        .en (~(~lsu_ctl_state_wr_en[0])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(10) lsu_ctl_reg0_ff2 (
 
 
 
        .din    (lsu_ctl_reg0_din[9:0]),
 
 
 
        .q      (lsu_ctl_reg0[13:4]),
 
 
 
        .clk    (lsu_ctl_state0_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
   wire [3:0]  lsuctl_ctlbits0_wr_data_din;
 
   wire [3:0]  lsuctl_ctlbits0_wr_data_din;
 
   assign      lsuctl_ctlbits0_wr_data_din[3:0] = {4{~lctl_rst[0]}} & lsuctl_ctlbits_wr_data[3:0];
 
   assign      lsuctl_ctlbits0_wr_data_din[3:0] = {4{~lctl_rst[0]}} & lsuctl_ctlbits_wr_data[3:0];
 
 
 
 
 
   wire        lsuctl_ctlbits0_clk;
 
   wire        lsuctl_ctlbits0_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf lsuctl_ctlbits0_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~lsuctl_ctlbits_wr_en[0]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (lsuctl_ctlbits0_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(4) lsu_ctl_reg0_ff1 (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(4) lsu_ctl_reg0_ff1 (
 
 
 
        .din    (lsuctl_ctlbits0_wr_data_din[3:0]),
 
        .din    (lsuctl_ctlbits0_wr_data_din[3:0]),
 
        .q      (lsu_ctl_reg0[3:0]),
 
        .q      (lsu_ctl_reg0[3:0]),
 
        .en (~(~lsuctl_ctlbits_wr_en[0])), .clk(clk),
 
        .en (~(~lsuctl_ctlbits_wr_en[0])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(4) lsu_ctl_reg0_ff1 (
 
 
 
        .din    (lsuctl_ctlbits0_wr_data_din[3:0]),
 
 
 
        .q      (lsu_ctl_reg0[3:0]),
 
 
 
        .clk    (lsuctl_ctlbits0_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
// Thread1
 
// Thread1
 
   wire [9:0] lsu_ctl_reg1_din;
 
   wire [9:0] lsu_ctl_reg1_din;
 
   assign      lsu_ctl_reg1_din[9:0] = {10{~lctl_rst[1]}} & lsu_ctl_reg_din[9:0];
 
   assign      lsu_ctl_reg1_din[9:0] = {10{~lctl_rst[1]}} & lsu_ctl_reg_din[9:0];
 
 
 
 
 
   wire        lsu_ctl_state1_clk;
 
   wire        lsu_ctl_state1_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf lsu_ctl_state1_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~lsu_ctl_state_wr_en[1]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (lsu_ctl_state1_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(10) lsu_ctl_reg1_ff2 (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(10) lsu_ctl_reg1_ff2 (
 
 
 
        .din    (lsu_ctl_reg1_din[9:0]),
 
        .din    (lsu_ctl_reg1_din[9:0]),
 
        .q      (lsu_ctl_reg1[13:4]),
 
        .q      (lsu_ctl_reg1[13:4]),
 
        .en (~(~lsu_ctl_state_wr_en[1])), .clk(clk),
 
        .en (~(~lsu_ctl_state_wr_en[1])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(10) lsu_ctl_reg1_ff2 (
 
 
 
        .din    (lsu_ctl_reg1_din[9:0]),
 
 
 
        .q      (lsu_ctl_reg1[13:4]),
 
 
 
        .clk    (lsu_ctl_state1_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
   wire [3:0]  lsuctl_ctlbits1_wr_data_din;
 
   wire [3:0]  lsuctl_ctlbits1_wr_data_din;
 
   assign      lsuctl_ctlbits1_wr_data_din[3:0] = {4{~lctl_rst[1]}} & lsuctl_ctlbits_wr_data[3:0];
 
   assign      lsuctl_ctlbits1_wr_data_din[3:0] = {4{~lctl_rst[1]}} & lsuctl_ctlbits_wr_data[3:0];
 
 
 
 
 
   wire        lsuctl_ctlbits1_clk;
 
   wire        lsuctl_ctlbits1_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf lsuctl_ctlbits1_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~lsuctl_ctlbits_wr_en[1]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (lsuctl_ctlbits1_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(4) lsu_ctl_reg1_ff1 (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(4) lsu_ctl_reg1_ff1 (
 
 
 
        .din    (lsuctl_ctlbits1_wr_data_din[3:0]),
 
        .din    (lsuctl_ctlbits1_wr_data_din[3:0]),
 
        .q      (lsu_ctl_reg1[3:0]),
 
        .q      (lsu_ctl_reg1[3:0]),
 
        .en (~(~lsuctl_ctlbits_wr_en[1])), .clk(clk),
 
        .en (~(~lsuctl_ctlbits_wr_en[1])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(4) lsu_ctl_reg1_ff1 (
 
 
 
        .din    (lsuctl_ctlbits1_wr_data_din[3:0]),
 
 
 
        .q      (lsu_ctl_reg1[3:0]),
 
 
 
        .clk    (lsuctl_ctlbits1_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
// Thread2
 
// Thread2
 
   wire [9:0] lsu_ctl_reg2_din;
 
   wire [9:0] lsu_ctl_reg2_din;
 
   assign      lsu_ctl_reg2_din[9:0] = {10{~lctl_rst[2]}} & lsu_ctl_reg_din[9:0];
 
   assign      lsu_ctl_reg2_din[9:0] = {10{~lctl_rst[2]}} & lsu_ctl_reg_din[9:0];
 
 
 
 
 
   wire        lsu_ctl_state2_clk;
 
   wire        lsu_ctl_state2_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf lsu_ctl_state2_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~lsu_ctl_state_wr_en[2]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (lsu_ctl_state2_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(10) lsu_ctl_reg2_ff2 (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(10) lsu_ctl_reg2_ff2 (
 
 
 
        .din    (lsu_ctl_reg2_din[9:0]),
 
        .din    (lsu_ctl_reg2_din[9:0]),
 
        .q      (lsu_ctl_reg2[13:4]),
 
        .q      (lsu_ctl_reg2[13:4]),
 
        .en (~(~lsu_ctl_state_wr_en[2])), .clk(clk),
 
        .en (~(~lsu_ctl_state_wr_en[2])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(10) lsu_ctl_reg2_ff2 (
 
 
 
        .din    (lsu_ctl_reg2_din[9:0]),
 
 
 
        .q      (lsu_ctl_reg2[13:4]),
 
 
 
        .clk    (lsu_ctl_state2_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
   wire [3:0]  lsuctl_ctlbits2_wr_data_din;
 
   wire [3:0]  lsuctl_ctlbits2_wr_data_din;
 
   assign      lsuctl_ctlbits2_wr_data_din[3:0] = {4{~lctl_rst[2]}} & lsuctl_ctlbits_wr_data[3:0];
 
   assign      lsuctl_ctlbits2_wr_data_din[3:0] = {4{~lctl_rst[2]}} & lsuctl_ctlbits_wr_data[3:0];
 
 
 
 
 
   wire        lsuctl_ctlbits2_clk;
 
   wire        lsuctl_ctlbits2_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf lsuctl_ctlbits2_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~lsuctl_ctlbits_wr_en[2]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (lsuctl_ctlbits2_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(4) lsu_ctl_reg2_ff1 (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(4) lsu_ctl_reg2_ff1 (
 
 
 
        .din    (lsuctl_ctlbits2_wr_data_din[3:0]),
 
        .din    (lsuctl_ctlbits2_wr_data_din[3:0]),
 
        .q      (lsu_ctl_reg2[3:0]),
 
        .q      (lsu_ctl_reg2[3:0]),
 
        .en (~(~lsuctl_ctlbits_wr_en[2])), .clk(clk),
 
        .en (~(~lsuctl_ctlbits_wr_en[2])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(4) lsu_ctl_reg2_ff1 (
 
 
 
        .din    (lsuctl_ctlbits2_wr_data_din[3:0]),
 
 
 
        .q      (lsu_ctl_reg2[3:0]),
 
 
 
        .clk    (lsuctl_ctlbits2_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
// Thread3
 
// Thread3
 
   wire [9:0] lsu_ctl_reg3_din;
 
   wire [9:0] lsu_ctl_reg3_din;
 
   assign      lsu_ctl_reg3_din[9:0] = {10{~lctl_rst[3]}} & lsu_ctl_reg_din[9:0];
 
   assign      lsu_ctl_reg3_din[9:0] = {10{~lctl_rst[3]}} & lsu_ctl_reg_din[9:0];
 
 
 
 
 
   wire        lsu_ctl_state3_clk;
 
   wire        lsu_ctl_state3_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf lsu_ctl_state3_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~lsu_ctl_state_wr_en[3]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (lsu_ctl_state3_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(10) lsu_ctl_reg3_ff2 (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(10) lsu_ctl_reg3_ff2 (
 
 
 
        .din    (lsu_ctl_reg3_din[9:0]),
 
        .din    (lsu_ctl_reg3_din[9:0]),
 
        .q      (lsu_ctl_reg3[13:4]),
 
        .q      (lsu_ctl_reg3[13:4]),
 
        .en (~(~lsu_ctl_state_wr_en[3])), .clk(clk),
 
        .en (~(~lsu_ctl_state_wr_en[3])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(10) lsu_ctl_reg3_ff2 (
 
 
 
        .din    (lsu_ctl_reg3_din[9:0]),
 
 
 
        .q      (lsu_ctl_reg3[13:4]),
 
 
 
        .clk    (lsu_ctl_state3_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
   wire [3:0]  lsuctl_ctlbits3_wr_data_din;
 
   wire [3:0]  lsuctl_ctlbits3_wr_data_din;
 
   assign      lsuctl_ctlbits3_wr_data_din[3:0] = {4{~lctl_rst[3]}} & lsuctl_ctlbits_wr_data[3:0];
 
   assign      lsuctl_ctlbits3_wr_data_din[3:0] = {4{~lctl_rst[3]}} & lsuctl_ctlbits_wr_data[3:0];
 
 
 
 
 
   wire        lsuctl_ctlbits3_clk;
 
   wire        lsuctl_ctlbits3_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf lsuctl_ctlbits3_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~lsuctl_ctlbits_wr_en[3]),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (lsuctl_ctlbits3_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(4) lsu_ctl_reg3_ff1 (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(4) lsu_ctl_reg3_ff1 (
 
 
 
        .din    (lsuctl_ctlbits3_wr_data_din[3:0]),
 
        .din    (lsuctl_ctlbits3_wr_data_din[3:0]),
 
        .q      (lsu_ctl_reg3[3:0]),
 
        .q      (lsu_ctl_reg3[3:0]),
 
        .en (~(~lsuctl_ctlbits_wr_en[3])), .clk(clk),
 
        .en (~(~lsuctl_ctlbits_wr_en[3])), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(4) lsu_ctl_reg3_ff1 (
 
 
 
        .din    (lsuctl_ctlbits3_wr_data_din[3:0]),
 
 
 
        .q      (lsu_ctl_reg3[3:0]),
 
 
 
        .clk    (lsuctl_ctlbits3_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
// LSU Ctl Reg
 
// LSU Ctl Reg
 
mux4ds #(14)     lctlrg_mx (
 
mux4ds #(14)     lctlrg_mx (
 
        .in0    (lsu_ctl_reg0[13:0]),
 
        .in0    (lsu_ctl_reg0[13:0]),
 
        .in1    (lsu_ctl_reg1[13:0]),
 
        .in1    (lsu_ctl_reg1[13:0]),
Line 1370... Line 1375... 
                .clk    (bistctl_clk)
 
                .clk    (bistctl_clk)
 
                ) ;
 
                ) ;
 
`endif
 
`endif
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
`ifdef FPGA_SYN_CLK_DFF
 
dffe #(11) bistctl_ff (
 
dffe_s #(11) bistctl_ff (
 
        .din    (bistctl_data_in[10:0]),
 
        .din    (bistctl_data_in[10:0]),
 
        .q      (bist_ctl_reg[10:0]),
 
        .q      (bist_ctl_reg[10:0]),
 
        .en (~(~bistctl_wr_en)), .clk(clk),
 
        .en (~(~bistctl_wr_en)), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
`else
 
`else
 
dff #(11) bistctl_ff (
 
dff_s #(11) bistctl_ff (
 
        .din    (bistctl_data_in[10:0]),
 
        .din    (bistctl_data_in[10:0]),
 
        .q      (bist_ctl_reg[10:0]),
 
        .q      (bist_ctl_reg[10:0]),
 
        .clk    (bistctl_clk),
 
        .clk    (bistctl_clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
`endif
 
`endif
 
*/
 
*/
 
 
 
 
 
// Self-Timed Margin Control ASI
 
// Self-Timed Margin Control ASI
Line 1409... Line 1414... 
(~rst_l) ?  {8'b01011011, 8'b01011011, 4'b0101,4'b0101,4'b0101} :
 
(~rst_l) ?  {8'b01011011, 8'b01011011, 4'b0101,4'b0101,4'b0101} :
 
             st_rs3_data_g[27:0];
 
             st_rs3_data_g[27:0];
 
 
 
 
 
   wire mrgnctl_clk;
 
   wire mrgnctl_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf mrgnctl_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~mrgnctl_wr_en),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (mrgnctl_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(28) mrgnctl_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(28) mrgnctl_ff (
 
 
 
        .din    (mrgnctl_data_in[27:0]),
 
        .din    (mrgnctl_data_in[27:0]),
 
        .q      (mrgn_ctl_reg[27:0]),
 
        .q      (mrgn_ctl_reg[27:0]),
 
        .en (~(~mrgnctl_wr_en)), .clk(clk),
 
        .en (~(~mrgnctl_wr_en)), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(28) mrgnctl_ff (
 
 
 
        .din    (mrgnctl_data_in[27:0]),
 
 
 
        .q      (mrgn_ctl_reg[27:0]),
 
 
 
        .clk    (mrgnctl_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_itlb_mrgn[7:0] = mrgn_ctl_reg[27:20] ;
 
assign  lsu_itlb_mrgn[7:0] = mrgn_ctl_reg[27:20] ;
 
assign  lsu_dtlb_mrgn[7:0] = mrgn_ctl_reg[19:12] ;
 
assign  lsu_dtlb_mrgn[7:0] = mrgn_ctl_reg[19:12] ;
 
assign  lsu_ictag_mrgn[3:0] = mrgn_ctl_reg[11:8] ;
 
assign  lsu_ictag_mrgn[3:0] = mrgn_ctl_reg[11:8] ;
 
assign  lsu_dctag_mrgn[3:0] = mrgn_ctl_reg[7:4] ;
 
assign  lsu_dctag_mrgn[3:0] = mrgn_ctl_reg[7:4] ;
Line 1450... Line 1455... 
 
 
 
 
assign  ldiagctl_data_in[1:0] = {2{rst_l}} & st_rs3_data_g[1:0] ;
 
assign  ldiagctl_data_in[1:0] = {2{rst_l}} & st_rs3_data_g[1:0] ;
 
 
 
 
 
   wire ldiagctl_clk;
 
   wire ldiagctl_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf ldiagctl_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~ldiagctl_wr_en),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (ldiagctl_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(2) ldiagctl_ff (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(2) ldiagctl_ff (
 
 
 
        .din    (ldiagctl_data_in[1:0]),
 
        .din    (ldiagctl_data_in[1:0]),
 
        .q      (ldiag_ctl_reg[1:0]),
 
        .q      (ldiag_ctl_reg[1:0]),
 
        .en (~(~ldiagctl_wr_en)), .clk(clk),
 
        .en (~(~ldiagctl_wr_en)), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(2) ldiagctl_ff (
 
 
 
        .din    (ldiagctl_data_in[1:0]),
 
 
 
        .q      (ldiag_ctl_reg[1:0]),
 
 
 
        .clk    (ldiagctl_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
assign  lsu_ifu_direct_map_l1 = ldiag_ctl_reg[0] ;
 
assign  lsu_ifu_direct_map_l1 = ldiag_ctl_reg[0] ;
 
assign  dc_direct_map = ldiag_ctl_reg[1] ;
 
assign  dc_direct_map = ldiag_ctl_reg[1] ;
 
 
 
 
 
   wire [43:0] misc_ctl_reg;
 
   wire [43:0] misc_ctl_reg;
 
 
 
 
 
   wire [3:0] misc_ctl_sel_q;
 
   wire [3:0] misc_ctl_sel_q;
 
 
 
 
 
dff #(4) misc_ctl_sel_stgg (
 
dff_s #(4) misc_ctl_sel_stgg (
 
    .din ( misc_ctl_sel_din[3:0] ),
 
    .din ( misc_ctl_sel_din[3:0] ),
 
    .q   ( misc_ctl_sel_q[3:0]   ),
 
    .q   ( misc_ctl_sel_q[3:0]   ),
 
    .clk (clk),
 
    .clk (clk),
 
    .se  (se),       .si (),          .so ()
 
    .se  (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
);
 
);
 
   wire [3:0] misc_ctl_sel;
 
   wire [3:0] misc_ctl_sel;
 
 
 
 
 
   assign     misc_ctl_sel[0] =  misc_ctl_sel_q [0] & ~rst_tri_en;
 
   assign     misc_ctl_sel[0] =  misc_ctl_sel_q [0] & ~rst_tri_en;
 
   assign     misc_ctl_sel[1] =  misc_ctl_sel_q [1] & ~rst_tri_en;
 
   assign     misc_ctl_sel[1] =  misc_ctl_sel_q [1] & ~rst_tri_en;
Line 1558... Line 1563... 
assign        lsu_local_ldxa_data_g[47:0] =  final_ldxa_data_g[47:0];
 
assign        lsu_local_ldxa_data_g[47:0] =  final_ldxa_data_g[47:0];
 
 
 
 
 
 
 
 
 
/****************va staging*******************/
 
/****************va staging*******************/
 
 wire [47:0] ldst_va_m;
 
 wire [47:0] ldst_va_m;
 
dff  #(48) va_stgm (
 
dff_s  #(48) va_stgm (
 
        .din    (exu_lsu_ldst_va_e[47:0]),
 
        .din    (exu_lsu_ldst_va_e[47:0]),
 
        .q      (ldst_va_m[47:0]),
 
        .q      (ldst_va_m[47:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
assign lsu_ldst_va_m[12:0] = ldst_va_m[12:0];
 
assign lsu_ldst_va_m[12:0] = ldst_va_m[12:0];
 
 
 
 
 
assign lsu_ldst_va_m_buf[47:0] = ldst_va_m[47:0];
 
assign lsu_ldst_va_m_buf[47:0] = ldst_va_m[47:0];
 
 
 
 
 
 
 
 
 
assign lsu_tlu_ldst_va_m[9:0] = ldst_va_m[9:0];
 
assign lsu_tlu_ldst_va_m[9:0] = ldst_va_m[9:0];
 
 
 
 
 
wire [47:0] ldst_va_g;
 
wire [47:0] ldst_va_g;
 
dff  #(48) va_stgg (
 
dff_s  #(48) va_stgg (
 
        .din    (ldst_va_m[47:0]),
 
        .din    (ldst_va_m[47:0]),
 
        .q      (ldst_va_g[47:0]),
 
        .q      (ldst_va_g[47:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
assign  lsu_ldst_va_g[7:0] = ldst_va_g[7:0] ;
 
assign  lsu_ldst_va_g[7:0] = ldst_va_g[7:0] ;
 
 
 
 
 
 
 
 
Line 1594... Line 1599... 
// Thread 0
 
// Thread 0
 
   wire [47:0] ldst_va0;
 
   wire [47:0] ldst_va0;
 
 
 
 
 
   wire        tlb_access0_clk;
 
   wire        tlb_access0_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf tlb_access0_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~tlb_access_en0_g),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (tlb_access0_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(56)  asi_thrd0 (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(56)  asi_thrd0 (
 
 
 
        .din    ({asi_state_g[7:0],   ldst_va_g[47:0]}),
 
        .din    ({asi_state_g[7:0],   ldst_va_g[47:0]}),
 
        .q      ({tlb_asi_state0[7:0],ldst_va0[47:0]}),
 
        .q      ({tlb_asi_state0[7:0],ldst_va0[47:0]}),
 
        .en (~(~tlb_access_en0_g)), .clk(clk),
 
        .en (~(~tlb_access_en0_g)), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(56)  asi_thrd0 (
 
 
 
        .din    ({asi_state_g[7:0],   ldst_va_g[47:0]}),
 
 
 
        .q      ({tlb_asi_state0[7:0],ldst_va0[47:0]}),
 
 
 
        .clk    (tlb_access0_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
// Thread 1
 
// Thread 1
 
   wire [47:0] ldst_va1;
 
   wire [47:0] ldst_va1;
 
 
 
 
 
   wire        tlb_access1_clk;
 
   wire        tlb_access1_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf tlb_access1_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~tlb_access_en1_g),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (tlb_access1_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(56)  asi_thrd1 (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(56)  asi_thrd1 (
 
 
 
        .din    ({asi_state_g[7:0],   ldst_va_g[47:0]}),
 
        .din    ({asi_state_g[7:0],   ldst_va_g[47:0]}),
 
        .q      ({tlb_asi_state1[7:0],ldst_va1[47:0]}),
 
        .q      ({tlb_asi_state1[7:0],ldst_va1[47:0]}),
 
        .en (~(~tlb_access_en1_g)), .clk(clk),
 
        .en (~(~tlb_access_en1_g)), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(56)  asi_thrd1 (
 
 
 
        .din    ({asi_state_g[7:0],   ldst_va_g[47:0]}),
 
 
 
        .q      ({tlb_asi_state1[7:0],ldst_va1[47:0]}),
 
 
 
        .clk    (tlb_access1_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
// Thread 2
 
// Thread 2
 
   wire [47:0] ldst_va2;
 
   wire [47:0] ldst_va2;
 
 
 
 
 
   wire        tlb_access2_clk;
 
   wire        tlb_access2_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf tlb_access2_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~tlb_access_en2_g),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (tlb_access2_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(56)  asi_thrd2 (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(56)  asi_thrd2 (
 
 
 
        .din    ({asi_state_g[7:0],   ldst_va_g[47:0]}),
 
        .din    ({asi_state_g[7:0],   ldst_va_g[47:0]}),
 
        .q      ({tlb_asi_state2[7:0],ldst_va2[47:0]}),
 
        .q      ({tlb_asi_state2[7:0],ldst_va2[47:0]}),
 
        .en (~(~tlb_access_en2_g)), .clk(clk),
 
        .en (~(~tlb_access_en2_g)), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(56)  asi_thrd2 (
 
 
 
        .din    ({asi_state_g[7:0],   ldst_va_g[47:0]}),
 
 
 
        .q      ({tlb_asi_state2[7:0],ldst_va2[47:0]}),
 
 
 
        .clk    (tlb_access2_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
// Thread 3
 
// Thread 3
 
   wire [47:0] ldst_va3;
 
   wire [47:0] ldst_va3;
 
 
 
 
 
   wire        tlb_access3_clk;
 
   wire        tlb_access3_clk;
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf tlb_access3_clkbuf (
 
 
 
                .rclk   (clk),
 
 
 
                .enb_l  (~tlb_access_en3_g),
 
 
 
                .tmb_l  (~se),
 
 
 
                .clk    (tlb_access3_clk)
 
 
 
                ) ;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s #(56)  asi_thrd3 (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe #(56)  asi_thrd3 (
 
 
 
        .din    ({asi_state_g[7:0],   ldst_va_g[47:0]}),
 
        .din    ({asi_state_g[7:0],   ldst_va_g[47:0]}),
 
        .q      ({tlb_asi_state3[7:0],ldst_va3[47:0]}),
 
        .q      ({tlb_asi_state3[7:0],ldst_va3[47:0]}),
 
        .en (~(~tlb_access_en3_g)), .clk(clk),
 
        .en (~(~tlb_access_en3_g)), .clk(clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
`else
 
 
 
dff_s #(56)  asi_thrd3 (
 
 
 
        .din    ({asi_state_g[7:0],   ldst_va_g[47:0]}),
 
 
 
        .q      ({tlb_asi_state3[7:0],ldst_va3[47:0]}),
 
 
 
        .clk    (tlb_access3_clk),
 
 
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
 
 
        );
 
 
 
`endif
 
 
 
 
 
   wire [47:0] ldst_va_dout;
 
   wire [47:0] ldst_va_dout;
 
 
 
 
 
mux4ds #(56)     ldst_va_mx (
 
mux4ds #(56)     ldst_va_mx (
 
        .in0    ({tlb_asi_state0[7:0],ldst_va0[47:0]}),
 
        .in0    ({tlb_asi_state0[7:0],ldst_va0[47:0]}),
Line 1745... Line 1750... 
 
 
 
 
//dff #(4)  diagsel_stgd1 (
 
//dff #(4)  diagsel_stgd1 (
 
//        .din    (lsu_diag_access_sel[3:0]),
 
//        .din    (lsu_diag_access_sel[3:0]),
 
//        .q      (lsu_diag_access_sel_d1[3:0]),
 
//        .q      (lsu_diag_access_sel_d1[3:0]),
 
//        .clk    (clk),
 
//        .clk    (clk),
 
//        .se     (se),       .si (),          .so ()
 
//        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
//        ); 
//        ); 
  wire [3:0] diagnstc_va_sel;
 
  wire [3:0] diagnstc_va_sel;
 
//change buffer to nand / nor 
//change buffer to nand / nor 
assign     diagnstc_va_sel[0] =   lsu_diagnstc_va_sel[0] & ~rst_tri_en;
 
assign     diagnstc_va_sel[0] =   lsu_diagnstc_va_sel[0] & ~rst_tri_en;
 
assign     diagnstc_va_sel[1] =   lsu_diagnstc_va_sel[1] & ~rst_tri_en;
 
assign     diagnstc_va_sel[1] =   lsu_diagnstc_va_sel[1] & ~rst_tri_en;
Line 1785... Line 1790... 
assign  lsu_diag_va_prty_invrt = diag_va[13] ;
 
assign  lsu_diag_va_prty_invrt = diag_va[13] ;
 
 
 
 
 
/***************error addr***************/
 
/***************error addr***************/
 
wire  [10:4] dcfill_addr_m,dcfill_addr_g ;
 
wire  [10:4] dcfill_addr_m,dcfill_addr_g ;
 
 
 
 
 
dff #(7)  filla_stgm (
 
dff_s #(7)  filla_stgm (
 
        .din    (lsu_dcfill_addr_e[10:4]),
 
        .din    (lsu_dcfill_addr_e[10:4]),
 
        .q      (dcfill_addr_m[10:4]),
 
        .q      (dcfill_addr_m[10:4]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
dff #(7)  filla_stgg (
 
dff_s #(7)  filla_stgg (
 
        .din    (dcfill_addr_m[10:4]),
 
        .din    (dcfill_addr_m[10:4]),
 
        .q      (dcfill_addr_g[10:4]),
 
        .q      (dcfill_addr_g[10:4]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
wire  [28:0]  error_pa_g ;
 
wire  [28:0]  error_pa_g ;
 
dff #(29)  epa_stgg (
 
dff_s #(29)  epa_stgg (
 
        .din    (lsu_error_pa_m[28:0]),
 
        .din    (lsu_error_pa_m[28:0]),
 
        .q      (error_pa_g[28:0]),
 
        .q      (error_pa_g[28:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
wire  [47:4]  err_addr_g ;
 
wire  [47:4]  err_addr_g ;
 
 
 
 
 
mux3ds #(44)     erra_mx (
 
mux3ds #(44)     erra_mx (
Line 1824... Line 1829... 
/*assign  err_addr_g[47:4] =
 
/*assign  err_addr_g[47:4] =
 
  sync_error_sel ?  ldst_va_g[47:4] :
 
  sync_error_sel ?  ldst_va_g[47:4] :
 
        async_error_sel ? {38'd0,async_tlb_index[5:0]} :
 
        async_error_sel ? {38'd0,async_tlb_index[5:0]} :
 
                        {8'd0,error_pa_g[28:0],dcfill_addr_g[10:4]} ;*/
 
                        {8'd0,error_pa_g[28:0],dcfill_addr_g[10:4]} ;*/
 
 
 
 
 
dff #(44)  errad_stgg (
 
dff_s #(44)  errad_stgg (
 
        .din    (err_addr_g[47:4]),
 
        .din    (err_addr_g[47:4]),
 
        .q      (lsu_ifu_err_addr[47:4]),
 
        .q      (lsu_ifu_err_addr[47:4]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
endmodule // lsu_dctldp
 
endmodule // lsu_dctldp
 
 
 
 
 
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