Subversion Repositories s1_core

// You should have received a copy of the GNU General Public

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// 

// ========== Copyright Header End ============================================

// ========== Copyright Header End ============================================

/////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////

module lsu_excpctl ( /*AUTOARG*/

module lsu_excpctl ( /*AUTOARG*/

   // Outputs

   // Outputs

   so, lsu_exu_st_dtlb_perr_g, lsu_ffu_st_dtlb_perr_g,

   so, lsu_exu_st_dtlb_perr_g, lsu_ffu_st_dtlb_perr_g,

   lsu_defr_trp_taken_g, lsu_tlu_defr_trp_taken_g,

   lsu_defr_trp_taken_g, lsu_tlu_defr_trp_taken_g,

wire    priv_pg_usr_mode_m, priv_pg_usr_mode_g, priv_pg_usr_mode;

wire    priv_pg_usr_mode_m, priv_pg_usr_mode_g, priv_pg_usr_mode;

wire    nfo_pg_nonnfo_asi_m, nfo_pg_nonnfo_asi_g, nfo_pg_nonnfo_asi;

wire    nfo_pg_nonnfo_asi_m, nfo_pg_nonnfo_asi_g, nfo_pg_nonnfo_asi;

wire    spec_access_epage_m, spec_access_epage_g, spec_access_epage ;

wire    spec_access_epage_m, spec_access_epage_g, spec_access_epage ;

wire    nonwr_pg_st_access;

wire    nonwr_pg_st_access;

//=========================================================================================

//=========================================================================================

// MISCELLANEOUS

// MISCELLANEOUS

//=========================================================================================

//=========================================================================================

   wire       clk;

   wire       clk;

   wire       dbb_reset_l;

   wire       dbb_reset_l;

    dffrl_async rstff(.din (grst_l),

    dffrl_async rstff(.din (grst_l),

                        .q   (dbb_reset_l),

                        .q   (dbb_reset_l),

                        .rst_l (arst_l));

                        .rst_l (arst_l));

   assign reset = ~dbb_reset_l ;

   assign reset = ~dbb_reset_l ;

bw_u1_buf_30x UZsize_stb_cam_hit_bf1  (.a(stb_cam_hit),   .z(stb_cam_hit_bf1));  //to dctl, stb_rwctl

bw_u1_buf_30x UZsize_stb_cam_hit_bf1  (.a(stb_cam_hit),   .z(stb_cam_hit_bf1));  //to dctl, stb_rwctl

bw_u1_buf_30x UZsize_stb_cam_hit_bf   (.a(stb_cam_hit),   .z(stb_cam_hit_bf ));  //to qctl1

bw_u1_buf_30x UZsize_stb_cam_hit_bf   (.a(stb_cam_hit),   .z(stb_cam_hit_bf ));  //to qctl1

wire                ld_inst_vld_m;

wire                ld_inst_vld_m;

wire                st_inst_vld_m;

wire                st_inst_vld_m;

   .din ({ld_inst_vld_e, st_inst_vld_e}),

   .din ({ld_inst_vld_e, st_inst_vld_e}),

   .q   ({ld_inst_vld_m, st_inst_vld_m}),

   .q   ({ld_inst_vld_m, st_inst_vld_m}),

   .clk    (clk),

   .clk    (clk),

);

);

   .din ({ld_inst_vld_m, st_inst_vld_m}),

   .din ({ld_inst_vld_m, st_inst_vld_m}),

   .q   ({ld_inst_vld_unflushed, st_inst_vld_unflushed}),

   .q   ({ld_inst_vld_unflushed, st_inst_vld_unflushed}),

   .clk    (clk),

   .clk    (clk),

);

);

wire    tlu_priv_trap_g ;

wire    tlu_priv_trap_g ;

   .din (tlu_lsu_priv_trap_m),

   .din (tlu_lsu_priv_trap_m),

   .q   (tlu_priv_trap_g),

   .q   (tlu_priv_trap_g),

   .clk    (clk),

   .clk    (clk),

);

);

//=========================================================================================

//=========================================================================================

//  Thread Staging

//  Thread Staging

//=========================================================================================

//=========================================================================================

wire [1:0] thrid_m, thrid_g ;

wire [1:0] thrid_m, thrid_g ;

        .din    (ifu_tlu_thrid_e[1:0]),

        .din    (ifu_tlu_thrid_e[1:0]),

        .q      (thrid_m[1:0]),

        .q      (thrid_m[1:0]),

        .clk    (clk),

        .clk    (clk),

        );

        );

wire    thread0_m, thread1_m, thread2_m, thread3_m;

wire    thread0_m, thread1_m, thread2_m, thread3_m;

assign  thread0_m = ~thrid_m[1] & ~thrid_m[0] ;

assign  thread0_m = ~thrid_m[1] & ~thrid_m[0] ;

assign  thread1_m = ~thrid_m[1] &  thrid_m[0] ;

assign  thread1_m = ~thrid_m[1] &  thrid_m[0] ;

assign  thread2_m =  thrid_m[1] & ~thrid_m[0] ;

assign  thread2_m =  thrid_m[1] & ~thrid_m[0] ;

assign  thread3_m =  thrid_m[1] &  thrid_m[0] ;

assign  thread3_m =  thrid_m[1] &  thrid_m[0] ;

wire thread0_g, thread1_g, thread2_g, thread3_g ;

wire thread0_g, thread1_g, thread2_g, thread3_g ;

        .din    ({thread0_m, thread1_m, thread2_m, thread3_m}),

        .din    ({thread0_m, thread1_m, thread2_m, thread3_m}),

        .q      ({thread0_g, thread1_g, thread2_g, thread3_g}),

        .q      ({thread0_g, thread1_g, thread2_g, thread3_g}),

        .clk    (clk),

        .clk    (clk),

        );

        );

//=========================================================================================

//=========================================================================================

//  INST_VLD_W GENERATION

//  INST_VLD_W GENERATION

//=========================================================================================

//=========================================================================================

wire    lsu_flush_pipe_w;

wire    lsu_flush_pipe_w;

assign  flush_w_inst_vld_m =

assign  flush_w_inst_vld_m =

        ifu_tlu_inst_vld_m &

        ifu_tlu_inst_vld_m &

        ~(lsu_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w

        ~(lsu_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w

        .din    (flush_w_inst_vld_m),

        .din    (flush_w_inst_vld_m),

        .q      (lsu_inst_vld_w),

        .q      (lsu_inst_vld_w),

        .clk    (clk),

        .clk    (clk),

        );

        );

//========================================================================

//========================================================================

//      Miscellaneous

//      Miscellaneous

//========================================================================

//========================================================================

   wire pstate_am_m ;

   wire pstate_am_m ;

assign lsu_va_match_m = ((lsu_va_match_b47_b32_m & lsu_va_match_b31_b3_m) & ~pstate_am_m) |

assign lsu_va_match_m = ((lsu_va_match_b47_b32_m & lsu_va_match_b31_b3_m) & ~pstate_am_m) |

                          (lsu_va_match_b31_b3_m & pstate_am_m);

                          (lsu_va_match_b31_b3_m & pstate_am_m);

        .din    ({va_wtchpt_en_m,

        .din    ({va_wtchpt_en_m,

                  lsu_va_match_m,

                  lsu_va_match_m,

                  va_wtchpt_msk_match_m}),

                  va_wtchpt_msk_match_m}),

        .q      ({va_wtchpt_en_g,

        .q      ({va_wtchpt_en_g,

                  va_match_g,

                  va_match_g,

                  va_wtchpt_msk_match_g}),

                  va_wtchpt_msk_match_g}),

        .clk    (clk),

        .clk    (clk),

        );

        );

// These signals will eventually generate exceptions.

// These signals will eventually generate exceptions.

   wire va_wtchpt_match;

   wire va_wtchpt_match;

assign  tlb_daccess_excptn_e  =

assign  tlb_daccess_excptn_e  =

  ((rd_only_ltlb_asi_e &  st_inst_vld_e)  |

  ((rd_only_ltlb_asi_e &  st_inst_vld_e)  |

   (wr_only_ltlb_asi_e &  ld_inst_vld_e)) & ifu_lsu_alt_space_e   ;

   (wr_only_ltlb_asi_e &  ld_inst_vld_e)) & ifu_lsu_alt_space_e   ;

        .din    ({tlb_daccess_excptn_e}),

        .din    ({tlb_daccess_excptn_e}),

        .q      ({tlb_daccess_excptn_e_d1}),

        .q      ({tlb_daccess_excptn_e_d1}),

        .clk    (clk),

        .clk    (clk),

        );

        );

assign tlb_daccess_excptn_m = tlb_daccess_excptn_e_d1 | tlb_illgl_pgsz_m;

assign tlb_daccess_excptn_m = tlb_daccess_excptn_e_d1 | tlb_illgl_pgsz_m;

wire pstate_priv_m;

wire pstate_priv_m;

//dff #(1)  priv_stgg (

//dff #(1)  priv_stgg (

//        .din    (pstate_priv_m),

//        .din    (pstate_priv_m),

//        .q      (pstate_priv),

//        .q      (pstate_priv),

//        .clk    (clk),

//        .clk    (clk),

//        );

//        );

// privilege violation - priv page accessed in user mode

// privilege violation - priv page accessed in user mode

//timing 

//timing 

//assign  priv_pg_usr_mode =  // data access exception; TT=h30

//assign  priv_pg_usr_mode =  // data access exception; TT=h30

//SC2   wire hpv_priv_m;

//SC2   wire hpv_priv_m;

   assign priv_pg_usr_mode_m = (ld_inst_vld_m | st_inst_vld_m) & ~(pstate_priv_m | hpv_priv_m);

   assign priv_pg_usr_mode_m = (ld_inst_vld_m | st_inst_vld_m) & ~(pstate_priv_m | hpv_priv_m);

        .din    (priv_pg_usr_mode_m),

        .din    (priv_pg_usr_mode_m),

        .q      (priv_pg_usr_mode_g),

        .q      (priv_pg_usr_mode_g),

        .clk    (clk),

        .clk    (clk),

        );

        );

   assign priv_pg_usr_mode = priv_pg_usr_mode_g & tlb_rd_tte_data_pbit ;

   assign priv_pg_usr_mode = priv_pg_usr_mode_g & tlb_rd_tte_data_pbit ;

// protection violation - store to a page that does not have write permission

// protection violation - store to a page that does not have write permission

//  & tlb_rd_tte_data_nfobit ;

//  & tlb_rd_tte_data_nfobit ;

assign nfo_pg_nonnfo_asi_m = (ld_inst_vld_m | st_inst_vld_m) &

assign nfo_pg_nonnfo_asi_m = (ld_inst_vld_m | st_inst_vld_m) &

                             ((~nofault_asi_m & lsu_alt_space_m) | ~lsu_alt_space_m) ;

                             ((~nofault_asi_m & lsu_alt_space_m) | ~lsu_alt_space_m) ;

        .din    (nfo_pg_nonnfo_asi_m),

        .din    (nfo_pg_nonnfo_asi_m),

        .q      (nfo_pg_nonnfo_asi_g),

        .q      (nfo_pg_nonnfo_asi_g),

        .clk    (clk),

        .clk    (clk),

        );

        );

assign    nfo_pg_nonnfo_asi = nfo_pg_nonnfo_asi_g & tlb_rd_tte_data_nfobit ;

assign    nfo_pg_nonnfo_asi = nfo_pg_nonnfo_asi_g & tlb_rd_tte_data_nfobit ;

// as_if_usr asi accesses priv page.

// as_if_usr asi accesses priv page.

//timing

//timing

//      tlb_rd_tte_data_pbit ;

//      tlb_rd_tte_data_pbit ;

   wire   as_if_usr_priv_pg_m, as_if_usr_priv_pg_g, as_if_usr_priv_pg;

   wire   as_if_usr_priv_pg_m, as_if_usr_priv_pg_g, as_if_usr_priv_pg;

   assign as_if_usr_priv_pg_m = (ld_inst_vld_m | st_inst_vld_m) & as_if_user_asi_m & lsu_alt_space_m;

   assign as_if_usr_priv_pg_m = (ld_inst_vld_m | st_inst_vld_m) & as_if_user_asi_m & lsu_alt_space_m;

        .din    (as_if_usr_priv_pg_m),

        .din    (as_if_usr_priv_pg_m),

        .q      (as_if_usr_priv_pg_g),

        .q      (as_if_usr_priv_pg_g),

        .clk    (clk),

        .clk    (clk),

        );

        );

   assign  as_if_usr_priv_pg =  as_if_usr_priv_pg_g & tlb_rd_tte_data_pbit ;

   assign  as_if_usr_priv_pg =  as_if_usr_priv_pg_g & tlb_rd_tte_data_pbit ;

// non-cacheable address - iospace PA[39] = 1 

// non-cacheable address - iospace PA[39] = 1 

// atomic access to non-cacheable space.

// atomic access to non-cacheable space.

   wire    atm_access_w_nc, atomic_g;

   wire    atm_access_w_nc, atomic_g;

        .din    (atomic_m),

        .din    (atomic_m),

        .q      (atomic_g),

        .q      (atomic_g),

        .clk    (clk),

        .clk    (clk),

        );

        );

assign  atm_access_w_nc = atomic_g & tlb_pgnum_b39 ; // io space 

assign  atm_access_w_nc = atomic_g & tlb_pgnum_b39 ; // io space 

//assign  atm_access_unsup_asi = atomic_g & ~atomic_asi_g & lsu_alt_space_g ;

//assign  atm_access_unsup_asi = atomic_g & ~atomic_asi_g & lsu_alt_space_g ;

   wire atm_access_unsup_asi_m, atm_access_unsup_asi;

   wire atm_access_unsup_asi_m, atm_access_unsup_asi;

assign  atm_access_unsup_asi_m = atomic_m & ~atomic_asi_m & lsu_alt_space_m;

assign  atm_access_unsup_asi_m = atomic_m & ~atomic_asi_m & lsu_alt_space_m;

        .din    (atm_access_unsup_asi_m),

        .din    (atm_access_unsup_asi_m),

        .q      (atm_access_unsup_asi),

        .q      (atm_access_unsup_asi),

        .clk    (clk),

        .clk    (clk),

        );

        );

//timing

//timing

//assign  tlb_tte_vld_g = ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;

//assign  tlb_tte_vld_g = ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;

assign  tlb_tte_vld_m = ~dtlb_bypass_m & tlb_cam_hit &

assign  tlb_tte_vld_m = ~dtlb_bypass_m & tlb_cam_hit &

                        ~((unimp_asi_m | asi_internal_m | ~recognized_asi_m) &

                        ~((unimp_asi_m | asi_internal_m | ~recognized_asi_m) &