OpenCores

Line 16...

// You should have received a copy of the GNU General Public

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

//

//

// ========== Copyright Header End ============================================

// ========== Copyright Header End ============================================

`ifdef SIMPLY_RISC_TWEAKS

`define SIMPLY_RISC_SCANIN .si(0)

`else

`define SIMPLY_RISC_SCANIN .si()

`endif

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

/*

/*

//  Description:  LSU Queue Control for Sparc Core

//  Description:  LSU Queue Control for Sparc Core

//      - includes monitoring for pcx queues

//      - includes monitoring for pcx queues

//      - control for lsu datapath

//      - control for lsu datapath

Line 27...

Line 32...

//

//

*/

*/

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

// header file includes

// header file includes

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

// system level definition file which contains the /*

`include  "sys.h" // system level definition file which contains the

/* ========== Copyright Header Begin ==========================================

* OpenSPARC T1 Processor File: sys.h

* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

* The above named program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public

* License version 2 as published by the Free Software Foundation.

* The above named program is distributed in the hope that it will be

* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

* General Public License for more details.

* You should have received a copy of the GNU General Public

* License along with this work; if not, write to the Free Software

* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

* ========== Copyright Header End ============================================

*/

// -*- verilog -*-

////////////////////////////////////////////////////////////////////////

/*

//

// Description:         Global header file that contain definitions that

//                      are common/shared at the systme level

*/

////////////////////////////////////////////////////////////////////////

//

// Setting the time scale

// If the timescale changes, JP_TIMESCALE may also have to change.

`timescale      1ps/1ps

//

// JBUS clock

// =========

//

// Afara Link Defines

// ==================

// Reliable Link

// Afara Link Objects

// Afara Link Object Format - Reliable Link

// Afara Link Object Format - Congestion

// Afara Link Object Format - Acknowledge

// Afara Link Object Format - Request

// Afara Link Object Format - Message

// Acknowledge Types

// Request Types

// Afara Link Frame

//

// UCB Packet Type

// ===============

//

//

// UCB Data Packet Format

// ======================

//

// Size encoding for the UCB_SIZE_HI/LO field

// 000 - byte

// 001 - half-word

// 010 - word

// 011 - double-word

// 111 - quad-word

//

// UCB Interrupt Packet Format

// ===========================

//

//`define UCB_THR_HI             9      // (6) cpu/thread ID shared with

//`define UCB_THR_LO             4             data packet format

//`define UCB_PKT_HI             3      // (4) packet type shared with

//`define UCB_PKT_LO             0      //     data packet format

//

// FCRAM Bus Widths

// ================

//

//

// ENET clock periods

// ==================

//

//

// JBus Bridge defines

// =================

//

//

// PCI Device Address Configuration

// ================================

//

                  // time scale definition

                  // time scale definition

/*

`include  "iop.h"

/* ========== Copyright Header Begin ==========================================

* OpenSPARC T1 Processor File: iop.h

* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

* The above named program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public

* License version 2 as published by the Free Software Foundation.

* The above named program is distributed in the hope that it will be

* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

* General Public License for more details.

* You should have received a copy of the GNU General Public

* License along with this work; if not, write to the Free Software

* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

* ========== Copyright Header End ============================================

*/

//-*- verilog -*-

////////////////////////////////////////////////////////////////////////

/*

//

//  Description:        Global header file that contain definitions that

//                      are common/shared at the IOP chip level

*/

////////////////////////////////////////////////////////////////////////

// Address Map Defines

// ===================

// CMP space

// IOP space

                               //`define ENET_ING_CSR     8'h84

                               //`define ENET_EGR_CMD_CSR 8'h85

// L2 space

// More IOP space

//Cache Crossbar Width and Field Defines

//======================================

//bits 133:128 are shared by different fields

//for different packet types.

//End cache crossbar defines

// Number of COS supported by EECU

//

// BSC bus sizes

// =============

//

// General

// CTags

// reinstated temporarily

// CoS

// L2$ Bank

// L2$ Req

// L2$ Ack

// Enet Egress Command Unit

// Enet Egress Packet Unit

// This is cleaved in between Egress Datapath Ack's

// Enet Egress Datapath

// In-Order / Ordered Queue: EEPU

// Tag is: TLEN, SOF, EOF, QID = 15

// Nack + Tag Info + CTag

// ENET Ingress Queue Management Req

// ENET Ingress Queue Management Ack

// Enet Ingress Packet Unit

// ENET Ingress Packet Unit Ack

// In-Order / Ordered Queue: PCI

// Tag is: CTAG

// PCI-X Request

// PCI_X Acknowledge

//

// BSC array sizes

//================

//

// ECC syndrome bits per memory element

//

// BSC Port Definitions

// ====================

//

// Bits 7 to 4 of curr_port_id

// Number of ports of each type

// Bits needed to represent above

// How wide the linked list pointers are

// 60b for no payload (2CoS)

// 80b for payload (2CoS)

//`define BSC_OBJ_PTR   80

//`define BSC_HD1_HI    69

//`define BSC_HD1_LO    60

//`define BSC_TL1_HI    59

//`define BSC_TL1_LO    50

//`define BSC_CT1_HI    49

//`define BSC_CT1_LO    40

//`define BSC_HD0_HI    29

//`define BSC_HD0_LO    20

//`define BSC_TL0_HI    19

//`define BSC_TL0_LO    10

//`define BSC_CT0_HI     9

//`define BSC_CT0_LO     0

// I2C STATES in DRAMctl

//

// IOB defines

// ===========

//

//`define IOB_INT_STAT_WIDTH   32

//`define IOB_INT_STAT_HI      31

//`define IOB_INT_STAT_LO       0

// fixme - double check address mapping

// CREG in `IOB_INT_CSR space

// CREG in `IOB_MAN_CSR space

// Address map for TAP access of SPARC ASI

//

// CIOP UCB Bus Width

// ==================

//

//`define IOB_EECU_WIDTH       16  // ethernet egress command

//`define EECU_IOB_WIDTH       16

//`define IOB_NRAM_WIDTH       16  // NRAM (RLDRAM previously)

//`define NRAM_IOB_WIDTH        4

//`define IOB_ENET_ING_WIDTH   32  // ethernet ingress

//`define ENET_ING_IOB_WIDTH    8

//`define IOB_ENET_EGR_WIDTH    4  // ethernet egress

//`define ENET_EGR_IOB_WIDTH    4

//`define IOB_ENET_MAC_WIDTH    4  // ethernet MAC

//`define ENET_MAC_IOB_WIDTH    4

//`define IOB_BSC_WIDTH         4  // BSC

//`define BSC_IOB_WIDTH         4

//`define IOB_CLSP_WIDTH        4  // clk spine unit

//`define CLSP_IOB_WIDTH        4

//

// CIOP UCB Buf ID Type

// ====================

//

//

// Interrupt Device ID

// ===================

//

// Caution: DUMMY_DEV_ID has to be 9 bit wide

//          for fields to line up properly in the IOB.

//

// Soft Error related definitions

// ==============================

//

//

// CMP clock

// =========

//

//

// NRAM/IO Interface

// =================

//

//

// NRAM/ENET Interface

// ===================

//

//

// IO/FCRAM Interface

// ==================

//

//

// PCI Interface

// ==================

// Load/store size encodings

// -------------------------

// Size encoding

// 000 - byte

// 001 - half-word

// 010 - word

// 011 - double-word

// 100 - quad

//

// JBI<->SCTAG Interface

// =======================

// Outbound Header Format

// Inbound Header Format

//

// JBI->IOB Mondo Header Format

// ============================

//

// JBI->IOB Mondo Bus Width/Cycle

// ==============================

// Cycle  1 Header[15:8]

// Cycle  2 Header[ 7:0]

// Cycle  3 J_AD[127:120]

// Cycle  4 J_AD[119:112]

// .....

// Cycle 18 J_AD[  7:  0]

/*

/* ========== Copyright Header Begin ==========================================

* OpenSPARC T1 Processor File: lsu.h

* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

* The above named program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public

* License version 2 as published by the Free Software Foundation.

* The above named program is distributed in the hope that it will be

* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

* General Public License for more details.

* You should have received a copy of the GNU General Public

* License along with this work; if not, write to the Free Software

* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

* ========== Copyright Header End ============================================

*/

//`define STB_PCX_WY_HI   107

//`define STB_PCX_WY_LO   106

// TLB Tag and Data Format

// I-TLB version - lsu_tlb only.

// Invalidate Format

//addr<5:4>=00

//addr<5:4>=01

//addr<5:4>=10

//addr<5:4>=11

// cpuid - 4b

// CPUany, addr<5:4>=00,10

// CPUany, addr<5:4>=01,11

// CPUany, addr<5:4>=01,11

// DTAG parity error Invalidate

// CPX BINIT STORE

`include  "lsu.h"

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

// Local header file includes / local defines

// Local header file includes / local defines

////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////

Line 1543...

Line 132...

//input [`CPX_WIDTH-1:0] cpx_spc_data_cx ;       // cpx to processor packet

//input [`CPX_WIDTH-1:0] cpx_spc_data_cx ;       // cpx to processor packet

//input [17:0]            cpx_spc_data_b17t0_cx ; // cpx to processor packet

//input [17:0]            cpx_spc_data_b17t0_cx ; // cpx to processor packet

   input                lsu_dfq_rdata_flush_bit;

   input                lsu_dfq_rdata_flush_bit;

   input [17:0]         lsu_dfq_rdata_b17_b0;

   input [17:0]         lsu_dfq_rdata_b17_b0;

input [145-1:140] cpx_spc_data_cx_b144to140 ;       // vld, req type

input [`CPX_WIDTH-1:140] cpx_spc_data_cx_b144to140 ;       // vld, req type

input                   cpx_spc_data_cx_b138 ;

input                   cpx_spc_data_cx_b138 ;

//input                   cpx_spc_data_cx_b136 ;

//input                   cpx_spc_data_cx_b136 ;

input [135:134] cpx_spc_data_cx_b135to134 ;  // thread id

input [`CPX_TH_HI:`CPX_TH_LO] cpx_spc_data_cx_b135to134 ;  // thread id

input                   cpx_spc_data_cx_b133 ;

input                   cpx_spc_data_cx_b133 ;

input                   cpx_spc_data_cx_b130 ;

input                   cpx_spc_data_cx_b130 ;

input                   cpx_spc_data_cx_b129 ;

input                   cpx_spc_data_cx_b129 ;

input                   cpx_spc_data_cx_b128 ;

input                   cpx_spc_data_cx_b128 ;

input                   cpx_spc_data_cx_b125 ;

input                   cpx_spc_data_cx_b125 ;

input [123+1:123] cpx_spc_data_cx_b124to123 ;  // inv packet iinv,dinv

input [`CPX_PERR_DINV+1:`CPX_PERR_DINV] cpx_spc_data_cx_b124to123 ;  // inv packet iinv,dinv

input [120:118] cpx_spc_data_cx_b120to118 ;  // inv packet cpu id

input [`CPX_INV_CID_HI:`CPX_INV_CID_LO] cpx_spc_data_cx_b120to118 ;  // inv packet cpu id

input [1:0]             cpx_spc_data_cx_b71to70 ;

input [1:0]             cpx_spc_data_cx_b71to70 ;

input        cpx_spc_data_cx_b0 ;

input        cpx_spc_data_cx_b0 ;

input        cpx_spc_data_cx_b4 ;

input        cpx_spc_data_cx_b4 ;

input        cpx_spc_data_cx_b8 ;

input        cpx_spc_data_cx_b8 ;

Line 1825...

Line 414...

output                  lsu_dfq_byp_ff_en ;

output                  lsu_dfq_byp_ff_en ;

/*AUTOWIRE*/

/*AUTOWIRE*/

// Beginning of automatic wires (for undeclared instantiated-module outputs)

// Beginning of automatic wires (for undeclared instantiated-module outputs)

`ifdef SIMPLY_RISC_TWEAKS

wire dbb_reset_l;

wire clk;

wire fwd_reply_vld;

wire fwd_req_vld;

wire dcache_perror0;

wire dcache_perror1;

wire dcache_perror2;

wire dcache_perror3;

wire ldd_in_dfq_out_d1;

wire dfq_vld_entry_exists_d1;

`endif

// End of automatics

// End of automatics

wire        cpx_local_st_ack_type ;

wire        cpx_local_st_ack_type ;

wire  [3:0] cpx_pkt_thrd_sel ;

wire  [3:0] cpx_pkt_thrd_sel ;

Line 1910...

Line 511...

wire          dfq_rd_vld_d1 ;

wire          dfq_rd_vld_d1 ;

    dffrl_async rstff(.din (grst_l),

    dffrl_async rstff(.din (grst_l),

                        .q   (dbb_reset_l),

                        .q   (dbb_reset_l),

                        .clk (clk), .se(se), .si(), .so(),

                        .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so(),

                        .rst_l (arst_l));

                        .rst_l (arst_l));

assign  reset  =  ~dbb_reset_l;

assign  reset  =  ~dbb_reset_l;

assign  clk = rclk;

assign  clk = rclk;

Line 1925...

Line 526...

//dff #(2) mbist_stge (

//dff #(2) mbist_stge (

//   .din ({mbist_dcache_write, mbist_dcache_read}),

//   .din ({mbist_dcache_write, mbist_dcache_read}),

//   .q   ({lsu_bist_wvld_e,    lsu_bist_rvld_e  }),

//   .q   ({lsu_bist_wvld_e,    lsu_bist_rvld_e  }),

//   .clk (clk),

//   .clk (clk),

//   .se  (1'b0),       .si (),          .so ()

//   .se  (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

//);

//);

//=================================================================================================

//=================================================================================================

// SHADOW SCAN

// SHADOW SCAN

//=================================================================================================

//=================================================================================================

Line 1969...

Line 570...

assign  imiss0_inv_en = ifu_pcx_pkt_b51 & ~ifu_pcx_pkt_b41t40[1] & ~ifu_pcx_pkt_b41t40[0] & lsu_imiss_pcx_rq_sel_d1 ;

assign  imiss0_inv_en = ifu_pcx_pkt_b51 & ~ifu_pcx_pkt_b41t40[1] & ~ifu_pcx_pkt_b41t40[0] & lsu_imiss_pcx_rq_sel_d1 ;

assign  imiss1_inv_en = ifu_pcx_pkt_b51 & ~ifu_pcx_pkt_b41t40[1] &  ifu_pcx_pkt_b41t40[0] & lsu_imiss_pcx_rq_sel_d1 ;

assign  imiss1_inv_en = ifu_pcx_pkt_b51 & ~ifu_pcx_pkt_b41t40[1] &  ifu_pcx_pkt_b41t40[0] & lsu_imiss_pcx_rq_sel_d1 ;

assign  imiss2_inv_en = ifu_pcx_pkt_b51 &  ifu_pcx_pkt_b41t40[1] & ~ifu_pcx_pkt_b41t40[0] & lsu_imiss_pcx_rq_sel_d1 ;

assign  imiss2_inv_en = ifu_pcx_pkt_b51 &  ifu_pcx_pkt_b41t40[1] & ~ifu_pcx_pkt_b41t40[0] & lsu_imiss_pcx_rq_sel_d1 ;

assign  imiss3_inv_en = ifu_pcx_pkt_b51 &  ifu_pcx_pkt_b41t40[1] &  ifu_pcx_pkt_b41t40[0] & lsu_imiss_pcx_rq_sel_d1 ;

assign  imiss3_inv_en = ifu_pcx_pkt_b51 &  ifu_pcx_pkt_b41t40[1] &  ifu_pcx_pkt_b41t40[0] & lsu_imiss_pcx_rq_sel_d1 ;

dffe #(6) imiss_inv0 (

dffe_s #(6) imiss_inv0 (

        .din    ({ifu_pcx_pkt_b10t5[5:0]}),

        .din    ({ifu_pcx_pkt_b10t5[5:0]}),

        .q      ({imiss0_set_index[10:5]}),

        .q      ({imiss0_set_index[10:5]}),

        .en (imiss0_inv_en),

        .en (imiss0_inv_en),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dffe #(6) imiss_inv1 (

dffe_s #(6) imiss_inv1 (

        .din    ({ifu_pcx_pkt_b10t5[5:0]}),

        .din    ({ifu_pcx_pkt_b10t5[5:0]}),

        .q      ({imiss1_set_index[10:5]}),

        .q      ({imiss1_set_index[10:5]}),

        .en (imiss1_inv_en),

        .en (imiss1_inv_en),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dffe #(6) imiss_inv2 (

dffe_s #(6) imiss_inv2 (

        .din    ({ifu_pcx_pkt_b10t5[5:0]}),

        .din    ({ifu_pcx_pkt_b10t5[5:0]}),

        .q      ({imiss2_set_index[10:5]}),

        .q      ({imiss2_set_index[10:5]}),

        .en (imiss2_inv_en),

        .en (imiss2_inv_en),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dffe #(6) imiss_inv3 (

dffe_s #(6) imiss_inv3 (

        .din    ({ifu_pcx_pkt_b10t5[5:0]}),

        .din    ({ifu_pcx_pkt_b10t5[5:0]}),

        .q      ({imiss3_set_index[10:5]}),

        .q      ({imiss3_set_index[10:5]}),

        .en (imiss3_inv_en),

        .en (imiss3_inv_en),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  cpx_pkt_thrd_sel[0] = ~lsu_cpx_pkt_tid[1] & ~lsu_cpx_pkt_tid[0] ;

assign  cpx_pkt_thrd_sel[0] = ~lsu_cpx_pkt_tid[1] & ~lsu_cpx_pkt_tid[0] ;

assign  cpx_pkt_thrd_sel[1] = ~lsu_cpx_pkt_tid[1] &  lsu_cpx_pkt_tid[0] ;

assign  cpx_pkt_thrd_sel[1] = ~lsu_cpx_pkt_tid[1] &  lsu_cpx_pkt_tid[0] ;

assign  cpx_pkt_thrd_sel[2] =  lsu_cpx_pkt_tid[1] & ~lsu_cpx_pkt_tid[0] ;

assign  cpx_pkt_thrd_sel[2] =  lsu_cpx_pkt_tid[1] & ~lsu_cpx_pkt_tid[0] ;

Line 2044...

Line 645...

assign  lsu_iobrdge_rply_data_sel[2] = ~|lsu_iobrdge_rply_data_sel[1:0] ;

assign  lsu_iobrdge_rply_data_sel[2] = ~|lsu_iobrdge_rply_data_sel[1:0] ;

wire dcache_iob_rd,dcache_iob_rd_e, dcache_iob_rd_m, dcache_iob_rd_w ;

wire dcache_iob_rd,dcache_iob_rd_e, dcache_iob_rd_m, dcache_iob_rd_w ;

assign  dcache_iob_rd = lsu_iobrdge_tap_rq_type[6] & lsu_iobrdge_fwd_pkt_vld ;

assign  dcache_iob_rd = lsu_iobrdge_tap_rq_type[6] & lsu_iobrdge_fwd_pkt_vld ;

dff  dciob_rd_e (

dff_s  dciob_rd_e (

        .din    (dcache_iob_rd),

        .din    (dcache_iob_rd),

        .q      (dcache_iob_rd_e),

        .q      (dcache_iob_rd_e),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dff  dciob_rd_m (

dff_s  dciob_rd_m (

        .din    (dcache_iob_rd_e),

        .din    (dcache_iob_rd_e),

        .q      (dcache_iob_rd_m),

        .q      (dcache_iob_rd_m),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dff  dciob_rd_w (

dff_s  dciob_rd_w (

        .din    (dcache_iob_rd_m),

        .din    (dcache_iob_rd_m),

        .q      (dcache_iob_rd_w),

        .q      (dcache_iob_rd_w),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  lsu_dcache_iob_rd_w = dcache_iob_rd_w ;

assign  lsu_dcache_iob_rd_w = dcache_iob_rd_w ;

wire  cpx_fwd_rq_type ;

wire  cpx_fwd_rq_type ;

assign  cpx_fwd_rq_type =

assign  cpx_fwd_rq_type =

        cpx_spc_data_cx_b144to140[143]   & ~cpx_spc_data_cx_b144to140[140+2] & // fwd req

        cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // fwd req

        cpx_spc_data_cx_b144to140[140+1] & ~cpx_spc_data_cx_b144to140[140];

        cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO];

wire  cpx_fwd_rply_type ;

wire  cpx_fwd_rply_type ;

assign  cpx_fwd_rply_type =

assign  cpx_fwd_rply_type =

        cpx_spc_data_cx_b144to140[143]   & ~cpx_spc_data_cx_b144to140[140+2] & // fwd reply

        cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // fwd reply

        cpx_spc_data_cx_b144to140[140+1] &  cpx_spc_data_cx_b144to140[140] ;

        cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO] ;

// cpx pkt decode. fwd req/reply do not go into dfq.

// cpx pkt decode. fwd req/reply do not go into dfq.

assign  cpx_fwd_req =

assign  cpx_fwd_req =

         cpx_spc_data_cx_b144to140[144] & ~cpx_reverse_req & cpx_fwd_rq_type ;

         cpx_spc_data_cx_b144to140[`CPX_VLD] & ~cpx_reverse_req & cpx_fwd_rq_type ;

//8/25/03: add fwd req to L1I$ for RAMTEST to dfq_wr_en, dfq_rd_dvance

//8/25/03: add fwd req to L1I$ for RAMTEST to dfq_wr_en, dfq_rd_dvance

//bug4293 - set fwd_req_ic based on cpx_fwd_req_type and not based on cpx_fwd_req. this causes the request to

//bug4293 - set fwd_req_ic based on cpx_fwd_req_type and not based on cpx_fwd_req. this causes the request to

//          de dropped i.e. not written into dfq 'cos cpx_fwd_req_ic is not set

//          de dropped i.e. not written into dfq 'cos cpx_fwd_req_ic is not set

//assign  cpx_fwd_req_ic =  cpx_fwd_req & cpx_spc_data_cx_b103 ;

//assign  cpx_fwd_req_ic =  cpx_fwd_req & cpx_spc_data_cx_b103 ;

assign  cpx_fwd_req_ic =  cpx_spc_data_cx_b144to140[144] & cpx_fwd_rq_type &

assign  cpx_fwd_req_ic =  cpx_spc_data_cx_b144to140[`CPX_VLD] & cpx_fwd_rq_type &

                          cpx_reverse_req & cpx_spc_data_cx_b103 ;

                          cpx_reverse_req & cpx_spc_data_cx_b103 ;

assign  cpx_fwd_pkt_en_cx = cpx_fwd_req | cpx_fwd_reply ;

assign  cpx_fwd_pkt_en_cx = cpx_fwd_req | cpx_fwd_reply ;

assign  cpx_fwd_reply =

assign  cpx_fwd_reply =

         cpx_spc_data_cx_b144to140[144] & (cpx_fwd_rply_type | (cpx_fwd_rq_type & cpx_reverse_req)) ;

         cpx_spc_data_cx_b144to140[`CPX_VLD] & (cpx_fwd_rply_type | (cpx_fwd_rq_type & cpx_reverse_req)) ;

dff #(1) fwdpkt_stgd1 (

dff_s #(1) fwdpkt_stgd1 (

        .din    (fwd_reply_vld),

        .din    (fwd_reply_vld),

        .q      (lsu_pcx_fwd_reply),

        .q      (lsu_pcx_fwd_reply),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Requests from iobrdge will not be speculative as core is expected to be quiescent.

// Requests from iobrdge will not be speculative as core is expected to be quiescent.

assign  fwdpkt_reset =

assign  fwdpkt_reset =

  (reset | lsu_fwdpkt_pcx_rq_sel) ;

  (reset | lsu_fwdpkt_pcx_rq_sel) ;

  // (reset | (lsu_fwdpkt_pcx_rq_sel & ~pcx_req_squash)) ;

  // (reset | (lsu_fwdpkt_pcx_rq_sel & ~pcx_req_squash)) ;

wire    fwdpkt_vld_unmasked,fwdpkt_vld_unmasked_d1 ;

wire    fwdpkt_vld_unmasked,fwdpkt_vld_unmasked_d1 ;

wire    fwd_unc_err ;

wire    fwd_unc_err ;

// There can be only one outstanding fwd reply or request.

// There can be only one outstanding fwd reply or request.

dffre #(7)  fwdpkt_ff (

dffre_s #(7)  fwdpkt_ff (

        .din    ({cpx_fwd_pkt_en_cx,cpx_fwd_req,cpx_fwd_reply,

        .din    ({cpx_fwd_pkt_en_cx,cpx_fwd_req,cpx_fwd_reply,

                cpx_spc_data_cx_b138,cpx_spc_data_cx_b71to70[1:0], cpx_reverse_req}),

                cpx_spc_data_cx_b138,cpx_spc_data_cx_b71to70[1:0], cpx_reverse_req}),

        .q      ({fwdpkt_vld_unmasked,fwd_req_vld,fwd_reply_vld,

        .q      ({fwdpkt_vld_unmasked,fwd_req_vld,fwd_reply_vld,

                fwd_unc_err,fwdpkt_l2bnk_addr[1:0],cpx_reverse_req_d1}),

                fwd_unc_err,fwdpkt_l2bnk_addr[1:0],cpx_reverse_req_d1}),

  .rst  (fwdpkt_reset), .en (cpx_fwd_pkt_en_cx),

  .rst  (fwdpkt_reset), .en (cpx_fwd_pkt_en_cx),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire    fwd_rply_sz1_unc ; // Either size[1] for fwd-rq or unc-err for fwd-rply.

wire    fwd_rply_sz1_unc ; // Either size[1] for fwd-rq or unc-err for fwd-rply.

assign  fwd_rply_sz1_unc = fwd_reply_vld ? fwd_unc_err : 1'b1 ;

assign  fwd_rply_sz1_unc = fwd_reply_vld ? fwd_unc_err : 1'b1 ;

dff  fpktunc_d1 (

dff_s  fpktunc_d1 (

        .din    (fwd_rply_sz1_unc),

        .din    (fwd_rply_sz1_unc),

        .q      (lsu_fwd_rply_sz1_unc),

        .q      (lsu_fwd_rply_sz1_unc),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dff  fpktv_d1 (

dff_s  fpktv_d1 (

        .din    (fwdpkt_vld_unmasked),

        .din    (fwdpkt_vld_unmasked),

        .q      (fwdpkt_vld_unmasked_d1),

        .q      (fwdpkt_vld_unmasked_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire icache_rd_done,icache_wr_done ;

wire icache_rd_done,icache_wr_done ;

dff #(2) ifwd_d1 (

dff_s #(2) ifwd_d1 (

        .din    ({ifu_lsu_fwd_data_vld,ifu_lsu_fwd_wr_ack}),

        .din    ({ifu_lsu_fwd_data_vld,ifu_lsu_fwd_wr_ack}),

        .q      ({icache_rd_done,icache_wr_done}),

        .q      ({icache_rd_done,icache_wr_done}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// make one-shot : read data may be off.

// make one-shot : read data may be off.

assign  lsu_iobrdge_fwd_pkt_vld = fwdpkt_vld_unmasked & ~fwdpkt_vld_unmasked_d1 & cpx_reverse_req_d1 ;

assign  lsu_iobrdge_fwd_pkt_vld = fwdpkt_vld_unmasked & ~fwdpkt_vld_unmasked_d1 & cpx_reverse_req_d1 ;

//assign  lsu_iobrdge_fwd_pkt_vld = fwdpkt_vld ;

//assign  lsu_iobrdge_fwd_pkt_vld = fwdpkt_vld ;

Line 2185...

Line 786...

assign  lsu_tlu_cpx_req_din_l[3:0] = ~ lsu_dfq_rdata_rq_type[3:0];

assign  lsu_tlu_cpx_req_din_l[3:0] = ~ lsu_dfq_rdata_rq_type[3:0];

   wire lsu_tlu_cpx_vld_l;

   wire lsu_tlu_cpx_vld_l;

   wire [3:0] lsu_tlu_cpx_req_l;

   wire [3:0] lsu_tlu_cpx_req_l;

dff  #(23) lsu_tlu_stg (

dff_s  #(23) lsu_tlu_stg (

        .din    ({lsu_tlu_cpx_vld_din_l, lsu_tlu_intpkt_din[17:0], lsu_tlu_cpx_req_din_l[3:0]}),

        .din    ({lsu_tlu_cpx_vld_din_l, lsu_tlu_intpkt_din[17:0], lsu_tlu_cpx_req_din_l[3:0]}),

        .q      ({lsu_tlu_cpx_vld_l,     lsu_tlu_intpkt[17:0], lsu_tlu_cpx_req_l[3:0]}),

        .q      ({lsu_tlu_cpx_vld_l,     lsu_tlu_intpkt[17:0], lsu_tlu_cpx_req_l[3:0]}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

   assign     lsu_tlu_cpx_vld = ~lsu_tlu_cpx_vld_l;

   assign     lsu_tlu_cpx_vld = ~lsu_tlu_cpx_vld_l;

   assign     lsu_tlu_cpx_req[3:0] = ~lsu_tlu_cpx_req_l[3:0];

   assign     lsu_tlu_cpx_req[3:0] = ~lsu_tlu_cpx_req_l[3:0];

Line 2313...

Line 914...

//assign  lsu_error_rst[3:0]  =  error_rst[3:0];

//assign  lsu_error_rst[3:0]  =  error_rst[3:0];

wire    dtag_perror3,dtag_perror2,dtag_perror1,dtag_perror0;

wire    dtag_perror3,dtag_perror2,dtag_perror1,dtag_perror0;

// Thread 0

// Thread 0

dffre  #(2) error_t0 (

dffre_s  #(2) error_t0 (

        .din    ({lsu_dcache_tag_perror_g,lsu_dcache_data_perror_g}),

        .din    ({lsu_dcache_tag_perror_g,lsu_dcache_data_perror_g}),

    //lsu_cpx_pkt_ld_err[1:0]}),

    //lsu_cpx_pkt_ld_err[1:0]}),

        .q      ({dtag_perror0,dcache_perror0}),

        .q      ({dtag_perror0,dcache_perror0}),

        //.q      ({dtag_perror0,dcache_perror0,ld_error0[1:0]}),

        //.q      ({dtag_perror0,dcache_perror0,ld_error0[1:0]}),

        .rst  (error_rst[0]), .en     (error_en[0]),

        .rst  (error_rst[0]), .en     (error_en[0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Thread 1

// Thread 1

dffre  #(2) error_t1 (

dffre_s  #(2) error_t1 (

        .din    ({lsu_dcache_tag_perror_g,lsu_dcache_data_perror_g}),

        .din    ({lsu_dcache_tag_perror_g,lsu_dcache_data_perror_g}),

    //lsu_cpx_pkt_ld_err[1:0]}),

    //lsu_cpx_pkt_ld_err[1:0]}),

        .q      ({dtag_perror1,dcache_perror1}),

        .q      ({dtag_perror1,dcache_perror1}),

        //.q      ({dtag_perror1,dcache_perror1,ld_error1[1:0]}),

        //.q      ({dtag_perror1,dcache_perror1,ld_error1[1:0]}),

        .rst  (error_rst[1]), .en     (error_en[1]),

        .rst  (error_rst[1]), .en     (error_en[1]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Thread 2

// Thread 2

dffre  #(2) error_t2 (

dffre_s  #(2) error_t2 (

        .din    ({lsu_dcache_tag_perror_g,lsu_dcache_data_perror_g}),

        .din    ({lsu_dcache_tag_perror_g,lsu_dcache_data_perror_g}),

    //lsu_cpx_pkt_ld_err[1:0]}),

    //lsu_cpx_pkt_ld_err[1:0]}),

        .q      ({dtag_perror2,dcache_perror2}),

        .q      ({dtag_perror2,dcache_perror2}),

        //.q      ({dtag_perror2,dcache_perror2,ld_error2[1:0]}),

        //.q      ({dtag_perror2,dcache_perror2,ld_error2[1:0]}),

        .rst  (error_rst[2]), .en     (error_en[2]),

        .rst  (error_rst[2]), .en     (error_en[2]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Thread 3

// Thread 3

dffre  #(2) error_t3 (

dffre_s  #(2) error_t3 (

        .din    ({lsu_dcache_tag_perror_g,lsu_dcache_data_perror_g}),

        .din    ({lsu_dcache_tag_perror_g,lsu_dcache_data_perror_g}),

    //lsu_cpx_pkt_ld_err[1:0]}),

    //lsu_cpx_pkt_ld_err[1:0]}),

        .q      ({dtag_perror3,dcache_perror3}),

        .q      ({dtag_perror3,dcache_perror3}),

        //.q      ({dtag_perror3,dcache_perror3,ld_error3[1:0]}),

        //.q      ({dtag_perror3,dcache_perror3,ld_error3[1:0]}),

        .rst  (error_rst[3]), .en     (error_en[3]),

        .rst  (error_rst[3]), .en     (error_en[3]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//assign        lsu_dtag_perror_w2[3] = dtag_perror3 ;

//assign        lsu_dtag_perror_w2[3] = dtag_perror3 ;

//assign        lsu_dtag_perror_w2[2] = dtag_perror2 ;

//assign        lsu_dtag_perror_w2[2] = dtag_perror2 ;

//assign        lsu_dtag_perror_w2[1] = dtag_perror1 ;

//assign        lsu_dtag_perror_w2[1] = dtag_perror1 ;

Line 2390...

Line 991...

      cpx_pkt_thrd_sel[2] ? ld_error2[1:0] : ld_error3[1:0] ;*/

      cpx_pkt_thrd_sel[2] ? ld_error2[1:0] : ld_error3[1:0] ;*/

//===

//===

wire memref_e;

wire memref_e;

dff #(1) stge_ad_e (

dff_s #(1) stge_ad_e (

  .din (ifu_lsu_memref_d),

  .din (ifu_lsu_memref_d),

  .q   (memref_e),

  .q   (memref_e),

  .clk (clk),

  .clk (clk),

  .se     (1'b0),       .si (),          .so ()

  .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

Line 2416...

Line 1017...

assign ldd_vld_en = lmq_ldd_vld & ~lsu_cpx_pkt_prefetch & dcfill_active_e ;

assign ldd_vld_en = lmq_ldd_vld & ~lsu_cpx_pkt_prefetch & dcfill_active_e ;

// fp

// fp

assign lsu_fldd_vld_en = lmq_ldd_vld & ~lsu_cpx_pkt_prefetch & lsu_l2fill_fpld_e & dcfill_active_e ;

assign lsu_fldd_vld_en = lmq_ldd_vld & ~lsu_cpx_pkt_prefetch & lsu_l2fill_fpld_e & dcfill_active_e ;

dffre   ldd_in_dfq_ff (

dffre_s   ldd_in_dfq_ff (

        .din    (lmq_ldd_vld), .q  (ldd_in_dfq_out),

        .din    (lmq_ldd_vld), .q  (ldd_in_dfq_out),

        .rst    (ldd_vld_reset),        .en     (ldd_vld_en),

        .rst    (ldd_vld_reset),        .en     (ldd_vld_en),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

wire lsu_ignore_fill;

wire lsu_ignore_fill;

//dfq_ld_vld is redundant

//dfq_ld_vld is redundant

assign lsu_ignore_fill = dfq_ld_vld & lmq_ldd_vld & ~ldd_in_dfq_out & dcfill_active_e ;

assign lsu_ignore_fill = dfq_ld_vld & lmq_ldd_vld & ~ldd_in_dfq_out & dcfill_active_e ;

dff #(5)   dfq_rd_m (

dff_s #(5)   dfq_rd_m (

        .din    (ifu_lsu_rd_e[4:0]), .q  (ld_l1hit_rd_m[4:0]),

        .din    (ifu_lsu_rd_e[4:0]), .q  (ld_l1hit_rd_m[4:0]),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//dff #(5)   dfq_rd_g (

//dff #(5)   dfq_rd_g (

//        .din    (ld_l1hit_rd_m[4:0]), .q  (ld_l1hit_rd_g[4:0]),

//        .din    (ld_l1hit_rd_m[4:0]), .q  (ld_l1hit_rd_g[4:0]),

//        .clk  (clk),

//        .clk  (clk),

//        .se     (1'b0),       .si (),          .so ()

//        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

//        );

//        );

dff #(1)   stgd1_lrd (

dff_s #(1)   stgd1_lrd (

        .din    (ldd_in_dfq_out),

        .din    (ldd_in_dfq_out),

  .q    (ldd_in_dfq_out_d1),

  .q    (ldd_in_dfq_out_d1),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//dff #(1)   stgd2_lrd (

//dff #(1)   stgd2_lrd (

//        .din    (ldd_in_dfq_out_d1),

//        .din    (ldd_in_dfq_out_d1),

//  .q    (ldd_in_dfq_out_d2),

//  .q    (ldd_in_dfq_out_d2),

//        .clk  (clk),

//        .clk  (clk),

//        .se     (1'b0),       .si (),          .so ()

//        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

//        );

//        );

//wire [4:0] lmq_ld_rd1_g;

//wire [4:0] lmq_ld_rd1_g;

//dff #(5) ff_lmq_ld_rd1 (

//dff #(5) ff_lmq_ld_rd1 (

//        .din  (lmq_ld_rd1[4:0]),

//        .din  (lmq_ld_rd1[4:0]),

//        .q    (lmq_ld_rd1_g[4:0]),

//        .q    (lmq_ld_rd1_g[4:0]),

//        .clk  (clk),

//        .clk  (clk),

//        .se   (1'b0),       .si (),          .so ()

//        .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

//        );

//        );

// Stage l2fill vld

// Stage l2fill vld

//wire  l2fill_vld_m, l2fill_vld_g ;

//wire  l2fill_vld_m, l2fill_vld_g ;

wire    l2fill_vld_e,l2fill_vld_m ;

wire    l2fill_vld_e,l2fill_vld_m ;

dff     l2fv_stgm (

dff_s           l2fv_stgm (

        .din  (l2fill_vld_e),

        .din  (l2fill_vld_e),

        .q    (l2fill_vld_m),

        .q    (l2fill_vld_m),

        .clk  (clk),

        .clk  (clk),

        .se   (1'b0),       .si (),          .so ()

        .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//dff           l2fv_stgg (

//dff           l2fv_stgg (

//        .din  (l2fill_vld_m),

//        .din  (l2fill_vld_m),

//      .q    (l2fill_vld_g),

//      .q    (l2fill_vld_g),

//        .clk  (clk),

//        .clk  (clk),

//        .se   (1'b0),       .si (),          .so ()

//        .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

//        );

//        );

wire    ld_inst_vld_m ;

wire    ld_inst_vld_m ;

dff     lvld_stgm (

dff_s           lvld_stgm (

        .din  (ld_inst_vld_e),

        .din  (ld_inst_vld_e),

        .q    (ld_inst_vld_m),

        .q    (ld_inst_vld_m),

        .clk  (clk),

        .clk  (clk),

        .se   (1'b0),       .si (),          .so ()

        .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//wire  ld_inst_vld_g ;

//wire  ld_inst_vld_g ;

//dff           lvld_stgg (

//dff           lvld_stgg (

//        .din  (ld_inst_vld_m),

//        .din  (ld_inst_vld_m),

//      .q    (ld_inst_vld_g),

//      .q    (ld_inst_vld_g),

//        .clk  (clk),

//        .clk  (clk),

//        .se   (1'b0),       .si (),          .so ()

//        .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

//        );

//        );

wire    ldd_in_dfq_out_vld ;

wire    ldd_in_dfq_out_vld ;

assign  ldd_in_dfq_out_vld = ldd_in_dfq_out_d1 & l2fill_vld_m ;

assign  ldd_in_dfq_out_vld = ldd_in_dfq_out_d1 & l2fill_vld_m ;

assign lsu_exu_rd_m[4:0] =

assign lsu_exu_rd_m[4:0] =

Line 2525...

Line 1126...

// quad ldd, fp ldd sz = 2'b11, int ldd sz = 2'b10

// quad ldd, fp ldd sz = 2'b11, int ldd sz = 2'b10

assign  ldd_non_alt_space = lsu_byp_misc_sz_e[1] & ~lsu_byp_misc_sz_e[0] ;

assign  ldd_non_alt_space = lsu_byp_misc_sz_e[1] & ~lsu_byp_misc_sz_e[0] ;

assign  ldd_oddrd_e = ldd_in_dfq_out & ldd_non_alt_space ;

assign  ldd_oddrd_e = ldd_in_dfq_out & ldd_non_alt_space ;

dff   ldd_stgm (

dff_s   ldd_stgm (

        .din    (ldd_oddrd_e),

        .din    (ldd_oddrd_e),

  .q    (lsu_byp_ldd_oddrd_m),

  .q    (lsu_byp_ldd_oddrd_m),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// all incoming ld and inv packets must be written to dfq or its bypass flop.

// all incoming ld and inv packets must be written to dfq or its bypass flop.

// wrt ptr must be updated in cycle that cpx pkt is sent.

// wrt ptr must be updated in cycle that cpx pkt is sent.

Line 2551...

Line 1152...

wire    strmack_cmplt1_d1, strmack_cmplt2_d1, strmack_cmplt3_d1 ;

wire    strmack_cmplt1_d1, strmack_cmplt2_d1, strmack_cmplt3_d1 ;

//wire  strm_ack_cmplt ;

//wire  strm_ack_cmplt ;

assign  strmack_cmplt1 =

assign  strmack_cmplt1 =

        // check inflight, no inv. if inv, write to dfq_byp.

        // check inflight, no inv. if inv, write to dfq_byp.

        (cpx_strm_st_ack_type & ~(dfq_wr_en | lsu_cpx_spc_inv_vld) &

        (cpx_strm_st_ack_type & ~(dfq_wr_en | lsu_cpx_spc_inv_vld) &

         (const_cpuid[2:0] == cpx_spc_data_cx_b120to118[120:118])) ;

         (const_cpuid[2:0] == cpx_spc_data_cx_b120to118[`CPX_INV_CID_HI:`CPX_INV_CID_LO])) ;

assign  strmack_cmplt2 =

assign  strmack_cmplt2 =

        // check dfq-rd - no inv, gets dropped.

        // check dfq-rd - no inv, gets dropped.

        (lsu_dfq_byp_type[1] & dfq_rd_advance & ~lsu_dfq_byp_cpx_inv & local_pkt) ;

        (lsu_dfq_byp_type[1] & dfq_rd_advance & ~lsu_dfq_byp_cpx_inv & local_pkt) ;

assign  strmack_cmplt3 =

assign  strmack_cmplt3 =

        // check dfq-rd - inv, and thus process from dfq_bypass.

        // check dfq-rd - inv, and thus process from dfq_bypass.

Line 2568...

Line 1169...

        // check dfq-rd - no inv, gets dropped.

        // check dfq-rd - no inv, gets dropped.

        (lsu_dfq_byp_type[1] & dfq_rd_advance & ~lsu_dfq_byp_cpx_inv & local_pkt) |

        (lsu_dfq_byp_type[1] & dfq_rd_advance & ~lsu_dfq_byp_cpx_inv & local_pkt) |

        // check dfq-rd - inv, and thus process from dfq_bypass.

        // check dfq-rd - inv, and thus process from dfq_bypass.

        (lsu_cpx_pkt_strm_ack & inv_active_e & dfq_inv_vld & dfq_local_pkt) ;*/

        (lsu_cpx_pkt_strm_ack & inv_active_e & dfq_inv_vld & dfq_local_pkt) ;*/

dff #(3)   strmackcnt_stg (

dff_s #(3)   strmackcnt_stg (

        .din    ({strmack_cmplt3,strmack_cmplt2,strmack_cmplt1}),

        .din    ({strmack_cmplt3,strmack_cmplt2,strmack_cmplt1}),

        .q      ({strmack_cmplt3_d1,strmack_cmplt2_d1,strmack_cmplt1_d1}),

        .q      ({strmack_cmplt3_d1,strmack_cmplt2_d1,strmack_cmplt1_d1}),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  lsu_spu_strm_ack_cmplt[0] =      // lsb  of cnt, 1 or 3.

assign  lsu_spu_strm_ack_cmplt[0] =      // lsb  of cnt, 1 or 3.

        (~strmack_cmplt1_d1 & ~strmack_cmplt2_d1 &  strmack_cmplt3_d1) | //001

        (~strmack_cmplt1_d1 & ~strmack_cmplt2_d1 &  strmack_cmplt3_d1) | //001

        (~strmack_cmplt1_d1 &  strmack_cmplt2_d1 & ~strmack_cmplt3_d1) | //010

        (~strmack_cmplt1_d1 &  strmack_cmplt2_d1 & ~strmack_cmplt3_d1) | //010

Line 2590...

Line 1191...

/*dff   strmack_d1 (

/*dff   strmack_d1 (

        .din  (strm_ack_cmplt),

        .din  (strm_ack_cmplt),

        .q    (lsu_spu_strm_ack_cmplt),

        .q    (lsu_spu_strm_ack_cmplt),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

        ); */

        ); */

// Active as soon as it is visible in dfq byp ff.

// Active as soon as it is visible in dfq byp ff.

assign  inv_active_e = dfq_inv_vld ;      // evict/icache/strm-st

assign  inv_active_e = dfq_inv_vld ;      // evict/icache/strm-st

//wire  st_atm_err ;

//wire  st_atm_err ;

Line 2672...

Line 1273...

//timing fix: 7/14/03 - to improve setup of dfq_st_vld and dfq_ld_vld and move the flop to qdp2 -

//timing fix: 7/14/03 - to improve setup of dfq_st_vld and dfq_ld_vld and move the flop to qdp2 -

//            to eventually improve dcache_fill_data timing

//            to eventually improve dcache_fill_data timing

//            add byp mux for cpuid in qctl2

//            add byp mux for cpuid in qctl2

wire  [2:0]  dfq_byp_cpuid ;

wire  [2:0]  dfq_byp_cpuid ;

assign  dfq_byp_cpuid[2:0]  =  dfq_rd_vld_d1 ? lsu_dfq_rdata_cpuid[2:0] :

assign  dfq_byp_cpuid[2:0]  =  dfq_rd_vld_d1 ? lsu_dfq_rdata_cpuid[2:0] :

                                   cpx_spc_data_cx_b120to118[120:118] ;

                                   cpx_spc_data_cx_b120to118[`CPX_INV_CID_HI:`CPX_INV_CID_LO] ;

//assign  local_pkt =  &(const_cpuid[2:0] ~^ lsu_dfq_byp_cpuid[2:0]) ;

//assign  local_pkt =  &(const_cpuid[2:0] ~^ lsu_dfq_byp_cpuid[2:0]) ;

assign  local_pkt =  &(const_cpuid[2:0] ~^ dfq_byp_cpuid[2:0]) ;

assign  local_pkt =  &(const_cpuid[2:0] ~^ dfq_byp_cpuid[2:0]) ;

assign  dfq_rdata_local_pkt =  &(const_cpuid[2:0] ~^ lsu_dfq_rdata_cpuid[2:0]) ;

assign  dfq_rdata_local_pkt =  &(const_cpuid[2:0] ~^ lsu_dfq_rdata_cpuid[2:0]) ;

assign  dfq_byp_st_vld = lsu_dfq_byp_type[2] & local_pkt ;

assign  dfq_byp_st_vld = lsu_dfq_byp_type[2] & local_pkt ;

Line 2696...

Line 1297...

    ~ld_ignore_sec  // secondary loads

    ~ld_ignore_sec  // secondary loads

    ) ; */

    ) ; */

/*wire  ld_sec_rst, ld_sec_rst_d1 ;

/*wire  ld_sec_rst, ld_sec_rst_d1 ;

assign  ld_sec_rst = dcfill_active_e & ld_ignore_sec_last ;

assign  ld_sec_rst = dcfill_active_e & ld_ignore_sec_last ;

dff   secl_d1 (

dff_s   secl_d1 (

        .din    (ld_sec_rst), .q  (ld_sec_rst_d1),

        .din    (ld_sec_rst), .q  (ld_sec_rst_d1),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

        ); */

        ); */

/* phase 2 change

/* phase 2 change

assign dfq_vld_reset =

assign dfq_vld_reset =

    // dside pkt in waiting, ldd, secondary loads

    // dside pkt in waiting, ldd, secondary loads

Line 2721...

Line 1322...

// vld is enabled only if both i and d side buffers are clear

// vld is enabled only if both i and d side buffers are clear

// for co-dependent events. co-dependent events are rare.

// for co-dependent events. co-dependent events are rare.

wire    dfq_rd_advance_buf1 ;

wire    dfq_rd_advance_buf1 ;

assign dfq_vld_en = dfq_byp_vld &

assign dfq_vld_en = dfq_byp_vld &

                (dfq_rd_advance_buf1 |

                (dfq_rd_advance_buf1 |

                (cpx_spc_data_cx_b144to140[144] & vld_dfq_pkt & ~dfq_wr_en)) ;

                (cpx_spc_data_cx_b144to140[`CPX_VLD] & vld_dfq_pkt & ~dfq_wr_en)) ;

/* phase 2 change

/* phase 2 change

assign  dfq_byp_ff_en =

assign  dfq_byp_ff_en =

  (~dfq_byp_full |

  (~dfq_byp_full |

  ( dfq_byp_full & ((dcfill_active_e & ~(lsu_ignore_fill | ld_ignore_sec)) |

  ( dfq_byp_full & ((dcfill_active_e & ~(lsu_ignore_fill | ld_ignore_sec)) |

Line 2751...

Line 1352...

// dfq bypass valid

// dfq bypass valid

//timing fix: 6/6/03: add duplicate flop for dfq_byp_ld_vld and dfq_byp_st_vld

//timing fix: 6/6/03: add duplicate flop for dfq_byp_ld_vld and dfq_byp_st_vld

//timing fix: 10/3/03 - add separate flop for lsu_dfq_vld lsu_dfq_st_vld to dctl

//timing fix: 10/3/03 - add separate flop for lsu_dfq_vld lsu_dfq_st_vld to dctl

//bug4460:  qualify stream store ack w/ local packet - add local pkt flop

//bug4460:  qualify stream store ack w/ local packet - add local pkt flop

dffre  #(10) dfq_vld (

dffre_s  #(10) dfq_vld (

        .din({local_pkt,dfq_byp_st_vld,dfq_byp_vld,dfq_byp_vld,

        .din({local_pkt,dfq_byp_st_vld,dfq_byp_vld,dfq_byp_vld,

              dfq_byp_ld_vld,dfq_byp_inv_vld,dfq_byp_st_vld,

              dfq_byp_ld_vld,dfq_byp_inv_vld,dfq_byp_st_vld,

              lsu_dfq_byp_cpx_inv,dfq_byp_ld_vld,dfq_byp_st_vld}),

              lsu_dfq_byp_cpx_inv,dfq_byp_ld_vld,dfq_byp_st_vld}),

        .q  ({dfq_local_pkt,lsu_dfq_st_vld,lsu_dfq_vld,dfq_byp_full,

        .q  ({dfq_local_pkt,lsu_dfq_st_vld,lsu_dfq_vld,dfq_byp_full,

              dfq_ld_vld,dfq_inv_vld,dfq_st_vld,

              dfq_ld_vld,dfq_inv_vld,dfq_st_vld,

              dfq_local_inv,lsu_qdp2_dfq_ld_vld,lsu_qdp2_dfq_st_vld}),

              dfq_local_inv,lsu_qdp2_dfq_ld_vld,lsu_qdp2_dfq_st_vld}),

//.din    ({dfq_byp_vld,dfq_byp_ld_vld,dfq_byp_inv_vld,dfq_byp_st_vld,cpx_inv,lsu_dfq_byp_cpx_inv}),

//.din    ({dfq_byp_vld,dfq_byp_ld_vld,dfq_byp_inv_vld,dfq_byp_st_vld,cpx_inv,lsu_dfq_byp_cpx_inv}),

//.q      ({dfq_byp_full,dfq_ld_vld,dfq_inv_vld,dfq_st_vld,local_inv,dfq_local_inv}),

//.q      ({dfq_byp_full,dfq_ld_vld,dfq_inv_vld,dfq_st_vld,local_inv,dfq_local_inv}),

        .rst    (dfq_vld_reset),        .en     (dfq_vld_en),

        .rst    (dfq_vld_reset),        .en     (dfq_vld_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//bug4057: kill diagnostic write if dfq has valid requests to l1d$

//bug4057: kill diagnostic write if dfq has valid requests to l1d$

//timing fix: 10/3/03 - add separate flop for lsu_dfq_vld

//timing fix: 10/3/03 - add separate flop for lsu_dfq_vld

//assign  lsu_dfq_vld  =  dfq_byp_full ;

//assign  lsu_dfq_vld  =  dfq_byp_full ;

Line 2778...

Line 1379...

//bw_u1_buf_30x UZsize_lsu_dfq_st_vld_buf1 ( .a(dfq_st_vld), .z(lsu_dfq_st_vld) );

//bw_u1_buf_30x UZsize_lsu_dfq_st_vld_buf1 ( .a(dfq_st_vld), .z(lsu_dfq_st_vld) );

assign  lsu_dfq_ldst_vld  =  lsu_qdp2_dfq_ld_vld | lsu_qdp2_dfq_st_vld;

assign  lsu_dfq_ldst_vld  =  lsu_qdp2_dfq_ld_vld | lsu_qdp2_dfq_st_vld;

// Flop invalidate bits

// Flop invalidate bits

dffe  #(12) dfq_inv (

dffe_s  #(12) dfq_inv (

        .din    ({lsu_cpu_inv_data_b13to9,lsu_cpu_inv_data_b7to2,lsu_cpu_inv_data_b0}),

        .din    ({lsu_cpu_inv_data_b13to9,lsu_cpu_inv_data_b7to2,lsu_cpu_inv_data_b0}),

        .q    ({dfq_inv_data_b13to9,dfq_inv_data_b7to2,dfq_inv_data_b0}),

        .q    ({dfq_inv_data_b13to9,dfq_inv_data_b7to2,dfq_inv_data_b0}),

        //.din    (lsu_cpu_inv_data[13:0]),

        //.din    (lsu_cpu_inv_data[13:0]),

        //.q      (dfq_inv_data[13:0]),

        //.q      (dfq_inv_data[13:0]),

        .en     (dfq_vld_en),

        .en     (dfq_vld_en),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

/*

/*

assign  lsu_st_ack_addr_b54[0] = dfq_inv_data[4] | dfq_inv_data[11] ;

assign  lsu_st_ack_addr_b54[0] = dfq_inv_data[4] | dfq_inv_data[11] ;

Line 2819...

Line 1420...

// All cpx pkts are written.

// All cpx pkts are written.

// - unwanted pkts are explicity overwritten by next incoming pkt.

// - unwanted pkts are explicity overwritten by next incoming pkt.

   /*wire stb_cam_hit_w2;

   /*wire stb_cam_hit_w2;

dff #(1)  stb_cam_hit_stg_w2  (

dff_s #(1)  stb_cam_hit_stg_w2  (

  .din (stb_cam_hit),

  .din (stb_cam_hit),

  .q   (stb_cam_hit_w2),

  .q   (stb_cam_hit_w2),

  .clk (clk),

  .clk (clk),

  .se  (1'b0), .si (), .so ()

  .se  (1'b0), `SIMPLY_RISC_SCANIN, .so ()

  ); */

  ); */

// Need to include error pkt !!

// Need to include error pkt !!

//8/25/03: add error type to dfq_wr_en, dfq_rd_advance

//8/25/03: add error type to dfq_wr_en, dfq_rd_advance

//8/25/03: add fwd req to L1I$ for RAMTEST to dfq_wr_en, dfq_rd_dvance

//8/25/03: add fwd req to L1I$ for RAMTEST to dfq_wr_en, dfq_rd_dvance

Line 2860...

Line 1461...

assign  dfq_wptr_new_w_wrap[5:0]  = dfq_wptr_w_wrap[5:0] + {5'b00000, dfq_wr_en} ;

assign  dfq_wptr_new_w_wrap[5:0]  = dfq_wptr_w_wrap[5:0] + {5'b00000, dfq_wr_en} ;

//assign  dfq_wptr_vld = dfq_wr_en ;

//assign  dfq_wptr_vld = dfq_wr_en ;

// every pkt is to be written to dfq. The pkt may be rejected by not updating

// every pkt is to be written to dfq. The pkt may be rejected by not updating

// write ptr based on certain conditions.

// write ptr based on certain conditions.

assign  dfq_wptr_vld = cpx_spc_data_cx_b144to140[144] ;

assign  dfq_wptr_vld = cpx_spc_data_cx_b144to140[`CPX_VLD] ;

dffre  #(6) dfq_wptr_ff (

dffre_s  #(6) dfq_wptr_ff (

        .din    (dfq_wptr_new_w_wrap[5:0]), .q  (dfq_wptr_w_wrap[5:0]),

        .din    (dfq_wptr_new_w_wrap[5:0]), .q  (dfq_wptr_w_wrap[5:0]),

        .rst    (reset), .en (dfq_wr_en), .clk (clk),

        .rst    (reset), .en (dfq_wr_en), .clk (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//1/20/04: mintime fix - add minbuf to dfq_wptr

//1/20/04: mintime fix - add minbuf to dfq_wptr

//assign  dfq_wptr[4:0] = dfq_wptr_w_wrap[4:0] ;

//assign  dfq_wptr[4:0] = dfq_wptr_w_wrap[4:0] ;

Line 2933...

Line 1534...

assign  lsu_ifill_pkt_vld =

assign  lsu_ifill_pkt_vld =

  (dfq_rptr_vld_d1 & ~(lsu_dfq_rdata_st_ack_type & lsu_dfq_rdata_stack_dcfill_vld) &

  (dfq_rptr_vld_d1 & ~(lsu_dfq_rdata_st_ack_type & lsu_dfq_rdata_stack_dcfill_vld) &

                     ~ifill_dinv_head_of_dfq_pend &

                     ~ifill_dinv_head_of_dfq_pend &

                     ~ifill_pkt_fwd_done_d1 ) |

                     ~ifill_pkt_fwd_done_d1 ) |

  (~dfq_rptr_vld_d1 & cpx_spc_data_cx_b144to140[144] & ~(dfq_wr_en | cpx_fwd_rply_type | cpx_fp_type)) ;

  (~dfq_rptr_vld_d1 & cpx_spc_data_cx_b144to140[`CPX_VLD] & ~(dfq_wr_en | cpx_fwd_rply_type | cpx_fp_type)) ;

// this signal acts as a mask i.e. fill valid will be asserted until the ifu_lsu_ibuf_busy=0. But certain packets need

// this signal acts as a mask i.e. fill valid will be asserted until the ifu_lsu_ibuf_busy=0. But certain packets need

// both busy=0 and memref_e=0 - in which case it is safer to mask until the dfq_rd_advance=1.

// both busy=0 and memref_e=0 - in which case it is safer to mask until the dfq_rd_advance=1.

//bug5309: add reset to the flop; x's get recycled from flop o/p until a dfq_rd_advance occurs i.e. flop reset

//bug5309: add reset to the flop; x's get recycled from flop o/p until a dfq_rd_advance occurs i.e. flop reset

Line 2946...

Line 1547...

assign  ifill_pkt_fwd_done  =  ~reset &

assign  ifill_pkt_fwd_done  =  ~reset &

                               (((dfq_rptr_vld_d1 & ~ifu_lsu_ibuf_busy & ~ifill_dinv_head_of_dfq_pend) |

                               (((dfq_rptr_vld_d1 & ~ifu_lsu_ibuf_busy & ~ifill_dinv_head_of_dfq_pend) |

                                ifill_pkt_fwd_done_d1)   // set|hold

                                ifill_pkt_fwd_done_d1)   // set|hold

                                & ~dfq_rd_advance);                                               // reset

                                & ~dfq_rd_advance);                                               // reset

dff  #(1) ifill_pkt_fwd_done_ff (

dff_s  #(1) ifill_pkt_fwd_done_ff (

        .din    (ifill_pkt_fwd_done),

        .din    (ifill_pkt_fwd_done),

        .q      (ifill_pkt_fwd_done_d1),

        .q      (ifill_pkt_fwd_done_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Note that this becomes valid in cycle of read. Flush will be continuously read

// Note that this becomes valid in cycle of read. Flush will be continuously read

Line 3007...

Line 1608...

        (dfq_st_ack_type & dfq_rdata_local_pkt &  lsu_dfq_rdata_stack_iinv_vld & ~ifu_lsu_ibuf_busy & dfq_byp_ff_en) ;

        (dfq_st_ack_type & dfq_rdata_local_pkt &  lsu_dfq_rdata_stack_iinv_vld & ~ifu_lsu_ibuf_busy & dfq_byp_ff_en) ;

// The pointer is advanced based on pre-flop bypass data.

// The pointer is advanced based on pre-flop bypass data.

wire inv_clear_d1 ;

wire inv_clear_d1 ;

dff  #(1) invclr_d1 (

dff_s  #(1) invclr_d1 (

        .din    (ifu_lsu_inv_clear),

        .din    (ifu_lsu_inv_clear),

        .q      (inv_clear_d1),

        .q      (inv_clear_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//---

//---

// Dealing with skid involving invalidate clear.

// Dealing with skid involving invalidate clear.

// 1. No stall asserted. If the int is immed. preceeded by an inv,

// 1. No stall asserted. If the int is immed. preceeded by an inv,

Line 3026...

Line 1627...

// stalls are conditionally inserted.

// stalls are conditionally inserted.

// Note : interrupts are always written into dfq.

// Note : interrupts are always written into dfq.

//---

//---

wire    dfq_rd_advance_d1 ;

wire    dfq_rd_advance_d1 ;

dff   rda_d1 (

dff_s   rda_d1 (

        .din    (dfq_rd_advance),

        .din    (dfq_rd_advance),

        .q      (dfq_rd_advance_d1),

        .q      (dfq_rd_advance_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Begin Bug 5583

// Begin Bug 5583

wire    dfq_int_type_d1 ;

wire    dfq_int_type_d1 ;

wire    int_skid_c1,int_skid_c2;

wire    int_skid_c1,int_skid_c2;

wire    int_skid_stall ;

wire    int_skid_stall ;

dff   itype_d1 (

dff_s   itype_d1 (

        .din    (dfq_int_type),

        .din    (dfq_int_type),

        .q      (dfq_int_type_d1),

        .q      (dfq_int_type_d1),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// decision made to issue intrpt from dfq even though

// decision made to issue intrpt from dfq even though

// intr-clear was not high, thus introduce stall for

// intr-clear was not high, thus introduce stall for

// 2 more cycles.

// 2 more cycles.

assign int_skid_c1 =

assign int_skid_c1 =

        dfq_int_type_d1 & dfq_rd_advance_d1 & ~inv_clear_d1 ;

        dfq_int_type_d1 & dfq_rd_advance_d1 & ~inv_clear_d1 ;

dff   iskid_c2 (

dff_s   iskid_c2 (

        .din    (int_skid_c1),

        .din    (int_skid_c1),

        .q      (int_skid_c2),

        .q      (int_skid_c2),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  int_skid_stall = int_skid_c1 | int_skid_c2 ;

assign  int_skid_stall = int_skid_c1 | int_skid_c2 ;

// End Bug 5583

// End Bug 5583

Line 3108...

Line 1709...

assign  dfq_flsh_cmplt[0] = local_flush & ~lsu_dfq_byp_tid[1] & ~lsu_dfq_byp_tid[0] ;

assign  dfq_flsh_cmplt[0] = local_flush & ~lsu_dfq_byp_tid[1] & ~lsu_dfq_byp_tid[0] ;

assign  dfq_flsh_cmplt[1] = local_flush & ~lsu_dfq_byp_tid[1] &  lsu_dfq_byp_tid[0] ;

assign  dfq_flsh_cmplt[1] = local_flush & ~lsu_dfq_byp_tid[1] &  lsu_dfq_byp_tid[0] ;

assign  dfq_flsh_cmplt[2] = local_flush &  lsu_dfq_byp_tid[1] & ~lsu_dfq_byp_tid[0] ;

assign  dfq_flsh_cmplt[2] = local_flush &  lsu_dfq_byp_tid[1] & ~lsu_dfq_byp_tid[0] ;

assign  dfq_flsh_cmplt[3] = local_flush &  lsu_dfq_byp_tid[1] &  lsu_dfq_byp_tid[0] ;

assign  dfq_flsh_cmplt[3] = local_flush &  lsu_dfq_byp_tid[1] &  lsu_dfq_byp_tid[0] ;

dff  #(4) flshcmplt (

dff_s  #(4) flshcmplt (

        .din    (dfq_flsh_cmplt[3:0]),

        .din    (dfq_flsh_cmplt[3:0]),

        .q      (lsu_dfq_flsh_cmplt[3:0]),

        .q      (lsu_dfq_flsh_cmplt[3:0]),

        .clk    (clk),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

// Check for extra bubbles in pipeline.

// Check for extra bubbles in pipeline.

//timing fix: 10/3/03 - use dfq_rd_advance as mux select

//timing fix: 10/3/03 - use dfq_rd_advance as mux select

Line 3131...

Line 1732...

assign  dfq_rptr_vld  =   dfq_vld_entry_exists_w ;

assign  dfq_rptr_vld  =   dfq_vld_entry_exists_w ;

wire   dfq_rptr_vld_w_d1;

wire   dfq_rptr_vld_w_d1;

dff   rvld_stgd1_new (

dff_s   rvld_stgd1_new (

        .din    (dfq_vld_entry_exists), .q  (dfq_vld_entry_exists_d1),

        .din    (dfq_vld_entry_exists), .q  (dfq_vld_entry_exists_d1),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

dff   rvld_stgd1 (

dff_s   rvld_stgd1 (

        .din    (dfq_rptr_vld), .q  (dfq_rptr_vld_w_d1),

        .din    (dfq_rptr_vld), .q  (dfq_rptr_vld_w_d1),

        //.din    (dfq_rptr_vld), .q  (dfq_rptr_vld_d1),

        //.din    (dfq_rptr_vld), .q  (dfq_rptr_vld_d1),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//dff   rdad_stgd1 (

//dff   rdad_stgd1 (

//        .din    (dfq_rd_advance), .q  (dfq_rd_advance_d1),

//        .din    (dfq_rd_advance), .q  (dfq_rd_advance_d1),

//        .clk  (clk),

//        .clk  (clk),

//        .se     (1'b0),       .si (),          .so ()

//        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

//        );

//        );

dffre  #(6) dfq_rptr_ff (

dffre_s  #(6) dfq_rptr_ff (

        .din    (dfq_rptr_new_w_wrap[5:0]), .q  (dfq_rptr_w_wrap[5:0]),

        .din    (dfq_rptr_new_w_wrap[5:0]), .q  (dfq_rptr_w_wrap[5:0]),

        .rst    (reset), .en (dfq_rd_advance), .clk (clk),

        .rst    (reset), .en (dfq_rd_advance), .clk (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

assign  dfq_rptr_vld_d1 = dfq_rptr_vld_w_d1 & dfq_vld_entry_exists_d1;

assign  dfq_rptr_vld_d1 = dfq_rptr_vld_w_d1 & dfq_vld_entry_exists_d1;

assign  dfq_rd_vld_d1 = dfq_rptr_vld_d1 ;

assign  dfq_rd_vld_d1 = dfq_rptr_vld_d1 ;

//bug4576: add sehold to the dfq_rdata mux select

//bug4576: add sehold to the dfq_rdata mux select

Line 3194...

Line 1795...

assign  dfq_stall = (dfq_vld_entries[5:0] >= 6'd4) ;

assign  dfq_stall = (dfq_vld_entries[5:0] >= 6'd4) ;

assign  lsu_ifu_stallreq =

assign  lsu_ifu_stallreq =

        dfq_stall |  int_skid_stall | lsu_tlbop_force_swo ;

        dfq_stall |  int_skid_stall | lsu_tlbop_force_swo ;

        //dfq_stall | dfq_stall_d1 | dfq_stall_d2 | int_skid_stall | lsu_tlbop_force_swo ;

        //dfq_stall | dfq_stall_d1 | dfq_stall_d2 | int_skid_stall | lsu_tlbop_force_swo ;

dff   dfqst_d1 (

dff_s   dfqst_d1 (

        .din  (dfq_stall), .q  (dfq_stall_d1),

        .din  (dfq_stall), .q  (dfq_stall_d1),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//=================================================================================================

//=================================================================================================

//  INVALIDATE PROCESSING

//  INVALIDATE PROCESSING

//=================================================================================================

//=================================================================================================

Line 3281...

Line 1882...

wire  [1:0]  lsu_dfq_byp_stack_adr_b54_d1,

wire  [1:0]  lsu_dfq_byp_stack_adr_b54_d1,

             lsu_dfq_byp_stack_wrway_d1;

             lsu_dfq_byp_stack_wrway_d1;

// bug3375: add enable to this flop - dfq_vld_en

// bug3375: add enable to this flop - dfq_vld_en

dffe #(5)  dfq_by_wrway_ad54_ff (

dffe_s #(5)  dfq_by_wrway_ad54_ff (

        .din    ({stack_type_dcfill_vld,lsu_dfq_byp_stack_adr_b54[1:0],lsu_dfq_byp_stack_wrway[1:0]}),

        .din    ({stack_type_dcfill_vld,lsu_dfq_byp_stack_adr_b54[1:0],lsu_dfq_byp_stack_wrway[1:0]}),

        .q      ({stack_type_dcfill_vld_d1,lsu_dfq_byp_stack_adr_b54_d1[1:0],lsu_dfq_byp_stack_wrway_d1[1:0]}),

        .q      ({stack_type_dcfill_vld_d1,lsu_dfq_byp_stack_adr_b54_d1[1:0],lsu_dfq_byp_stack_wrway_d1[1:0]}),

        .en     (dfq_vld_en),

        .en     (dfq_vld_en),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

//cpx_cpu_inv_data[13:0] =  {dfq_inv_data_b13to9,1'b0,dfq_inv_data_b7to2,1'b0,dfq_inv_data_b0}

//cpx_cpu_inv_data[13:0] =  {dfq_inv_data_b13to9,1'b0,dfq_inv_data_b7to2,1'b0,dfq_inv_data_b0}

//CPX_AX0_INV_DVLD 0

//CPX_AX0_INV_DVLD 0

//CPX_AX0_INV_WY_LO 2

//CPX_AX0_INV_WY_LO 2

Line 3400...

Line 2001...

  (dfq_byp_st_vld & dfq_rd_advance & ~lsu_dfq_byp_stquad_pkt2))   // local st ack from dfq

  (dfq_byp_st_vld & dfq_rd_advance & ~lsu_dfq_byp_stquad_pkt2))   // local st ack from dfq

  //(dfq_byp_st_vld & dfq_rd_advance_d1)) // local st ack from dfq

  //(dfq_byp_st_vld & dfq_rd_advance_d1)) // local st ack from dfq

  & cpx_inv ; */

  & cpx_inv ; */

/*

/*

dff #(1)  stackr_d1 (

dff_s #(1)  stackr_d1 (

        .din    (st_ack_rq_stb),

        .din    (st_ack_rq_stb),

        .q      (st_ack_rq_stb_d1),

        .q      (st_ack_rq_stb_d1),

        .clk  (clk),

        .clk  (clk),

        .se     (1'b0),       .si (),          .so ()

        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()

);

);

*/

*/

// Mux's control signal can be flipped - TIMING

// Mux's control signal can be flipped - TIMING

//assign  st_ack_tid[1:0] =

//assign  st_ack_tid[1:0] =

Line 3459...

Line 2060...

assign lsu_cpxpkt_type_dcd_cx[5:0] =

assign lsu_cpxpkt_type_dcd_cx[5:0] =

{cpx_ld_type,cpx_ifill_type,cpx_evict_type,cpx_st_ack_type,cpx_strm_st_ack_type,cpx_int_type};

{cpx_ld_type,cpx_ifill_type,cpx_evict_type,cpx_st_ack_type,cpx_strm_st_ack_type,cpx_int_type};

assign  cpx_ld_type =

assign  cpx_ld_type =

         cpx_spc_data_cx_b144to140[144] &

         cpx_spc_data_cx_b144to140[`CPX_VLD] &

        ((~cpx_spc_data_cx_b144to140[143]   & ~cpx_spc_data_cx_b144to140[140+2] & // 0000

        ((~cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 0000

          ~cpx_spc_data_cx_b144to140[140+1] & ~cpx_spc_data_cx_b144to140[140]));

          ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));

assign  cpx_ifill_type =

assign  cpx_ifill_type =

         cpx_spc_data_cx_b144to140[144] &

         cpx_spc_data_cx_b144to140[`CPX_VLD] &

        ((~cpx_spc_data_cx_b144to140[143]   & ~cpx_spc_data_cx_b144to140[140+2] & // 0001

        ((~cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 0001

          ~cpx_spc_data_cx_b144to140[140+1] &  cpx_spc_data_cx_b144to140[140]));

          ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));

assign  cpx_evict_type =

assign  cpx_evict_type =

         cpx_spc_data_cx_b144to140[144] &

         cpx_spc_data_cx_b144to140[`CPX_VLD] &

        ((~cpx_spc_data_cx_b144to140[143]   & ~cpx_spc_data_cx_b144to140[140+2] & // 0011

        ((~cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 0011

           cpx_spc_data_cx_b144to140[140+1] &  cpx_spc_data_cx_b144to140[140]));

           cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));

assign  cpx_st_ack_type =

assign  cpx_st_ack_type =

         cpx_spc_data_cx_b144to140[144] &

         cpx_spc_data_cx_b144to140[`CPX_VLD] &

        ((~cpx_spc_data_cx_b144to140[143]  &   cpx_spc_data_cx_b144to140[140+2] & // 0100

        ((~cpx_spc_data_cx_b144to140[`CPX_RQ_HI]  &   cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 0100

          ~cpx_spc_data_cx_b144to140[140+1] & ~cpx_spc_data_cx_b144to140[140]));

          ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));

         //~cpx_spc_data_cx[108] ;  // 1st stquad ack is rejected

         //~cpx_spc_data_cx[108] ;  // 1st stquad ack is rejected

assign  cpx_strm_st_ack_type =

assign  cpx_strm_st_ack_type =

         cpx_spc_data_cx_b144to140[144] &

         cpx_spc_data_cx_b144to140[`CPX_VLD] &

        ((~cpx_spc_data_cx_b144to140[143]   &  cpx_spc_data_cx_b144to140[140+2] & // 0110

        ((~cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 0110

           cpx_spc_data_cx_b144to140[140+1] & ~cpx_spc_data_cx_b144to140[140]));

           cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));

assign  cpx_int_type =

assign  cpx_int_type =

         cpx_spc_data_cx_b144to140[144] &

         cpx_spc_data_cx_b144to140[`CPX_VLD] &

        ((~cpx_spc_data_cx_b144to140[143]   &  cpx_spc_data_cx_b144to140[140+2] & // 0111

        ((~cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 0111

           cpx_spc_data_cx_b144to140[140+1] &  cpx_spc_data_cx_b144to140[140]));

           cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));

//bug3657  - kill ifill vld in bypass path when cpxtype=fp/fwd_reply

//bug3657  - kill ifill vld in bypass path when cpxtype=fp/fwd_reply

assign  cpx_fp_type =

assign  cpx_fp_type =

         cpx_spc_data_cx_b144to140[144] &

         cpx_spc_data_cx_b144to140[`CPX_VLD] &

        (( cpx_spc_data_cx_b144to140[143]   & ~cpx_spc_data_cx_b144to140[140+2] & // 1000

        (( cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 1000

          ~cpx_spc_data_cx_b144to140[140+1] & ~cpx_spc_data_cx_b144to140[140]));

          ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));

//8/25/03: add error type to dfq_wr_en, dfq_rd_advance

//8/25/03: add error type to dfq_wr_en, dfq_rd_advance

assign  cpx_error_type =

assign  cpx_error_type =

         cpx_spc_data_cx_b144to140[144] &

         cpx_spc_data_cx_b144to140[`CPX_VLD] &

        (( cpx_spc_data_cx_b144to140[143]   &  cpx_spc_data_cx_b144to140[140+2] & // 1100

        (( cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 1100

          ~cpx_spc_data_cx_b144to140[140+1] & ~cpx_spc_data_cx_b144to140[140]));

          ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));

// Miscellaneous cpu based decode

// Miscellaneous cpu based decode

assign  lsu_cpu_dcd_sel[7:0]  = {cpu_sel[3:0],cpu_sel[3:0]} ;

assign  lsu_cpu_dcd_sel[7:0]  = {cpu_sel[3:0],cpu_sel[3:0]} ;

assign  lsu_cpu_uhlf_sel  = const_cpuid[2] ;

assign  lsu_cpu_uhlf_sel  = const_cpuid[2] ;

Line 3518...

Line 2119...

// st ack to respective stb's. will not be generated for blk init stores

// st ack to respective stb's. will not be generated for blk init stores

// as such stores have already been deallocated.

// as such stores have already been deallocated.

assign  cpx_local_st_ack_type =

assign  cpx_local_st_ack_type =

  cpx_st_ack_type & (const_cpuid[2:0] == cpx_spc_data_cx_b120to118[120:118]) ;

  cpx_st_ack_type & (const_cpuid[2:0] == cpx_spc_data_cx_b120to118[`CPX_INV_CID_HI:`CPX_INV_CID_LO]) ;

 // & ~(cpx_spc_data_cx[`CPX_BINIT_STACK] | (|cpx_spc_data_cx[`CPX_PERR_DINV+1:`CPX_PERR_DINV])) ;

 // & ~(cpx_spc_data_cx[`CPX_BINIT_STACK] | (|cpx_spc_data_cx[`CPX_PERR_DINV+1:`CPX_PERR_DINV])) ;

wire    squash_ack ;

wire    squash_ack ;

assign squash_ack =

assign squash_ack =

(cpx_spc_data_cx_b125 | (|cpx_spc_data_cx_b124to123[123+1:123])) ;

(cpx_spc_data_cx_b125 | (|cpx_spc_data_cx_b124to123[`CPX_PERR_DINV+1:`CPX_PERR_DINV])) ;

assign  cpx_st_ack_tid0 = cpx_local_st_ack_type & ~squash_ack &

assign  cpx_st_ack_tid0 = cpx_local_st_ack_type & ~squash_ack &

                        ~cpx_spc_data_cx_b135to134[135] & ~cpx_spc_data_cx_b135to134[134] ;

                        ~cpx_spc_data_cx_b135to134[`CPX_TH_HI] & ~cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;

                        //~cpx_spc_data_cx[125] ; // rmo st will not ack

                        //~cpx_spc_data_cx[125] ; // rmo st will not ack

                        //~cpx_spc_data_cx[`CPX_WY_LO] ; // stquad1 will not ack - just invalidate.

                        //~cpx_spc_data_cx[`CPX_WY_LO] ; // stquad1 will not ack - just invalidate.

                                                      // b131 of cpx pkt used.

                                                      // b131 of cpx pkt used.

assign  cpx_st_ack_tid1 = cpx_local_st_ack_type & ~squash_ack &

assign  cpx_st_ack_tid1 = cpx_local_st_ack_type & ~squash_ack &

                        ~cpx_spc_data_cx_b135to134[135] &  cpx_spc_data_cx_b135to134[134] ;

                        ~cpx_spc_data_cx_b135to134[`CPX_TH_HI] &  cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;

                        //~cpx_spc_data_cx[125] ; // rmo st will not ack

                        //~cpx_spc_data_cx[125] ; // rmo st will not ack

                        //~cpx_spc_data_cx[`CPX_WY_LO] ; // stquad1 will not ack - just invalidate.

                        //~cpx_spc_data_cx[`CPX_WY_LO] ; // stquad1 will not ack - just invalidate.

                                                      // b131 of cpx pkt used.

                                                      // b131 of cpx pkt used.

assign  cpx_st_ack_tid2 = cpx_local_st_ack_type & ~squash_ack &

assign  cpx_st_ack_tid2 = cpx_local_st_ack_type & ~squash_ack &

                         cpx_spc_data_cx_b135to134[135] & ~cpx_spc_data_cx_b135to134[134] ;

                         cpx_spc_data_cx_b135to134[`CPX_TH_HI] & ~cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;

                        //~cpx_spc_data_cx[125] ; // rmo st will not ack

                        //~cpx_spc_data_cx[125] ; // rmo st will not ack

                        //~cpx_spc_data_cx[`CPX_WY_LO] ; // stquad1 will not ack - just invalidate.

                        //~cpx_spc_data_cx[`CPX_WY_LO] ; // stquad1 will not ack - just invalidate.

                                                      // b131 of cpx pkt used.

                                                      // b131 of cpx pkt used.

assign  cpx_st_ack_tid3 = cpx_local_st_ack_type & ~squash_ack &

assign  cpx_st_ack_tid3 = cpx_local_st_ack_type & ~squash_ack &

                         cpx_spc_data_cx_b135to134[135] & cpx_spc_data_cx_b135to134[134] ;

                         cpx_spc_data_cx_b135to134[`CPX_TH_HI] & cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;

                        //~cpx_spc_data_cx[125] ; // rmo st will not ack

                        //~cpx_spc_data_cx[125] ; // rmo st will not ack

                        //~cpx_spc_data_cx[`CPX_WY_LO] ; // stquad1 will not ack - just invalidate.

                        //~cpx_spc_data_cx[`CPX_WY_LO] ; // stquad1 will not ack - just invalidate.

                                                      // b131 of cpx pkt used.

                                                      // b131 of cpx pkt used.

// Performance Ctr Info

// Performance Ctr Info

Line 3639...

Line 2240...

assign  cpx_iinv_vld[7] = cpx_spc_data_cx_b85 |

assign  cpx_iinv_vld[7] = cpx_spc_data_cx_b85 |

                          cpx_spc_data_cx_b29 ;

                          cpx_spc_data_cx_b29 ;

//bug3701 - include i$ parity error invalidate - b[124]

//bug3701 - include i$ parity error invalidate - b[124]

assign cpx_spc_iinv_vld  =  |( (cpx_iinv_vld[7:0] | {8{cpx_spc_data_cx_b124to123[123+1]}}) & cpu_sel_dcd[7:0] )  ;

assign cpx_spc_iinv_vld  =  |( (cpx_iinv_vld[7:0] | {8{cpx_spc_data_cx_b124to123[`CPX_PERR_DINV+1]}}) & cpu_sel_dcd[7:0] )  ;

// dfq_rd_advance - local st ack not qualified w/ ifu_lsu_ibuf_busy

// dfq_rd_advance - local st ack not qualified w/ ifu_lsu_ibuf_busy

// qualify ifu_busy w/ local_st_ack=1 and iinv=1

// qualify ifu_busy w/ local_st_ack=1 and iinv=1

Line 3662...

Line 2263...

//assign  lsu_dcfill_addr_mx_sel_e  =  ~|lsu_dcfill_mx_sel_e[1:0];

//assign  lsu_dcfill_addr_mx_sel_e  =  ~|lsu_dcfill_mx_sel_e[1:0];

//assign  lsu_dcfill_data_mx_sel_e  =  lsu_dc_iob_access_e | lsu_bist_wvld_e;

//assign  lsu_dcfill_data_mx_sel_e  =  lsu_dc_iob_access_e | lsu_bist_wvld_e;

assign lsu_cpx_thrdid[0]  =  ~cpx_spc_data_cx_b135to134[135] & ~cpx_spc_data_cx_b135to134[134] ;

assign lsu_cpx_thrdid[0]  =  ~cpx_spc_data_cx_b135to134[`CPX_TH_HI] & ~cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;

assign lsu_cpx_thrdid[1]  =  ~cpx_spc_data_cx_b135to134[135] &  cpx_spc_data_cx_b135to134[134] ;

assign lsu_cpx_thrdid[1]  =  ~cpx_spc_data_cx_b135to134[`CPX_TH_HI] &  cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;

assign lsu_cpx_thrdid[2]  =   cpx_spc_data_cx_b135to134[135] & ~cpx_spc_data_cx_b135to134[134] ;

assign lsu_cpx_thrdid[2]  =   cpx_spc_data_cx_b135to134[`CPX_TH_HI] & ~cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;

assign lsu_cpx_thrdid[3]  =   cpx_spc_data_cx_b135to134[135] &  cpx_spc_data_cx_b135to134[134] ;

assign lsu_cpx_thrdid[3]  =   cpx_spc_data_cx_b135to134[`CPX_TH_HI] &  cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;

// modify cpx packet only if dcache update from stb has to be made.

// modify cpx packet only if dcache update from stb has to be made.

// lsu_cpx_spc_inv_vld = 1 => invalidate dcache for atomic- b[129] and bst- b[125]

// lsu_cpx_spc_inv_vld = 1 => invalidate dcache for atomic- b[129] and bst- b[125]

//                            update dcache for other requests

//                            update dcache for other requests

//

//

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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [lsu_qctl2.v] - Diff between revs 105 and 113