OpenCores
URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [lsu_qdp2.v] - Diff between revs 105 and 113

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Rev 105 Rev 113
Line 16... Line 16... 
// You should have received a copy of the GNU General Public
 
// You should have received a copy of the GNU General Public
 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
`define SIMPLY_RISC_SCANIN .si(0)
 
 
 
`else
 
 
 
`define SIMPLY_RISC_SCANIN .si()
 
 
 
`endif
 
///////////////////////////////////////////////////////////////////////
 
///////////////////////////////////////////////////////////////////////
 
/*
 
/*
 
//  Module Name:  LSU_QDP2
 
//  Module Name:  LSU_QDP2
 
//  Description:  LSU CPX Datapath.
 
//  Description:  LSU CPX Datapath.
 
*/
 
*/
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// header file includes
 
// header file includes
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// system level definition file which contains the /*
 
`include  "sys.h" // system level definition file which contains the 
/* ========== Copyright Header Begin ==========================================
 
                  // time scale definition
 
*
 
`include  "iop.h"
 
* OpenSPARC T1 Processor File: sys.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
// -*- verilog -*-
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
// Description:         Global header file that contain definitions that
 
 
 
//                      are common/shared at the systme level
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
//
 
 
 
// Setting the time scale
 
 
 
// If the timescale changes, JP_TIMESCALE may also have to change.
 
 
 
`timescale      1ps/1ps
 
 
 
 
 
 
 
//
 
 
 
// JBUS clock
 
 
 
// =========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Defines
 
 
 
// ==================
 
 
 
 
 
 
 
// Reliable Link
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Objects
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Reliable Link
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Congestion
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Acknowledge
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Request
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Message
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Acknowledge Types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Request Types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Frame
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Packet Type
 
 
 
// ===============
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Data Packet Format
 
 
 
// ======================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Size encoding for the UCB_SIZE_HI/LO field
 
 
 
// 000 - byte
 
 
 
// 001 - half-word
 
 
 
// 010 - word
 
 
 
// 011 - double-word
 
 
 
// 111 - quad-word
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Interrupt Packet Format
 
 
 
// ===========================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define UCB_THR_HI             9      // (6) cpu/thread ID shared with
 
 
 
//`define UCB_THR_LO             4             data packet format
 
 
 
//`define UCB_PKT_HI             3      // (4) packet type shared with
 
 
 
//`define UCB_PKT_LO             0      //     data packet format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// FCRAM Bus Widths
 
 
 
// ================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// ENET clock periods
 
 
 
// ==================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBus Bridge defines
 
 
 
// =================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PCI Device Address Configuration
 
 
 
// ================================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                  // time scale definition
 
 
 
/*
 
 
 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: iop.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
//-*- verilog -*-
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
//  Description:        Global header file that contain definitions that
 
 
 
//                      are common/shared at the IOP chip level
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
 
 
 
 
 
 
 
// Address Map Defines
 
 
 
// ===================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CMP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// IOP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                               //`define ENET_ING_CSR     8'h84
 
 
 
                               //`define ENET_EGR_CMD_CSR 8'h85
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2 space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// More IOP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//Cache Crossbar Width and Field Defines
 
 
 
//======================================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//bits 133:128 are shared by different fields
 
 
 
//for different packet types.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//End cache crossbar defines
 
 
 
 
 
 
 
 
 
 
 
// Number of COS supported by EECU 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// BSC bus sizes
 
 
 
// =============
 
 
 
//
 
 
 
 
 
 
 
// General
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CTags
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// reinstated temporarily
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CoS
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Bank
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Req
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Command Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// This is cleaved in between Egress Datapath Ack's
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Datapath
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: EEPU
 
 
 
// Tag is: TLEN, SOF, EOF, QID = 15
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Nack + Tag Info + CTag
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Req
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Ingress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Packet Unit Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: PCI
 
 
 
// Tag is: CTAG
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PCI-X Request
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PCI_X Acknowledge
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// BSC array sizes
 
 
 
//================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ECC syndrome bits per memory element
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// BSC Port Definitions
 
 
 
// ====================
 
 
 
//
 
 
 
// Bits 7 to 4 of curr_port_id
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Number of ports of each type
 
 
 
 
 
 
 
 
 
 
 
// Bits needed to represent above
 
 
 
 
 
 
 
 
 
 
 
// How wide the linked list pointers are
 
 
 
// 60b for no payload (2CoS)
 
 
 
// 80b for payload (2CoS)
 
 
 
 
 
 
 
//`define BSC_OBJ_PTR   80
 
 
 
//`define BSC_HD1_HI    69
 
 
 
//`define BSC_HD1_LO    60
 
 
 
//`define BSC_TL1_HI    59
 
 
 
//`define BSC_TL1_LO    50
 
 
 
//`define BSC_CT1_HI    49
 
 
 
//`define BSC_CT1_LO    40
 
 
 
//`define BSC_HD0_HI    29
 
 
 
//`define BSC_HD0_LO    20
 
 
 
//`define BSC_TL0_HI    19
 
 
 
//`define BSC_TL0_LO    10
 
 
 
//`define BSC_CT0_HI     9
 
 
 
//`define BSC_CT0_LO     0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// I2C STATES in DRAMctl
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// IOB defines
 
 
 
// ===========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_INT_STAT_WIDTH   32
 
 
 
//`define IOB_INT_STAT_HI      31
 
 
 
//`define IOB_INT_STAT_LO       0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// fixme - double check address mapping
 
 
 
// CREG in `IOB_INT_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CREG in `IOB_MAN_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Address map for TAP access of SPARC ASI
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CIOP UCB Bus Width
 
 
 
// ==================
 
 
 
//
 
 
 
//`define IOB_EECU_WIDTH       16  // ethernet egress command
 
 
 
//`define EECU_IOB_WIDTH       16
 
 
 
 
 
 
 
//`define IOB_NRAM_WIDTH       16  // NRAM (RLDRAM previously)
 
 
 
//`define NRAM_IOB_WIDTH        4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_ENET_ING_WIDTH   32  // ethernet ingress
 
 
 
//`define ENET_ING_IOB_WIDTH    8
 
 
 
 
 
 
 
//`define IOB_ENET_EGR_WIDTH    4  // ethernet egress
 
 
 
//`define ENET_EGR_IOB_WIDTH    4
 
 
 
 
 
 
 
//`define IOB_ENET_MAC_WIDTH    4  // ethernet MAC
 
 
 
//`define ENET_MAC_IOB_WIDTH    4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_BSC_WIDTH         4  // BSC
 
 
 
//`define BSC_IOB_WIDTH         4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_CLSP_WIDTH        4  // clk spine unit
 
 
 
//`define CLSP_IOB_WIDTH        4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CIOP UCB Buf ID Type
 
 
 
// ====================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Interrupt Device ID
 
 
 
// ===================
 
 
 
//
 
 
 
// Caution: DUMMY_DEV_ID has to be 9 bit wide
 
 
 
//          for fields to line up properly in the IOB.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Soft Error related definitions 
 
 
// ==============================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CMP clock
 
 
 
// =========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// NRAM/IO Interface
 
 
 
// =================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// NRAM/ENET Interface
 
 
 
// ===================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// IO/FCRAM Interface
 
 
 
// ==================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PCI Interface
 
 
 
// ==================
 
 
 
// Load/store size encodings
 
 
 
// -------------------------
 
 
 
// Size encoding
 
 
 
// 000 - byte
 
 
 
// 001 - half-word
 
 
 
// 010 - word
 
 
 
// 011 - double-word
 
 
 
// 100 - quad
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBI<->SCTAG Interface
 
 
 
// =======================
 
 
 
// Outbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Inbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBI->IOB Mondo Header Format
 
 
 
// ============================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// JBI->IOB Mondo Bus Width/Cycle
 
 
 
// ==============================
 
 
 
// Cycle  1 Header[15:8]
 
 
 
// Cycle  2 Header[ 7:0]
 
 
 
// Cycle  3 J_AD[127:120]
 
 
 
// Cycle  4 J_AD[119:112]
 
 
 
// .....
 
 
 
// Cycle 18 J_AD[  7:  0]
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/*
 
 
 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: lsu.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define STB_PCX_WY_HI   107
 
 
 
//`define STB_PCX_WY_LO   106
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// TLB Tag and Data Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// I-TLB version - lsu_tlb only.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Invalidate Format
 
 
 
//addr<5:4>=00
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//addr<5:4>=01
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//addr<5:4>=10
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//addr<5:4>=11
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// cpuid - 4b
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CPUany, addr<5:4>=00,10
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CPUany, addr<5:4>=01,11
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CPUany, addr<5:4>=01,11
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// DTAG parity error Invalidate
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CPX BINIT STORE
 
 
 
 
 
 
 
 
 
`include  "lsu.h"
 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Local header file includes / local defines
 
// Local header file includes / local defines
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
 
//FPGA_SYN enables all FPGA related modifications
 
//FPGA_SYN enables all FPGA related modifications
 
 
 
`ifdef FPGA_SYN
 
 
 
`define FPGA_SYN_CLK_EN
 
 
 
`define FPGA_SYN_CLK_DFF
 
 
 
`endif
 
 
 
 
 
module lsu_qdp2 ( /*AUTOARG*/
 
module lsu_qdp2 ( /*AUTOARG*/
 
   // Outputs
 
   // Outputs
 
   so, lsu_l2fill_data, dfq_wdata, dfq_tid, lsu_dcache_fill_data_e,
 
   so, lsu_l2fill_data, dfq_wdata, dfq_tid, lsu_dcache_fill_data_e,
 
   lsu_ifill_pkt, lsu_pcx_fwd_pkt, lsu_cpx_pkt_strm_ack,
 
   lsu_ifill_pkt, lsu_pcx_fwd_pkt, lsu_cpx_pkt_strm_ack,
Line 1499... Line 88... 
 
 
 
 
input                       lsu_dfill_data_sel_hi ; // select hi or low order 8B. 
input                       lsu_dfill_data_sel_hi ; // select hi or low order 8B. 
//input                       dcfill_src_dfq_sel ;
 
//input                       dcfill_src_dfq_sel ;
 
input                       dfq_byp_ff_en ;
 
input                       dfq_byp_ff_en ;
 
input                       dfq_rd_vld_d1 ;
 
input                       dfq_rd_vld_d1 ;
 
input [151:0]        dfq_rdata ;             // dfq rd output
 
input [`DFQ_WIDTH:0]        dfq_rdata ;             // dfq rd output
 
input [145-1:0]      cpx_spc_data_cx;        // cpx to processor pkt
 
input [`CPX_WIDTH-1:0]      cpx_spc_data_cx;        // cpx to processor pkt
 
//input [2:0]                 stb_dfq_rd_id ;         // stb entry id 
//input [2:0]                 stb_dfq_rd_id ;         // stb entry id 
input [69:0]                stb_rdata_ramd_buf ;        // stb0 data ram output.
 
input [69:0]                stb_rdata_ramd_buf ;        // stb0 data ram output.
 
input                       stb_rdata_ramd_b74_buf ;        // stb0 data ram output.
 
input                       stb_rdata_ramd_b74_buf ;        // stb0 data ram output.
 
input [14:9]                stb_rdata_ramc_buf ;        // stb0 tag ram output.
 
input [14:9]                stb_rdata_ramc_buf ;        // stb0 tag ram output.
 
input                       lsu_stb_pcx_rvld_d1 ;   // stb has been read-delayby1cycle
 
input                       lsu_stb_pcx_rvld_d1 ;   // stb has been read-delayby1cycle
Line 1558... Line 147... 
// End of automatics
 
// End of automatics
 
//
 
//
 
 
 
 
 
output  [63:0]            lsu_l2fill_data ;       // dfill data for write to irf
 
output  [63:0]            lsu_l2fill_data ;       // dfill data for write to irf
 
 
 
 
 
output  [151:0]    dfq_wdata ;
 
output  [`DFQ_WIDTH:0]    dfq_wdata ;
 
output  [1:0]             dfq_tid ;               // thread-id for load at head of DFQ.
 
output  [1:0]             dfq_tid ;               // thread-id for load at head of DFQ.
 
 
 
 
 
output  [143:0]           lsu_dcache_fill_data_e ;// store-write/ld-miss fill 
output  [143:0]           lsu_dcache_fill_data_e ;// store-write/ld-miss fill 
 
 
 
 
output  [144-1:0]  lsu_ifill_pkt ;
 
output  [`CPX_VLD-1:0]  lsu_ifill_pkt ;
 
output  [107:0]           lsu_pcx_fwd_pkt ;       // local fwd reply/req 
output  [107:0]           lsu_pcx_fwd_pkt ;       // local fwd reply/req 
output                    lsu_cpx_pkt_strm_ack ;
 
output                    lsu_cpx_pkt_strm_ack ;
 
output                    lsu_cpx_pkt_vld ;
 
output                    lsu_cpx_pkt_vld ;
 
output                    lsu_cpx_pkt_atm_st_cmplt ;
 
output                    lsu_cpx_pkt_atm_st_cmplt ;
 
output  [1:0]             lsu_cpx_pkt_tid ;
 
output  [1:0]             lsu_cpx_pkt_tid ;
Line 1618... Line 207... 
// End of automatics
 
// End of automatics
 
wire  [13:0]      cpx_cpulo_inv_data ;
 
wire  [13:0]      cpx_cpulo_inv_data ;
 
wire  [13:0]      cpx_cpuhi_inv_data ;
 
wire  [13:0]      cpx_cpuhi_inv_data ;
 
//wire  [`STB_PCX_WIDTH-1:0]  stb_pcx_pkt ;
 
//wire  [`STB_PCX_WIDTH-1:0]  stb_pcx_pkt ;
 
//wire  [`STB_DFQ_WIDTH-1:0]  stb_dfq_pkt_data ;
 
//wire  [`STB_DFQ_WIDTH-1:0]  stb_dfq_pkt_data ;
 
wire  [83-1:0]  stb_dfq_data_in ;
 
wire  [`STB_DFQ_WIDTH-1:0]  stb_dfq_data_in ;
 
//wire  [`DFQ_WIDTH-1:0]  cpx_dfq_data ;
 
//wire  [`DFQ_WIDTH-1:0]  cpx_dfq_data ;
 
//wire  [`DFQ_WIDTH-1:0]  cpx_dfq_data_d1 ;
 
//wire  [`DFQ_WIDTH-1:0]  cpx_dfq_data_d1 ;
 
//wire  [`CPX_WIDTH-1:0]  cpx_data_cx_d1 ;
 
//wire  [`CPX_WIDTH-1:0]  cpx_data_cx_d1 ;
 
//wire        cpx_st_cmplt_d1 ;
 
//wire        cpx_st_cmplt_d1 ;
 
wire  [151:0]  dfq_byp_mx_data ;
 
wire  [`DFQ_WIDTH:0]  dfq_byp_mx_data ;
 
wire  [151-1:0]    dfq_byp_ff_data ;
 
wire  [`DFQ_WIDTH-1:0]    dfq_byp_ff_data ;
 
//wire  [`STB_DFQ_WIDTH-1:0]  store_dfq_pkt ;
 
//wire  [`STB_DFQ_WIDTH-1:0]  store_dfq_pkt ;
 
wire  [127:0]   st_dcfill_data ;
 
wire  [127:0]   st_dcfill_data ;
 
wire  [63:0]      dcache_wr_data ;
 
wire  [63:0]      dcache_wr_data ;
 
wire  [127:0]   ldinv_dcfill_data ;
 
wire  [127:0]   ldinv_dcfill_data ;
 
//wire  [`LMQ_WIDTH-1:0]  lmq0_pcx_pkt, lmq1_pcx_pkt ;
 
//wire  [`LMQ_WIDTH-1:0]  lmq0_pcx_pkt, lmq1_pcx_pkt ;
Line 1639... Line 228... 
wire  [107:0]     cpx_fwd_pkt_din ;
 
wire  [107:0]     cpx_fwd_pkt_din ;
 
 
 
 
 
//wire [3:0]     bist_rsel_way_m ;
 
//wire [3:0]     bist_rsel_way_m ;
 
//wire [3:0]     lsu_bist_rsel_way_wb ;  // way select for read
 
//wire [3:0]     lsu_bist_rsel_way_wb ;  // way select for read
 
wire  [1:0]  cpx_st_dcfill_wrway;
 
wire  [1:0]  cpx_st_dcfill_wrway;
 
wire  [82:0]   stb_dcfill_data_mx;
 
wire  [`STB_DFQ_VLD:0]   stb_dcfill_data_mx;
 
wire           clk;
 
wire           clk;
 
wire  [13:0]            lsu_cpu_inv_data ;
 
wire  [13:0]            lsu_cpu_inv_data ;
 
 
 
 
 
assign  clk = rclk;
 
assign  clk = rclk;
 
 
 
 
Line 1669... Line 258... 
//assign  stb_pcx_pkt[`STB_PCX_DA_HI:`STB_PCX_DA_LO] = 
//assign  stb_pcx_pkt[`STB_PCX_DA_HI:`STB_PCX_DA_LO] = 
//      stb_rdata_ramd[63:0];         // Data   
//      stb_rdata_ramd[63:0];         // Data   
 
 
 
 
// STB to DFQ Data Formatting
 
// STB to DFQ Data Formatting
 
// THREAD0
 
// THREAD0
 
assign  stb_dfq_data_in[83-1:0] =
 
assign  stb_dfq_data_in[`STB_DFQ_WIDTH-1:0] =
 
  {lsu_stb_pcx_rvld_d1,                         // 82:82 vld  //stb_pcx_pkt[`STB_PCX_VLD],
 
  {lsu_stb_pcx_rvld_d1,                         // 82:82 vld  //stb_pcx_pkt[`STB_PCX_VLD],
 
  stb_rdata_ramd_b74_buf,                           // 81:81 ??   //stb_rdata_ramd[74],
 
  stb_rdata_ramd_b74_buf,                           // 81:81 ??   //stb_rdata_ramd[74],
 
  2'b00,                                        // 80:79 not used
 
  2'b00,                                        // 80:79 not used
 
  //stb_pcx_pkt[`STB_PCX_WY_HI:`STB_PCX_WY_LO],
 
  //stb_pcx_pkt[`STB_PCX_WY_HI:`STB_PCX_WY_LO],
 
  3'b000,                                       // 78:76 instead of stb_dfq_rd_id[2:0],
 
  3'b000,                                       // 78:76 instead of stb_dfq_rd_id[2:0],
Line 1685... Line 274... 
// STB DATA BYPASS FLOP
 
// STB DATA BYPASS FLOP
 
// Data is read out on read for pcx. The data is then
 
// Data is read out on read for pcx. The data is then
 
// bypassed to the dfq when the st-ack is received.
 
// bypassed to the dfq when the st-ack is received.
 
//wire  [3:0]   pcx_rq_for_stb_d1;
 
//wire  [3:0]   pcx_rq_for_stb_d1;
 
wire  [3:0]   clk_stb_data;
 
wire  [3:0]   clk_stb_data;
 
wire  [82:0]  stb_dfq_pkt_data0,
 
wire  [`STB_DFQ_VLD:0]  stb_dfq_pkt_data0,
 
                        stb_dfq_pkt_data1,
 
                        stb_dfq_pkt_data1,
 
                        stb_dfq_pkt_data2,
 
                        stb_dfq_pkt_data2,
 
                        stb_dfq_pkt_data3;
 
                        stb_dfq_pkt_data3;
 
 
 
 
 
// timing fix: 9/15/03 - reduce loading on pcx_rq_for_stb[3:0] to stb_clt[0-3]. it had FO2 (stb_ctl,qdp2 - cap=0.5-0.8)
 
// timing fix: 9/15/03 - reduce loading on pcx_rq_for_stb[3:0] to stb_clt[0-3]. it had FO2 (stb_ctl,qdp2 - cap=0.5-0.8)
Line 1698... Line 287... 
//flop pcx rq to read stb data
 
//flop pcx rq to read stb data
 
//dff  #(4) pcx_rq_for_stb_ff (                       
//dff  #(4) pcx_rq_for_stb_ff (                       
//           .din  (pcx_rq_for_stb[3:0]),
 
//           .din  (pcx_rq_for_stb[3:0]),
 
//           .q    (pcx_rq_for_stb_d1[3:0]),
 
//           .q    (pcx_rq_for_stb_d1[3:0]),
 
//           .clk  (clk), 
//           .clk  (clk), 
//           .se   (1'b0),       .si (),          .so ());                                
//           .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ());                                
 
 
 
 
//dffe  #(83) stb_dfq_byp_ff (
 
//dffe  #(83) stb_dfq_byp_ff (
 
//        .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]), 
//        .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]), 
//  .q    (stb_dfq_pkt_data[`STB_DFQ_VLD:0]),
 
//  .q    (stb_dfq_pkt_data[`STB_DFQ_VLD:0]),
 
//        .en   (lsu_stb_dfq_rvld), .clk (clk),
 
//        .en   (lsu_stb_dfq_rvld), .clk (clk),
 
//        .se     (1'b0),       .si (),          .so ()
 
//        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
 
//        );
 
//        );
 
 
 
 
 
//THREAD0
 
//THREAD0
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf stb_dfq_byp0_clken(
 
 
 
          .clk(clk_stb_data[0]),
 
 
 
          .rclk(clk),
 
 
 
          .enb_l(~pcx_rq_for_stb_d1[0]),
 
 
 
          .tmb_l(~se));
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
dffe  #(83) stb_dfq_byp0_ff (
 
dffe_s  #(83) stb_dfq_byp0_ff (
 
           .din  (stb_dfq_data_in[82:0]),
 
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
 
           .q    (stb_dfq_pkt_data0[82:0]),
 
           .q    (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),
 
           .en (~(~pcx_rq_for_stb_d1[0])), .clk(clk),
 
           .en (~(~pcx_rq_for_stb_d1[0])), .clk(clk),
 
           .se   (1'b0),       .si (),          .so ());
 
           .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ());
 
 
 
`else
 
 
 
dff_s  #(83) stb_dfq_byp0_ff (
 
 
 
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
 
 
 
           .q    (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),
 
 
 
           .clk  (clk_stb_data[0]),
 
 
 
           .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ());
 
 
 
`endif
 
 
 
 
 
//THREAD1
 
//THREAD1
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf stb_dfq_byp1_clken(
 
 
 
          .clk(clk_stb_data[1]),
 
 
 
          .rclk(clk),
 
 
 
          .enb_l(~pcx_rq_for_stb_d1[1]),
 
 
 
          .tmb_l(~se));
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
dffe  #(83) stb_dfq_byp1_ff (
 
dffe_s  #(83) stb_dfq_byp1_ff (
 
           .din  (stb_dfq_data_in[82:0]),
 
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
 
           .q    (stb_dfq_pkt_data1[82:0]),
 
           .q    (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),
 
           .en (~(~pcx_rq_for_stb_d1[1])), .clk(clk),
 
           .en (~(~pcx_rq_for_stb_d1[1])), .clk(clk),
 
           .se   (1'b0),       .si (),          .so ());
 
           .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ());
 
 
 
`else
 
 
 
dff_s  #(83) stb_dfq_byp1_ff (
 
 
 
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
 
 
 
           .q    (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),
 
 
 
           .clk  (clk_stb_data[1]),
 
 
 
           .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ());
 
 
 
`endif
 
 
 
 
 
//THREAD2
 
//THREAD2
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf stb_dfq_byp2_clken(
 
 
 
          .clk(clk_stb_data[2]),
 
 
 
          .rclk(clk),
 
 
 
          .enb_l(~pcx_rq_for_stb_d1[2]),
 
 
 
          .tmb_l(~se));
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
dffe  #(83) stb_dfq_byp2_ff (
 
dffe_s  #(83) stb_dfq_byp2_ff (
 
           .din  (stb_dfq_data_in[82:0]),
 
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
 
           .q    (stb_dfq_pkt_data2[82:0]),
 
           .q    (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),
 
           .en (~(~pcx_rq_for_stb_d1[2])), .clk(clk),
 
           .en (~(~pcx_rq_for_stb_d1[2])), .clk(clk),
 
           .se   (1'b0),       .si (),          .so ());
 
           .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ());
 
 
 
`else
 
 
 
dff_s  #(83) stb_dfq_byp2_ff (
 
 
 
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
 
 
 
           .q    (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),
 
 
 
           .clk  (clk_stb_data[2]),
 
 
 
           .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ());
 
 
 
`endif
 
 
 
 
 
//THREAD3
 
//THREAD3
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf stb_dfq_byp3_clken(
 
 
 
          .clk(clk_stb_data[3]),
 
 
 
          .rclk(clk),
 
 
 
          .enb_l(~pcx_rq_for_stb_d1[3]),
 
 
 
          .tmb_l(~se));
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
dffe  #(83) stb_dfq_byp3_ff (
 
dffe_s  #(83) stb_dfq_byp3_ff (
 
           .din  (stb_dfq_data_in[82:0]),
 
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
 
           .q    (stb_dfq_pkt_data3[82:0]),
 
           .q    (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),
 
           .en (~(~pcx_rq_for_stb_d1[3])), .clk(clk),
 
           .en (~(~pcx_rq_for_stb_d1[3])), .clk(clk),
 
           .se   (1'b0),       .si (),          .so ());
 
           .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ());
 
 
 
`else
 
 
 
dff_s  #(83) stb_dfq_byp3_ff (
 
 
 
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
 
 
 
           .q    (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),
 
 
 
           .clk  (clk_stb_data[3]),
 
 
 
           .se   (1'b0),       `SIMPLY_RISC_SCANIN,          .so ());
 
 
 
`endif
 
 
 
 
 
// MUX the store data if cpx_pkt==st_ack w/ dcfill vld=1
 
// MUX the store data if cpx_pkt==st_ack w/ dcfill vld=1
 
mux4ds  #(82+1) stb_data_mx (
 
mux4ds  #(`STB_DFQ_VLD+1) stb_data_mx (
 
  .in0  (stb_dfq_pkt_data0[82:0]),
 
  .in0  (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),
 
  .in1  (stb_dfq_pkt_data1[82:0]),
 
  .in1  (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),
 
  .in2  (stb_dfq_pkt_data2[82:0]),
 
  .in2  (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),
 
  .in3  (stb_dfq_pkt_data3[82:0]),
 
  .in3  (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),
 
  .sel0 (lsu_cpx_thrdid[0]),
 
  .sel0 (lsu_cpx_thrdid[0]),
 
  .sel1 (lsu_cpx_thrdid[1]),
 
  .sel1 (lsu_cpx_thrdid[1]),
 
  .sel2 (lsu_cpx_thrdid[2]),
 
  .sel2 (lsu_cpx_thrdid[2]),
 
  .sel3 (lsu_cpx_thrdid[3]),
 
  .sel3 (lsu_cpx_thrdid[3]),
 
  .dout (stb_dcfill_data_mx[82:0])
 
  .dout (stb_dcfill_data_mx[`STB_DFQ_VLD:0])
 
);
 
);
 
 
 
 
 
//NOTE: mux this raw data w/ modified data to generate dfq input and feed into dfq_wdata
 
//NOTE: mux this raw data w/ modified data to generate dfq input and feed into dfq_wdata
 
 
 
 
 
 
 
 
Line 1865... Line 454... 
 
 
 
 
// Formatted to contain fwd req which is of largest size.
 
// Formatted to contain fwd req which is of largest size.
 
// Truncate address !!! 40b should not be required.
 
// Truncate address !!! 40b should not be required.
 
assign  cpx_fwd_pkt_din[107:0] =
 
assign  cpx_fwd_pkt_din[107:0] =
 
  {
 
  {
 
  cpx_spc_data_cx[136], // r/!w   (1b)
 
  cpx_spc_data_cx[`CPX_NC], // r/!w   (1b)
 
  cpx_spc_data_cx[133:131], // src/tar  (3b)
 
  cpx_spc_data_cx[133:131], // src/tar  (3b)
 
  cpx_spc_data_cx[103:0]    // 64b data + 40b addr (104b)
 
  cpx_spc_data_cx[103:0]    // 64b data + 40b addr (104b)
 
  } ;
 
  } ;
 
 
 
 
 
// Contains cpx fwd reply or req
 
// Contains cpx fwd reply or req
 
//dffe  #(108) fwdpkt_ff  (
 
//dffe  #(108) fwdpkt_ff  (
 
//        .din  (cpx_fwd_pkt_din[107:0]), 
//        .din  (cpx_fwd_pkt_din[107:0]), 
//  .q    (lsu_pcx_fwd_pkt[107:0]),
 
//  .q    (lsu_pcx_fwd_pkt[107:0]),
 
//        .en   (cpx_fwd_pkt_en_cx), 
//        .en   (cpx_fwd_pkt_en_cx), 
//  .clk  (clk),
 
//  .clk  (clk),
 
//        .se     (1'b0),       .si (),          .so ()
 
//        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
 
//        );
 
//        );
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf fwdpkt_clken(
 
 
 
          .clk(clk_cpx_fwd_pkt_en_cx),
 
 
 
          .rclk(clk),
 
 
 
          .enb_l(~cpx_fwd_pkt_en_cx),
 
 
 
          .tmb_l(~se));
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
 
 
dffe_s  #(108) fwdpkt_ff  (
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
dffe  #(108) fwdpkt_ff  (
 
 
 
            .din  (cpx_fwd_pkt_din[107:0]),
 
            .din  (cpx_fwd_pkt_din[107:0]),
 
            .q    (lsu_pcx_fwd_pkt[107:0]),
 
            .q    (lsu_pcx_fwd_pkt[107:0]),
 
            .en (~(~cpx_fwd_pkt_en_cx)), .clk(clk),
 
            .en (~(~cpx_fwd_pkt_en_cx)), .clk(clk),
 
            .se     (1'b0),       .si (),          .so ());
 
            .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ());
 
 
 
`else
 
 
 
dff_s  #(108) fwdpkt_ff  (
 
 
 
            .din  (cpx_fwd_pkt_din[107:0]),
 
 
 
            .q    (lsu_pcx_fwd_pkt[107:0]),
 
 
 
            .clk  (clk_cpx_fwd_pkt_en_cx),
 
 
 
            .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ());
 
 
 
`endif
 
 
 
 
 
 
 
 
 
// New mapping for address bits given that tag is gone. (OBSOLETE)
 
// New mapping for address bits given that tag is gone. (OBSOLETE)
 
// pkt[74:73] - Way
 
// pkt[74:73] - Way
 
// pkt[72:65] - Set Index
 
// pkt[72:65] - Set Index
Line 1944... Line 533... 
// to be written to dfq if bypass full else wr to byp mx.
 
// to be written to dfq if bypass full else wr to byp mx.
 
//assign  dfq_wdata[`DFQ_WIDTH:0] = 
//assign  dfq_wdata[`DFQ_WIDTH:0] = 
//  {lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],cpx_spc_data_cx[`CPX_WIDTH-1:0]};
 
//  {lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],cpx_spc_data_cx[`CPX_WIDTH-1:0]};
 
//  //{{(`DFQ_WIDTH-`CPX_WIDTH)1'b0},cpx_spc_data_cx[`CPX_WIDTH-1:0]},
 
//  //{{(`DFQ_WIDTH-`CPX_WIDTH)1'b0},cpx_spc_data_cx[`CPX_WIDTH-1:0]},
 
 
 
 
 
wire  [151:0]  dfq_st_data,dfq_cpx_raw_wdata;
 
wire  [`DFQ_WIDTH:0]  dfq_st_data,dfq_cpx_raw_wdata;
 
wire  [1:0]           cpx_st_ack_addr_b54;
 
wire  [1:0]           cpx_st_ack_addr_b54;
 
 
 
 
 
assign  dfq_cpx_raw_wdata[151:0] =
 
assign  dfq_cpx_raw_wdata[`DFQ_WIDTH:0] =
 
  {lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],cpx_spc_data_cx[145-1:0]};
 
  {lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],cpx_spc_data_cx[`CPX_WIDTH-1:0]};
 
 
 
 
 
assign  dfq_st_data[151:0]  =
 
assign  dfq_st_data[`DFQ_WIDTH:0]  =
 
        {lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],
 
        {lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],
 
         cpx_spc_data_cx[145-1:87],
 
         cpx_spc_data_cx[`CPX_WIDTH-1:87],
 
         cpx_st_ack_addr_b54[1:0],             // 86:85
 
         cpx_st_ack_addr_b54[1:0],             // 86:85
 
         cpx_st_dcfill_wrway[1:0],             // 84:83
 
         cpx_st_dcfill_wrway[1:0],             // 84:83
 
         stb_dcfill_data_mx[82:0]};  // 82:0
 
         stb_dcfill_data_mx[`STB_DFQ_VLD:0]};  // 82:0
 
 
 
 
 
mux2ds  #(151+1) dfq_st_data_mx (
 
mux2ds  #(`DFQ_WIDTH+1) dfq_st_data_mx (
 
  .in0  (dfq_st_data[151:0]),
 
  .in0  (dfq_st_data[`DFQ_WIDTH:0]),
 
  .in1  (dfq_cpx_raw_wdata[151:0]),
 
  .in1  (dfq_cpx_raw_wdata[`DFQ_WIDTH:0]),
 
  .sel0 (lsu_cpx_stack_dcfill_vld),
 
  .sel0 (lsu_cpx_stack_dcfill_vld),
 
  .sel1 (~lsu_cpx_stack_dcfill_vld),
 
  .sel1 (~lsu_cpx_stack_dcfill_vld),
 
  .dout (dfq_wdata[151:0])
 
  .dout (dfq_wdata[`DFQ_WIDTH:0])
 
);
 
);
 
 
 
 
 
//timing fix: 05/31/03: decouple byp mux from lsu_cpx_stack_dcfill_vld
 
//timing fix: 05/31/03: decouple byp mux from lsu_cpx_stack_dcfill_vld
 
//            i.e. replace dfq_wdata w/ dfq_cpx_raw_wdata in byp mux
 
//            i.e. replace dfq_wdata w/ dfq_cpx_raw_wdata in byp mux
 
// select between dfq output and cpx bypass.
 
// select between dfq output and cpx bypass.
 
mux2ds  #(151+1) dfq_byp_mx (
 
mux2ds  #(`DFQ_WIDTH+1) dfq_byp_mx (
 
  .in0  (dfq_rdata[151:0]),
 
  .in0  (dfq_rdata[`DFQ_WIDTH:0]),
 
  .in1  (dfq_cpx_raw_wdata[151:0]),
 
  .in1  (dfq_cpx_raw_wdata[`DFQ_WIDTH:0]),
 
  .sel0 (dfq_rd_vld_d1),
 
  .sel0 (dfq_rd_vld_d1),
 
  .sel1 (~dfq_rd_vld_d1),
 
  .sel1 (~dfq_rd_vld_d1),
 
  .dout (dfq_byp_mx_data[151:0])
 
  .dout (dfq_byp_mx_data[`DFQ_WIDTH:0])
 
);
 
);
 
 
 
 
 
assign  lsu_dfq_byp_cpx_inv     =   dfq_byp_mx_data[151];
 
assign  lsu_dfq_byp_cpx_inv     =   dfq_byp_mx_data[`DFQ_WIDTH];
 
assign  lsu_dfq_byp_tid[1:0]    =   dfq_byp_mx_data[135:134] ;
 
assign  lsu_dfq_byp_tid[1:0]    =   dfq_byp_mx_data[`CPX_TH_HI:`CPX_TH_LO] ;
 
//assign  lsu_dfq_byp_cpuid[2:0]  =   dfq_byp_mx_data[`CPX_INV_CID_HI:`CPX_INV_CID_LO] ;
 
//assign  lsu_dfq_byp_cpuid[2:0]  =   dfq_byp_mx_data[`CPX_INV_CID_HI:`CPX_INV_CID_LO] ;
 
assign  lsu_dfq_byp_flush =     dfq_byp_mx_data[136] ;
 
assign  lsu_dfq_byp_flush =     dfq_byp_mx_data[`CPX_NC] ;
 
assign  lsu_dfq_byp_invwy_vld = dfq_byp_mx_data[133] ;
 
assign  lsu_dfq_byp_invwy_vld = dfq_byp_mx_data[`CPX_WYVLD] ;
 
 
 
 
 
//assign  lsu_dfq_byp_type[5:0]   =   dfq_byp_mx_data[`DFQ_WIDTH-1:`DFQ_WIDTH-6] ;
 
//assign  lsu_dfq_byp_type[5:0]   =   dfq_byp_mx_data[`DFQ_WIDTH-1:`DFQ_WIDTH-6] ;
 
assign  lsu_dfq_byp_type[5:3]   =   dfq_byp_mx_data[151-1:151-3] ;
 
assign  lsu_dfq_byp_type[5:3]   =   dfq_byp_mx_data[`DFQ_WIDTH-1:`DFQ_WIDTH-3] ;
 
assign  lsu_dfq_byp_type[2]   =   dfq_byp_mx_data[151-4] & dfq_rd_vld_d1;
 
assign  lsu_dfq_byp_type[2]   =   dfq_byp_mx_data[`DFQ_WIDTH-4] & dfq_rd_vld_d1;
 
assign  lsu_dfq_byp_type[1:0]   =   dfq_byp_mx_data[151-5:151-6] ;
 
assign  lsu_dfq_byp_type[1:0]   =   dfq_byp_mx_data[`DFQ_WIDTH-5:`DFQ_WIDTH-6] ;
 
 
 
 
 
//assign  lsu_dfq_byp_stquad_pkt2 =   dfq_byp_mx_data[130] ;
 
//assign  lsu_dfq_byp_stquad_pkt2 =   dfq_byp_mx_data[130] ;
 
assign  lsu_dfq_byp_binit_st =   dfq_byp_mx_data[125] ;
 
assign  lsu_dfq_byp_binit_st =   dfq_byp_mx_data[125] ;
 
//assign  lsu_dfq_byp_perror_iinv    = dfq_byp_mx_data[`CPX_PERR_DINV+1] ;
 
//assign  lsu_dfq_byp_perror_iinv    = dfq_byp_mx_data[`CPX_PERR_DINV+1] ;
 
//assign  lsu_dfq_byp_perror_dinv    = dfq_byp_mx_data[`CPX_PERR_DINV] ;
 
//assign  lsu_dfq_byp_perror_dinv    = dfq_byp_mx_data[`CPX_PERR_DINV] ;
 
//assign  lsu_dfq_byp_stack_dcfill_vld =   dfq_byp_mx_data[87] ;
 
//assign  lsu_dfq_byp_stack_dcfill_vld =   dfq_byp_mx_data[87] ;
 
assign  lsu_dfq_byp_stack_adr_b54[1:0] =   dfq_byp_mx_data[86:85] ;
 
assign  lsu_dfq_byp_stack_adr_b54[1:0] =   dfq_byp_mx_data[86:85] ;
 
assign  lsu_dfq_byp_stack_wrway[1:0] =   dfq_byp_mx_data[84:83] ;
 
assign  lsu_dfq_byp_stack_wrway[1:0] =   dfq_byp_mx_data[84:83] ;
 
 
 
 
 
assign  lsu_ifill_pkt[144-1:0] = dfq_byp_mx_data[144-1:0] ;
 
assign  lsu_ifill_pkt[`CPX_VLD-1:0] = dfq_byp_mx_data[`CPX_VLD-1:0] ;
 
//assign  lsu_ifill_pkt[`CPX_WIDTH-1:0] = {lsu_ifill_pkt_vld,dfq_byp_mx_data[`CPX_VLD-1:0]} ;
 
//assign  lsu_ifill_pkt[`CPX_WIDTH-1:0] = {lsu_ifill_pkt_vld,dfq_byp_mx_data[`CPX_VLD-1:0]} ;
 
 
 
 
 
assign  lsu_dfq_byp_atm  = dfq_byp_mx_data[129] ;
 
assign  lsu_dfq_byp_atm  = dfq_byp_mx_data[129] ;
 
 
 
 
 
// Decode in qctl !!!
 
// Decode in qctl !!!
Line 2011... Line 600... 
// byp ff until pkt completely utilized.
 
// byp ff until pkt completely utilized.
 
//dffe  #(`DFQ_WIDTH) dfq_data_stg (
 
//dffe  #(`DFQ_WIDTH) dfq_data_stg (
 
//        .din  (dfq_byp_mx_data[`DFQ_WIDTH-1:0]),
 
//        .din  (dfq_byp_mx_data[`DFQ_WIDTH-1:0]),
 
//  .q    (dfq_byp_ff_data[`DFQ_WIDTH-1:0]),
 
//  .q    (dfq_byp_ff_data[`DFQ_WIDTH-1:0]),
 
//        .en (dfq_byp_ff_en),  .clk  (clk),
 
//        .en (dfq_byp_ff_en),  .clk  (clk),
 
//        .se     (1'b0),     .si (),          .so ()
 
//        .se     (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
 
//);
 
//);
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_EN
 
 
 
`else
 
 
 
clken_buf dfq_byp_ff_en_clken(
 
 
 
          .clk(clk_dfq_byp_ff_en),
 
 
 
          .rclk(clk),
 
 
 
          .enb_l(~dfq_byp_ff_en),
 
 
 
          .tmb_l(~se));
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef FPGA_SYN_CLK_DFF
 
dffe  #(151) dfq_data_stg (
 
dffe_s  #(`DFQ_WIDTH) dfq_data_stg (
 
                  .din  (dfq_byp_mx_data[151-1:0]),
 
                  .din  (dfq_byp_mx_data[`DFQ_WIDTH-1:0]),
 
                  .q    (dfq_byp_ff_data[151-1:0]),
 
                  .q    (dfq_byp_ff_data[`DFQ_WIDTH-1:0]),
 
                  .en (~(~dfq_byp_ff_en)), .clk(clk),
 
                  .en (~(~dfq_byp_ff_en)), .clk(clk),
 
                  .se   (1'b0),     .si (),          .so ());
 
                  .se   (1'b0),     `SIMPLY_RISC_SCANIN,          .so ());
 
 
 
`else
 
 
 
dff_s  #(`DFQ_WIDTH) dfq_data_stg (
 
 
 
                  .din  (dfq_byp_mx_data[`DFQ_WIDTH-1:0]),
 
 
 
                  .q    (dfq_byp_ff_data[`DFQ_WIDTH-1:0]),
 
 
 
                  .clk  (clk_dfq_byp_ff_en),
 
 
 
                  .se   (1'b0),     `SIMPLY_RISC_SCANIN,          .so ());
 
 
 
`endif
 
 
 
 
 
 
 
 
 
// To be decoded in qctl
 
// To be decoded in qctl
 
//assign  lsu_st_cmplt_type = dfq_byp_ff_data[`DFQ_ST_CMPLT];
 
//assign  lsu_st_cmplt_type = dfq_byp_ff_data[`DFQ_ST_CMPLT];
 
 
 
 
 
assign  dfq_tid[1:0] = dfq_byp_ff_data[135:134] ;
 
assign  dfq_tid[1:0] = dfq_byp_ff_data[`CPX_TH_HI:`CPX_TH_LO] ;
 
 
 
 
 
output    lsu_cpx_pkt_ifill_type;
 
output    lsu_cpx_pkt_ifill_type;
 
output    lsu_cpx_pkt_atomic ;
 
output    lsu_cpx_pkt_atomic ;
 
 
 
 
 
// Should some of these be in-flight ?
 
// Should some of these be in-flight ?
 
//assign  lsu_cpx_pkt_rqtype[3:0]   = dfq_byp_ff_data[`CPX_RQ_HI:`CPX_RQ_LO] ;
 
//assign  lsu_cpx_pkt_rqtype[3:0]   = dfq_byp_ff_data[`CPX_RQ_HI:`CPX_RQ_LO] ;
 
assign  lsu_cpx_pkt_ifill_type    = dfq_byp_ff_data[151-2];
 
assign  lsu_cpx_pkt_ifill_type    = dfq_byp_ff_data[`DFQ_WIDTH-2];
 
assign  lsu_cpx_pkt_tid[1:0]      = dfq_byp_ff_data[135:134] ;
 
assign  lsu_cpx_pkt_tid[1:0]      = dfq_byp_ff_data[`CPX_TH_HI:`CPX_TH_LO] ;
 
assign  lsu_cpx_pkt_vld     = dfq_byp_ff_data[144] ;
 
assign  lsu_cpx_pkt_vld     = dfq_byp_ff_data[`CPX_VLD] ;
 
assign  lsu_cpx_pkt_atm_st_cmplt  = dfq_byp_ff_data[129] ;
 
assign  lsu_cpx_pkt_atm_st_cmplt  = dfq_byp_ff_data[129] ;
 
assign  lsu_cpx_pkt_invwy[1:0]    = dfq_byp_ff_data[132:131] ;
 
assign  lsu_cpx_pkt_invwy[1:0]    = dfq_byp_ff_data[`CPX_WY_HI:`CPX_WY_LO] ;
 
// Upper 6bits are used to store decoded request type information.
 
// Upper 6bits are used to store decoded request type information.
 
assign  lsu_cpx_pkt_strm_ack   = dfq_byp_ff_data[151-5];
 
assign  lsu_cpx_pkt_strm_ack   = dfq_byp_ff_data[`DFQ_WIDTH-5];
 
//assign  lsu_cpx_pkt_inv_pa[4:0]   = dfq_byp_ff_data[`CPX_INV_PA_HI-1:`CPX_INV_PA_LO];  //!!
 
//assign  lsu_cpx_pkt_inv_pa[4:0]   = dfq_byp_ff_data[`CPX_INV_PA_HI-1:`CPX_INV_PA_LO];  //!!
 
assign  lsu_cpx_pkt_inv_pa[4:0]   = dfq_byp_ff_data[116:112];
 
assign  lsu_cpx_pkt_inv_pa[4:0]   = dfq_byp_ff_data[`CPX_INV_PA_HI:`CPX_INV_PA_LO];
 
assign  lsu_cpx_pkt_atomic    = dfq_byp_ff_data[129]  | //atomic st ack
 
assign  lsu_cpx_pkt_atomic    = dfq_byp_ff_data[129]  | //atomic st ack
 
            dfq_byp_ff_data[131]  ; //stquad pkt1
 
            dfq_byp_ff_data[131]  ; //stquad pkt1
 
//assign  lsu_cpx_pkt_stquad_pkt2   = dfq_byp_ff_data[130] ;
 
//assign  lsu_cpx_pkt_stquad_pkt2   = dfq_byp_ff_data[130] ;
 
assign  lsu_cpx_pkt_binit_st   = dfq_byp_ff_data[125] ;
 
assign  lsu_cpx_pkt_binit_st   = dfq_byp_ff_data[125] ;
 
assign  lsu_cpx_pkt_prefetch = dfq_byp_ff_data[128] ; // for qctl2
 
assign  lsu_cpx_pkt_prefetch = dfq_byp_ff_data[128] ; // for qctl2
 
assign  lsu_cpx_pkt_prefetch2 = dfq_byp_ff_data[128] ;  // for dctl
 
assign  lsu_cpx_pkt_prefetch2 = dfq_byp_ff_data[128] ;  // for dctl
 
//assign        lsu_spu_strm_st = dfq_byp_ff_data[134] ; // strm store ack (vs. ma)
 
//assign        lsu_spu_strm_st = dfq_byp_ff_data[134] ; // strm store ack (vs. ma)
 
 
 
 
 
assign  lsu_cpx_pkt_perror_iinv    = dfq_byp_ff_data[123+1] ;
 
assign  lsu_cpx_pkt_perror_iinv    = dfq_byp_ff_data[`CPX_PERR_DINV+1] ;
 
assign  lsu_cpx_pkt_perror_dinv    = dfq_byp_ff_data[123] ;
 
assign  lsu_cpx_pkt_perror_dinv    = dfq_byp_ff_data[`CPX_PERR_DINV] ;
 
assign  lsu_cpx_pkt_perror_set[1:0] =
 
assign  lsu_cpx_pkt_perror_set[1:0] =
 
        dfq_byp_ff_data[122:121] ;
 
        dfq_byp_ff_data[`CPX_PERR_DINV_AD5:`CPX_PERR_DINV_AD4] ;
 
 
 
 
 
assign  lsu_cpx_pkt_ld_err[1:0] = dfq_byp_ff_data[138:137] ;
 
assign  lsu_cpx_pkt_ld_err[1:0] = dfq_byp_ff_data[138:137] ;
 
assign  lsu_cpx_pkt_l2miss = dfq_byp_ff_data[139] ;
 
assign  lsu_cpx_pkt_l2miss = dfq_byp_ff_data[139] ;
 
 
 
 
 
 
 
 
Line 2080... Line 669... 
//      DFQ OUTPUT - LOCAL PROCESSING
 
//      DFQ OUTPUT - LOCAL PROCESSING
 
//=================================================================================================
 
//=================================================================================================
 
 
 
 
 
 
 
 
 
mux4ds  #(14) invfld_lo_sel (
 
mux4ds  #(14) invfld_lo_sel (
 
        .in0    ({dfq_byp_mx_data[90:88],
 
        .in0    ({dfq_byp_mx_data[`CPX_A11_C0_HI:`CPX_A11_C0_LO],
 
                  dfq_byp_mx_data[59:56],
 
                  dfq_byp_mx_data[`CPX_A10_C0_HI:`CPX_A10_C0_LO],
 
                  dfq_byp_mx_data[34:32],
 
                  dfq_byp_mx_data[`CPX_A01_C0_HI:`CPX_A01_C0_LO],
 
                  dfq_byp_mx_data[3:0]}),
 
                  dfq_byp_mx_data[`CPX_A00_C0_HI:`CPX_A00_C0_LO]}),
 
        .in1    ({dfq_byp_mx_data[93:91],
 
        .in1    ({dfq_byp_mx_data[`CPX_A11_C1_HI:`CPX_A11_C1_LO],
 
                  dfq_byp_mx_data[63:60],
 
                  dfq_byp_mx_data[`CPX_A10_C1_HI:`CPX_A10_C1_LO],
 
                  dfq_byp_mx_data[37:35],
 
                  dfq_byp_mx_data[`CPX_A01_C1_HI:`CPX_A01_C1_LO],
 
                  dfq_byp_mx_data[7:4]}),
 
                  dfq_byp_mx_data[`CPX_A00_C1_HI:`CPX_A00_C1_LO]}),
 
        .in2    ({dfq_byp_mx_data[96:94],
 
        .in2    ({dfq_byp_mx_data[`CPX_A11_C2_HI:`CPX_A11_C2_LO],
 
                  dfq_byp_mx_data[67:64],
 
                  dfq_byp_mx_data[`CPX_A10_C2_HI:`CPX_A10_C2_LO],
 
                  dfq_byp_mx_data[40:38],
 
                  dfq_byp_mx_data[`CPX_A01_C2_HI:`CPX_A01_C2_LO],
 
                  dfq_byp_mx_data[11:8]}),
 
                  dfq_byp_mx_data[`CPX_A00_C2_HI:`CPX_A00_C2_LO]}),
 
        .in3    ({dfq_byp_mx_data[99:97],
 
        .in3    ({dfq_byp_mx_data[`CPX_A11_C3_HI:`CPX_A11_C3_LO],
 
                  dfq_byp_mx_data[71:68],
 
                  dfq_byp_mx_data[`CPX_A10_C3_HI:`CPX_A10_C3_LO],
 
                  dfq_byp_mx_data[43:41],
 
                  dfq_byp_mx_data[`CPX_A01_C3_HI:`CPX_A01_C3_LO],
 
                  dfq_byp_mx_data[15:12]}),
 
                  dfq_byp_mx_data[`CPX_A00_C3_HI:`CPX_A00_C3_LO]}),
 
        .sel0   (lsu_cpu_dcd_sel[0]),
 
        .sel0   (lsu_cpu_dcd_sel[0]),
 
        .sel1   (lsu_cpu_dcd_sel[1]),
 
        .sel1   (lsu_cpu_dcd_sel[1]),
 
        .sel2   (lsu_cpu_dcd_sel[2]),
 
        .sel2   (lsu_cpu_dcd_sel[2]),
 
        .sel3   (lsu_cpu_dcd_sel[3]),
 
        .sel3   (lsu_cpu_dcd_sel[3]),
 
        .dout   (cpx_cpulo_inv_data[13:0])
 
        .dout   (cpx_cpulo_inv_data[13:0])
 
);
 
);
 
 
 
 
 
mux4ds  #(14) invfld_hi_sel (
 
mux4ds  #(14) invfld_hi_sel (
 
        .in0    ({dfq_byp_mx_data[102:100],
 
        .in0    ({dfq_byp_mx_data[`CPX_A11_C4_HI:`CPX_A11_C4_LO],
 
                  dfq_byp_mx_data[75:72],
 
                  dfq_byp_mx_data[`CPX_A10_C4_HI:`CPX_A10_C4_LO],
 
                  dfq_byp_mx_data[46:44],
 
                  dfq_byp_mx_data[`CPX_A01_C4_HI:`CPX_A01_C4_LO],
 
                  dfq_byp_mx_data[19:16]}),
 
                  dfq_byp_mx_data[`CPX_A00_C4_HI:`CPX_A00_C4_LO]}),
 
        .in1    ({dfq_byp_mx_data[105:103],
 
        .in1    ({dfq_byp_mx_data[`CPX_A11_C5_HI:`CPX_A11_C5_LO],
 
                  dfq_byp_mx_data[79:76],
 
                  dfq_byp_mx_data[`CPX_A10_C5_HI:`CPX_A10_C5_LO],
 
                  dfq_byp_mx_data[49:47],
 
                  dfq_byp_mx_data[`CPX_A01_C5_HI:`CPX_A01_C5_LO],
 
                  dfq_byp_mx_data[23:20]}),
 
                  dfq_byp_mx_data[`CPX_A00_C5_HI:`CPX_A00_C5_LO]}),
 
        .in2    ({dfq_byp_mx_data[108:106],
 
        .in2    ({dfq_byp_mx_data[`CPX_A11_C6_HI:`CPX_A11_C6_LO],
 
                  dfq_byp_mx_data[83:80],
 
                  dfq_byp_mx_data[`CPX_A10_C6_HI:`CPX_A10_C6_LO],
 
                  dfq_byp_mx_data[52:50],
 
                  dfq_byp_mx_data[`CPX_A01_C6_HI:`CPX_A01_C6_LO],
 
                  dfq_byp_mx_data[27:24]}),
 
                  dfq_byp_mx_data[`CPX_A00_C6_HI:`CPX_A00_C6_LO]}),
 
        .in3    ({dfq_byp_mx_data[111:109],
 
        .in3    ({dfq_byp_mx_data[`CPX_A11_C7_HI:`CPX_A11_C7_LO],
 
                  dfq_byp_mx_data[87:84],
 
                  dfq_byp_mx_data[`CPX_A10_C7_HI:`CPX_A10_C7_LO],
 
                  dfq_byp_mx_data[55:53],
 
                  dfq_byp_mx_data[`CPX_A01_C7_HI:`CPX_A01_C7_LO],
 
                  dfq_byp_mx_data[31:28]}),
 
                  dfq_byp_mx_data[`CPX_A00_C7_HI:`CPX_A00_C7_LO]}),
 
        .sel0   (lsu_cpu_dcd_sel[4]),
 
        .sel0   (lsu_cpu_dcd_sel[4]),
 
        .sel1   (lsu_cpu_dcd_sel[5]),
 
        .sel1   (lsu_cpu_dcd_sel[5]),
 
        .sel2   (lsu_cpu_dcd_sel[6]),
 
        .sel2   (lsu_cpu_dcd_sel[6]),
 
        .sel3   (lsu_cpu_dcd_sel[7]),
 
        .sel3   (lsu_cpu_dcd_sel[7]),
 
        .dout   (cpx_cpuhi_inv_data[13:0])
 
        .dout   (cpx_cpuhi_inv_data[13:0])
Line 2147... Line 736... 
             cpx_cpuhi_dcfill_wrway,
 
             cpx_cpuhi_dcfill_wrway,
 
             cpx_st_dcfill_wrway_sel;
 
             cpx_st_dcfill_wrway_sel;
 
 
 
 
 
 
 
 
 
mux4ds  #(14) st_dcfill_wrway_lo (
 
mux4ds  #(14) st_dcfill_wrway_lo (
 
        .in0    ({cpx_spc_data_cx[90:88],
 
        .in0    ({cpx_spc_data_cx[`CPX_A11_C0_HI:`CPX_A11_C0_LO],
 
                  cpx_spc_data_cx[59:56],
 
                  cpx_spc_data_cx[`CPX_A10_C0_HI:`CPX_A10_C0_LO],
 
                  cpx_spc_data_cx[34:32],
 
                  cpx_spc_data_cx[`CPX_A01_C0_HI:`CPX_A01_C0_LO],
 
                  cpx_spc_data_cx[3:0]}),
 
                  cpx_spc_data_cx[`CPX_A00_C0_HI:`CPX_A00_C0_LO]}),
 
        .in1    ({cpx_spc_data_cx[93:91],
 
        .in1    ({cpx_spc_data_cx[`CPX_A11_C1_HI:`CPX_A11_C1_LO],
 
                  cpx_spc_data_cx[63:60],
 
                  cpx_spc_data_cx[`CPX_A10_C1_HI:`CPX_A10_C1_LO],
 
                  cpx_spc_data_cx[37:35],
 
                  cpx_spc_data_cx[`CPX_A01_C1_HI:`CPX_A01_C1_LO],
 
                  cpx_spc_data_cx[7:4]}),
 
                  cpx_spc_data_cx[`CPX_A00_C1_HI:`CPX_A00_C1_LO]}),
 
        .in2    ({cpx_spc_data_cx[96:94],
 
        .in2    ({cpx_spc_data_cx[`CPX_A11_C2_HI:`CPX_A11_C2_LO],
 
                  cpx_spc_data_cx[67:64],
 
                  cpx_spc_data_cx[`CPX_A10_C2_HI:`CPX_A10_C2_LO],
 
                  cpx_spc_data_cx[40:38],
 
                  cpx_spc_data_cx[`CPX_A01_C2_HI:`CPX_A01_C2_LO],
 
                  cpx_spc_data_cx[11:8]}),
 
                  cpx_spc_data_cx[`CPX_A00_C2_HI:`CPX_A00_C2_LO]}),
 
        .in3    ({cpx_spc_data_cx[99:97],
 
        .in3    ({cpx_spc_data_cx[`CPX_A11_C3_HI:`CPX_A11_C3_LO],
 
                  cpx_spc_data_cx[71:68],
 
                  cpx_spc_data_cx[`CPX_A10_C3_HI:`CPX_A10_C3_LO],
 
                  cpx_spc_data_cx[43:41],
 
                  cpx_spc_data_cx[`CPX_A01_C3_HI:`CPX_A01_C3_LO],
 
                  cpx_spc_data_cx[15:12]}),
 
                  cpx_spc_data_cx[`CPX_A00_C3_HI:`CPX_A00_C3_LO]}),
 
        .sel0   (lsu_cpu_dcd_sel[0]),
 
        .sel0   (lsu_cpu_dcd_sel[0]),
 
        .sel1   (lsu_cpu_dcd_sel[1]),
 
        .sel1   (lsu_cpu_dcd_sel[1]),
 
        .sel2   (lsu_cpu_dcd_sel[2]),
 
        .sel2   (lsu_cpu_dcd_sel[2]),
 
        .sel3   (lsu_cpu_dcd_sel[3]),
 
        .sel3   (lsu_cpu_dcd_sel[3]),
 
        .dout   (cpx_cpulo_dcfill_wrway[13:0])
 
        .dout   (cpx_cpulo_dcfill_wrway[13:0])
 
);
 
);
 
 
 
 
 
mux4ds  #(14) st_dcfill_wrway_hi (
 
mux4ds  #(14) st_dcfill_wrway_hi (
 
        .in0    ({cpx_spc_data_cx[102:100],
 
        .in0    ({cpx_spc_data_cx[`CPX_A11_C4_HI:`CPX_A11_C4_LO],
 
                  cpx_spc_data_cx[75:72],
 
                  cpx_spc_data_cx[`CPX_A10_C4_HI:`CPX_A10_C4_LO],
 
                  cpx_spc_data_cx[46:44],
 
                  cpx_spc_data_cx[`CPX_A01_C4_HI:`CPX_A01_C4_LO],
 
                  cpx_spc_data_cx[19:16]}),
 
                  cpx_spc_data_cx[`CPX_A00_C4_HI:`CPX_A00_C4_LO]}),
 
        .in1    ({cpx_spc_data_cx[105:103],
 
        .in1    ({cpx_spc_data_cx[`CPX_A11_C5_HI:`CPX_A11_C5_LO],
 
                  cpx_spc_data_cx[79:76],
 
                  cpx_spc_data_cx[`CPX_A10_C5_HI:`CPX_A10_C5_LO],
 
                  cpx_spc_data_cx[49:47],
 
                  cpx_spc_data_cx[`CPX_A01_C5_HI:`CPX_A01_C5_LO],
 
                  cpx_spc_data_cx[23:20]}),
 
                  cpx_spc_data_cx[`CPX_A00_C5_HI:`CPX_A00_C5_LO]}),
 
        .in2    ({cpx_spc_data_cx[108:106],
 
        .in2    ({cpx_spc_data_cx[`CPX_A11_C6_HI:`CPX_A11_C6_LO],
 
                  cpx_spc_data_cx[83:80],
 
                  cpx_spc_data_cx[`CPX_A10_C6_HI:`CPX_A10_C6_LO],
 
                  cpx_spc_data_cx[52:50],
 
                  cpx_spc_data_cx[`CPX_A01_C6_HI:`CPX_A01_C6_LO],
 
                  cpx_spc_data_cx[27:24]}),
 
                  cpx_spc_data_cx[`CPX_A00_C6_HI:`CPX_A00_C6_LO]}),
 
        .in3    ({cpx_spc_data_cx[111:109],
 
        .in3    ({cpx_spc_data_cx[`CPX_A11_C7_HI:`CPX_A11_C7_LO],
 
                  cpx_spc_data_cx[87:84],
 
                  cpx_spc_data_cx[`CPX_A10_C7_HI:`CPX_A10_C7_LO],
 
                  cpx_spc_data_cx[55:53],
 
                  cpx_spc_data_cx[`CPX_A01_C7_HI:`CPX_A01_C7_LO],
 
                  cpx_spc_data_cx[31:28]}),
 
                  cpx_spc_data_cx[`CPX_A00_C7_HI:`CPX_A00_C7_LO]}),
 
        .sel0   (lsu_cpu_dcd_sel[4]),
 
        .sel0   (lsu_cpu_dcd_sel[4]),
 
        .sel1   (lsu_cpu_dcd_sel[5]),
 
        .sel1   (lsu_cpu_dcd_sel[5]),
 
        .sel2   (lsu_cpu_dcd_sel[6]),
 
        .sel2   (lsu_cpu_dcd_sel[6]),
 
        .sel3   (lsu_cpu_dcd_sel[7]),
 
        .sel3   (lsu_cpu_dcd_sel[7]),
 
        .dout   (cpx_cpuhi_dcfill_wrway[13:0])
 
        .dout   (cpx_cpuhi_dcfill_wrway[13:0])
Line 2253... Line 842... 
// Mux in diagnostic information. Only data is muxed in because
 
// Mux in diagnostic information. Only data is muxed in because
 
// all other info is critical
 
// all other info is critical
 
 
 
 
 
   wire [63:0] diagnstc_wr_data;
 
   wire [63:0] diagnstc_wr_data;
 
 
 
 
 
dff  #(64) diagnstc_wr_data_ff (
 
dff_s  #(64) diagnstc_wr_data_ff (
 
        .din    (lsu_diagnstc_wr_data_e[63:0]),
 
        .din    (lsu_diagnstc_wr_data_e[63:0]),
 
        .q      (diagnstc_wr_data[63:0]),
 
        .q      (diagnstc_wr_data[63:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (1'b0),     .si (),          .so ()
 
        .se     (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
mux2ds  #(64) dcwr_sel (
 
mux2ds  #(64) dcwr_sel (
 
  //.in0  ({store_dfq_pkt[`STB_DFQ_DA_HI:`STB_DFQ_DA_LO]}),
 
  //.in0  ({store_dfq_pkt[`STB_DFQ_DA_HI:`STB_DFQ_DA_LO]}),
 
  .in0  ({dfq_byp_ff_data[63:0]}),
 
  .in0  ({dfq_byp_ff_data[`STB_DFQ_DA_HI:`STB_DFQ_DA_LO]}),
 
  .in1  ({diagnstc_wr_data[63:0]}),
 
  .in1  ({diagnstc_wr_data[63:0]}),
 
  .sel0 ( lsu_dfq_st_vld),
 
  .sel0 ( lsu_dfq_st_vld),
 
  .sel1 (~lsu_dfq_st_vld),
 
  .sel1 (~lsu_dfq_st_vld),
 
  //.sel0 (~lsu_diagnstc_wr_src_sel_e),  
  //.sel0 (~lsu_diagnstc_wr_src_sel_e),  
  //.sel1 ( lsu_diagnstc_wr_src_sel_e),
 
  //.sel1 ( lsu_diagnstc_wr_src_sel_e),
Line 2290... Line 879... 
                                                               //dfq_byp_ff_data[`STB_DFQ_AD_LO+3:`STB_DFQ_AD_LO]}, // addr 3:0
 
                                                               //dfq_byp_ff_data[`STB_DFQ_AD_LO+3:`STB_DFQ_AD_LO]}, // addr 3:0
 
   dcache_wr_data[63:0],                            // 127:64
 
   dcache_wr_data[63:0],                            // 127:64
 
   dcache_wr_data[63:0]};                           // 63:0
 
   dcache_wr_data[63:0]};                           // 63:0
 
 
 
 
 
   assign st_dcfill_addr[10:0] =
 
   assign st_dcfill_addr[10:0] =
 
   {dfq_byp_ff_data[116:112],    // addr 10:6
 
   {dfq_byp_ff_data[`CPX_INV_PA_HI:`CPX_INV_PA_LO],    // addr 10:6
 
    dfq_byp_ff_data[86:85],                            // addr 5:4
 
    dfq_byp_ff_data[86:85],                            // addr 5:4
 
    dfq_byp_ff_data[64+3:64]}; // addr 3:0
 
    dfq_byp_ff_data[`STB_DFQ_AD_LO+3:`STB_DFQ_AD_LO]}; // addr 3:0
 
 
 
 
 
// lmq0_pcx_pkt will have to be brought in. Same for lmq_ld_addr
 
// lmq0_pcx_pkt will have to be brought in. Same for lmq_ld_addr
 
// The width can be reduced !!!
 
// The width can be reduced !!!
 
 
 
 
 
//potentially we can take one cycle earlier version dfq_st_data   
//potentially we can take one cycle earlier version dfq_st_data   
   assign lsu_st_way_e[1:0] = dfq_byp_ff_data[84:83];
 
   assign lsu_st_way_e[1:0] = dfq_byp_ff_data[84:83];
 
   assign lsu_st_dcfill_size_e [1:0] = dfq_byp_ff_data[75:74];
 
   assign lsu_st_dcfill_size_e [1:0] = dfq_byp_ff_data[`STB_DFQ_SZ_HI:`STB_DFQ_SZ_LO];
 
 
 
 
 
assign ldinv_dcfill_data[127:0] =
 
assign ldinv_dcfill_data[127:0] =
 
  {                                                            //1'b0,
 
  {                                                            //1'b0,
 
                                                               //dfq_byp_ff_data[`DFQ_TH_HI:`DFQ_TH_LO],
 
                                                               //dfq_byp_ff_data[`DFQ_TH_HI:`DFQ_TH_LO],
 
                                                               //dfq_byp_ff_data[`DFQ_LD_TYPE:`DFQ_INV_TYPE],
 
                                                               //dfq_byp_ff_data[`DFQ_LD_TYPE:`DFQ_INV_TYPE],
 
                                                               //1'b1,  //assume ld always writes.
 
                                                               //1'b1,  //assume ld always writes.
 
                                                               //5'b00000,
 
                                                               //5'b00000,
 
//   lmq_ld_way[1:0],                                // 131:130 - way[1:0]- dfq_byp_ff_data[`DFQ_WY_HI:`DFQ_WY_LO],
 
//   lmq_ld_way[1:0],                                // 131:130 - way[1:0]- dfq_byp_ff_data[`DFQ_WY_HI:`DFQ_WY_LO],
 
//   2'b0,                                           // 129:128 - size[1:0]- lmq_pcx_pkt_sz[1:0],      //!!! reduce 
//   2'b0,                                           // 129:128 - size[1:0]- lmq_pcx_pkt_sz[1:0],      //!!! reduce 
                                                               //40'b0,  //lmq_pcx_pkt_addr[39:0],   //!!! reduce
 
                                                               //40'b0,  //lmq_pcx_pkt_addr[39:0],   //!!! reduce
 
   dfq_byp_ff_data[127:0]};        // 127:0
 
   dfq_byp_ff_data[`DFQ_DA_HI:`DFQ_DA_LO]};        // 127:0
 
 
 
 
 
 
 
 
 
// Select between dfq-bypass (ld-inv) and store.
 
// Select between dfq-bypass (ld-inv) and store.
 
// *** cpu-id currently hardwired in pkt
 
// *** cpu-id currently hardwired in pkt
 
// This may be further restricted in width !!!
 
// This may be further restricted in width !!!
Line 2328... Line 917... 
);
 
);
 
 
 
 
 
// Parity Generation for write data - from load or store.
 
// Parity Generation for write data - from load or store.
 
wire  [15:0]  dcache_wr_parity ;
 
wire  [15:0]  dcache_wr_parity ;
 
lsu_dc_parity_gen parity_gen (
 
lsu_dc_parity_gen parity_gen (
 
    .data_in  (lsu_dcfill_data[127:0]),
 
    .data_in  (lsu_dcfill_data[`DCFILL_DA_HI:`DCFILL_DA_LO]),
 
    .parity_out (dcache_wr_parity[15:0])
 
    .parity_out (dcache_wr_parity[15:0])
 
  );
 
  );
 
 
 
 
 
// Bug 4125. Corrupt parity if l2 unc err detected. Corrupt both upper and lower half
 
// Bug 4125. Corrupt parity if l2 unc err detected. Corrupt both upper and lower half
 
// as subsequent read will pick up one of two halves.
 
// as subsequent read will pick up one of two halves.
 
//wire  parity_byte0_flip ;
 
//wire  parity_byte0_flip ;
 
//wire  parity_byte8_flip ;
 
//wire  parity_byte8_flip ;
 
wire    ld_unc_error ;
 
wire    ld_unc_error ;
 
assign  ld_unc_error = (dfq_byp_ff_data[138] & dfq_byp_ff_data[151-1]); // not critical !
 
assign  ld_unc_error = (dfq_byp_ff_data[138] & dfq_byp_ff_data[`DFQ_WIDTH-1]); // not critical !
 
 
 
 
 
//bug7021/ECO7022
 
//bug7021/ECO7022
 
//assign        parity_byte0_flip = dcache_wr_parity[0] ^ ld_unc_error ;
 
//assign        parity_byte0_flip = dcache_wr_parity[0] ^ ld_unc_error ;
 
//assign        parity_byte8_flip = dcache_wr_parity[8] ^ ld_unc_error ;
 
//assign        parity_byte8_flip = dcache_wr_parity[8] ^ ld_unc_error ;
 
 
 
 
Line 2396... Line 985... 
//lsu_dc_iob_access_e ? dcache_iob_data_e[63:0] :
 
//lsu_dc_iob_access_e ? dcache_iob_data_e[63:0] :
 
//                      {32{lsu_bist_wdata_e[1:0]}} ;
 
//                      {32{lsu_bist_wdata_e[1:0]}} ;
 
 
 
 
 
   wire [7:0] mbist_write_data_d1;
 
   wire [7:0] mbist_write_data_d1;
 
 
 
 
 
dff #(8) mbist_write_data_ff (
 
dff_s #(8) mbist_write_data_ff (
 
   .din (mbist_write_data[7:0]),
 
   .din (mbist_write_data[7:0]),
 
   .q   (mbist_write_data_d1[7:0]),
 
   .q   (mbist_write_data_d1[7:0]),
 
   .clk    (clk),
 
   .clk    (clk),
 
   .se     (1'b0),     .si (),          .so ()
 
   .se     (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
 
);
 
);
 
 
 
 
 
 
 
 
 
   wire      [3:0] misc_fill_parity_e;
 
   wire      [3:0] misc_fill_parity_e;
 
assign    misc_fill_parity_e[3:0] = {4{~lsu_dc_iob_access_e}} & mbist_write_data_d1[3:0];
 
assign    misc_fill_parity_e[3:0] = {4{~lsu_dc_iob_access_e}} & mbist_write_data_d1[3:0];
Line 2417... Line 1006... 
              .dout(misc_fill_data_e[63:0])
 
              .dout(misc_fill_data_e[63:0])
 
);
 
);
 
 
 
 
 
mux2ds  #(144) lsu_dcache_fill_data_e_mux (
 
mux2ds  #(144) lsu_dcache_fill_data_e_mux (
 
               .in0({misc_fill_data_e[63:0],misc_fill_data_e[63:0],{4{misc_fill_parity_e[3:0]}}}),
 
               .in0({misc_fill_data_e[63:0],misc_fill_data_e[63:0],{4{misc_fill_parity_e[3:0]}}}),
 
               .in1({lsu_dcfill_data[127:0],dcache_wr_parity_mod[15:0]}),
 
               .in1({lsu_dcfill_data[`DCFILL_DA_HI:`DCFILL_DA_LO],dcache_wr_parity_mod[15:0]}),
 
               .sel0(lsu_dcfill_data_mx_sel_e),
 
               .sel0(lsu_dcfill_data_mx_sel_e),
 
               .sel1(~lsu_dcfill_data_mx_sel_e),
 
               .sel1(~lsu_dcfill_data_mx_sel_e),
 
               .dout(lsu_dcache_fill_data_e[143:0])
 
               .dout(lsu_dcache_fill_data_e[143:0])
 
);
 
);
 
 
 
 
Line 2457... Line 1046... 
 
 
 
 
//dff #(4) bist_rsel_way_m_ff (
 
//dff #(4) bist_rsel_way_m_ff (
 
//        .din    (bist_rsel_way_e[3:0]),
 
//        .din    (bist_rsel_way_e[3:0]),
 
//        .q      (bist_rsel_way_m[3:0]),
 
//        .q      (bist_rsel_way_m[3:0]),
 
//        .clk    (clk),
 
//        .clk    (clk),
 
//        .se     (1'b0),       .si (),          .so ()
 
//        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
 
//        );
 
//        );
 
 
 
 
 
//dff #(4) lsu_bist_rsel_way_wb_ff (
 
//dff #(4) lsu_bist_rsel_way_wb_ff (
 
//        .din    (bist_rsel_way_m[3:0]),
 
//        .din    (bist_rsel_way_m[3:0]),
 
//        .q      (lsu_bist_rsel_way_wb[3:0]),
 
//        .q      (lsu_bist_rsel_way_wb[3:0]),
 
//        .clk    (clk),
 
//        .clk    (clk),
 
//        .se     (1'b0),       .si (),          .so ()
 
//        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
 
//        );
 
//        );
 
 
 
 
 
//assign  lsu_dcache_fill_way_e[0] = 
//assign  lsu_dcache_fill_way_e[0] = 
//lsu_dc_iob_access_e ? dcache_iob_wy_e[0] : 
//lsu_dc_iob_access_e ? dcache_iob_wy_e[0] : 
//      (lsu_bist_wvld_e | lsu_bist_rvld_e) ? bist_rsel_way_e[0] :
 
//      (lsu_bist_wvld_e | lsu_bist_rvld_e) ? bist_rsel_way_e[0] :
Line 2540... Line 1129... 
//   assign lsu_dcache_fill_way_enc_e[1] =  lsu_dcache_fill_way_e[2] |  lsu_dcache_fill_way_e[3];
 
//   assign lsu_dcache_fill_way_enc_e[1] =  lsu_dcache_fill_way_e[2] |  lsu_dcache_fill_way_e[3];
 
 
 
 
 
wire [63:0] l2fill_data_e;
 
wire [63:0] l2fill_data_e;
 
 
 
 
 
mux2ds        #(64) half_sel (
 
mux2ds        #(64) half_sel (
 
      .in0    (lsu_dcfill_data[127:0+64]),
 
      .in0    (lsu_dcfill_data[`DCFILL_DA_HI:`DCFILL_DA_LO+64]),
 
      .in1    (lsu_dcfill_data[0+63:0]),
 
      .in1    (lsu_dcfill_data[`DCFILL_DA_LO+63:`DCFILL_DA_LO]),
 
      .sel0   (lsu_dfill_data_sel_hi),  .sel1 (~lsu_dfill_data_sel_hi),
 
      .sel0   (lsu_dfill_data_sel_hi),  .sel1 (~lsu_dfill_data_sel_hi),
 
      .dout   (l2fill_data_e[63:0])
 
      .dout   (l2fill_data_e[63:0])
 
);
 
);
 
 
 
 
 
dff #(64) stgm_l2fd (
 
dff_s #(64) stgm_l2fd (
 
        .din    (l2fill_data_e[63:0]),
 
        .din    (l2fill_data_e[63:0]),
 
        .q      (lsu_l2fill_data[63:0]),
 
        .q      (lsu_l2fill_data[63:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 No newline at end of file
 
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