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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_CLK_EN
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`define FPGA_SYN_CLK_DFF
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`endif
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module lsu_stb_ctldp (/*AUTOARG*/
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module lsu_stb_ctldp (/*AUTOARG*/
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// Outputs
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// Outputs
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so, stb_state_si_0, stb_state_si_1, stb_state_si_2,
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so, stb_state_si_0, stb_state_si_1, stb_state_si_2,
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stb_state_si_3, stb_state_si_4, stb_state_si_5, stb_state_si_6,
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stb_state_si_3, stb_state_si_4, stb_state_si_5, stb_state_si_6,
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| Line 74... |
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wire [7:0] stb_clk;
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wire [7:0] stb_clk;
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wire clk;
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wire clk;
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assign clk = rclk;
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assign clk = rclk;
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`ifdef FPGA_SYN_CLK_EN
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`else
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clken_buf stb0_clkbuf (
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.rclk (clk),
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.enb_l (stb_clk_en_l[0]),
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.tmb_l (~se),
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.clk (stb_clk[0])
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) ;
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`endif
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`ifdef FPGA_SYN_CLK_EN
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`else
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clken_buf stb1_clkbuf (
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.rclk (clk),
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.enb_l (stb_clk_en_l[1]),
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.tmb_l (~se),
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.clk (stb_clk[1])
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) ;
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`endif
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`ifdef FPGA_SYN_CLK_EN
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`else
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clken_buf stb2_clkbuf (
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.rclk (clk),
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.enb_l (stb_clk_en_l[2]),
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.tmb_l (~se),
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.clk (stb_clk[2])
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) ;
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`endif
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`ifdef FPGA_SYN_CLK_EN
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`else
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clken_buf stb3_clkbuf (
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.rclk (clk),
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.enb_l (stb_clk_en_l[3]),
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.tmb_l (~se),
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.clk (stb_clk[3])
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) ;
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`endif
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`ifdef FPGA_SYN_CLK_EN
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`else
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clken_buf stb4_clkbuf (
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.rclk (clk),
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.enb_l (stb_clk_en_l[4]),
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.tmb_l (~se),
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.clk (stb_clk[4])
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) ;
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`endif
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`ifdef FPGA_SYN_CLK_EN
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`else
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clken_buf stb5_clkbuf (
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.rclk (clk),
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.enb_l (stb_clk_en_l[5]),
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.tmb_l (~se),
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.clk (stb_clk[5])
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) ;
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`endif
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`ifdef FPGA_SYN_CLK_EN
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`else
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clken_buf stb6_clkbuf (
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.rclk (clk),
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.enb_l (stb_clk_en_l[6]),
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.tmb_l (~se),
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.clk (stb_clk[6])
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) ;
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`endif
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`ifdef FPGA_SYN_CLK_EN
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`else
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clken_buf stb7_clkbuf (
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.rclk (clk),
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.enb_l (stb_clk_en_l[7]),
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.tmb_l (~se),
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.clk (stb_clk[7])
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) ;
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`endif
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`ifdef FPGA_SYN_CLK_DFF
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dffe_s #(5) ff_spec_write_0 (
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dffe #(5) ff_spec_write_0 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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lsu_st_rmo_m}),
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.q ({stb_state_si_0[3:2], stb_state_rtype_0[2:1],
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.q ({stb_state_si_0[3:2], stb_state_rtype_0[2:1],
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stb_state_rmo[0]} ),
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stb_state_rmo[0]} ),
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.en (~(stb_clk_en_l[0])), .clk(clk),
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.en (~(stb_clk_en_l[0])), .clk(clk),
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.se (se), .si (), .so ()
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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);
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`else
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dff_s #(5) ff_spec_write_0 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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.q ({stb_state_si_0[3:2], stb_state_rtype_0[2:1],
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stb_state_rmo[0]} ),
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.clk (stb_clk[0]),
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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`endif
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`ifdef FPGA_SYN_CLK_DFF
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dffe_s #(5) ff_spec_write_1 (
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dffe #(5) ff_spec_write_1 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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lsu_st_rmo_m}),
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.q ({stb_state_si_1[3:2], stb_state_rtype_1[2:1],
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.q ({stb_state_si_1[3:2], stb_state_rtype_1[2:1],
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stb_state_rmo[1]} ),
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stb_state_rmo[1]} ),
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.en (~(stb_clk_en_l[1])), .clk(clk),
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.en (~(stb_clk_en_l[1])), .clk(clk),
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.se (se), .si (), .so ()
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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);
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`else
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dff_s #(5) ff_spec_write_1 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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.q ({stb_state_si_1[3:2], stb_state_rtype_1[2:1],
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stb_state_rmo[1]} ),
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.clk (stb_clk[1]),
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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`endif
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`ifdef FPGA_SYN_CLK_DFF
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dffe_s #(5) ff_spec_write_2 (
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dffe #(5) ff_spec_write_2 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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lsu_st_rmo_m}),
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.q ({stb_state_si_2[3:2], stb_state_rtype_2[2:1],
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.q ({stb_state_si_2[3:2], stb_state_rtype_2[2:1],
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stb_state_rmo[2]} ),
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stb_state_rmo[2]} ),
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.en (~(stb_clk_en_l[2])), .clk(clk),
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.en (~(stb_clk_en_l[2])), .clk(clk),
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.se (se), .si (), .so ()
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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);
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`else
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dff_s #(5) ff_spec_write_2 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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.q ({stb_state_si_2[3:2], stb_state_rtype_2[2:1],
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stb_state_rmo[2]} ),
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.clk (stb_clk[2]),
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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`endif
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`ifdef FPGA_SYN_CLK_DFF
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dffe #(5) ff_spec_write_3 (
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dffe_s #(5) ff_spec_write_3 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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lsu_st_rmo_m}),
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.q ({stb_state_si_3[3:2], stb_state_rtype_3[2:1],
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.q ({stb_state_si_3[3:2], stb_state_rtype_3[2:1],
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stb_state_rmo[3]} ),
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stb_state_rmo[3]} ),
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.en (~(stb_clk_en_l[3])), .clk(clk),
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.en (~(stb_clk_en_l[3])), .clk(clk),
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.se (se), .si (), .so ()
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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);
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`else
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dff_s #(5) ff_spec_write_3 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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.q ({stb_state_si_3[3:2], stb_state_rtype_3[2:1],
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stb_state_rmo[3]} ),
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.clk (stb_clk[3]),
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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`endif
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`ifdef FPGA_SYN_CLK_DFF
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dffe #(5) ff_spec_write_4 (
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dffe_s #(5) ff_spec_write_4 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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lsu_st_rmo_m}),
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.q ({stb_state_si_4[3:2], stb_state_rtype_4[2:1],
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.q ({stb_state_si_4[3:2], stb_state_rtype_4[2:1],
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stb_state_rmo[4]} ),
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stb_state_rmo[4]} ),
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.en (~(stb_clk_en_l[4])), .clk(clk),
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.en (~(stb_clk_en_l[4])), .clk(clk),
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.se (se), .si (), .so ()
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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);
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`else
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dff_s #(5) ff_spec_write_4 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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.q ({stb_state_si_4[3:2], stb_state_rtype_4[2:1],
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stb_state_rmo[4]} ),
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.clk (stb_clk[4]),
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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`endif
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`ifdef FPGA_SYN_CLK_DFF
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dffe #(5) ff_spec_write_5 (
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dffe_s #(5) ff_spec_write_5 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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lsu_st_rmo_m}),
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.q ({stb_state_si_5[3:2], stb_state_rtype_5[2:1],
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.q ({stb_state_si_5[3:2], stb_state_rtype_5[2:1],
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stb_state_rmo[5]} ),
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stb_state_rmo[5]} ),
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.en (~(stb_clk_en_l[5])), .clk(clk),
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.en (~(stb_clk_en_l[5])), .clk(clk),
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.se (se), .si (), .so ()
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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);
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`else
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dff_s #(5) ff_spec_write_5 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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.q ({stb_state_si_5[3:2], stb_state_rtype_5[2:1],
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stb_state_rmo[5]} ),
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.clk (stb_clk[5]),
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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`endif
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`ifdef FPGA_SYN_CLK_DFF
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dffe #(5) ff_spec_write_6 (
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dffe_s #(5) ff_spec_write_6 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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lsu_st_rmo_m}),
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.q ({stb_state_si_6[3:2], stb_state_rtype_6[2:1],
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.q ({stb_state_si_6[3:2], stb_state_rtype_6[2:1],
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stb_state_rmo[6]} ),
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stb_state_rmo[6]} ),
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.en (~(stb_clk_en_l[6])), .clk(clk),
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.en (~(stb_clk_en_l[6])), .clk(clk),
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.se (se), .si (), .so ()
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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);
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`else
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dff_s #(5) ff_spec_write_6 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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.q ({stb_state_si_6[3:2], stb_state_rtype_6[2:1],
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stb_state_rmo[6]} ),
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.clk (stb_clk[6]),
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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`endif
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`ifdef FPGA_SYN_CLK_DFF
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dffe_s #(5) ff_spec_write_7 (
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dffe #(5) ff_spec_write_7 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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lsu_st_rmo_m}),
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.q ({stb_state_si_7[3:2], stb_state_rtype_7[2:1],
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.q ({stb_state_si_7[3:2], stb_state_rtype_7[2:1],
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stb_state_rmo[7]} ),
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stb_state_rmo[7]} ),
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.en (~(stb_clk_en_l[7])), .clk(clk),
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.en (~(stb_clk_en_l[7])), .clk(clk),
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.se (se), .si (), .so ()
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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);
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`else
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dff_s #(5) ff_spec_write_7 (
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.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
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lsu_st_rmo_m}),
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.q ({stb_state_si_7[3:2], stb_state_rtype_7[2:1],
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stb_state_rmo[7]} ),
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.clk (stb_clk[7]),
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.se (se), `SIMPLY_RISC_SCANIN, .so ()
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);
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`endif
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endmodule // lsu_stb_ctldp
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endmodule // lsu_stb_ctldp
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No newline at end of file
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No newline at end of file
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