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URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [lsu_stb_rwctl.v] - Diff between revs 105 and 113

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Rev 105 Rev 113
Line 16... Line 16... 
// You should have received a copy of the GNU General Public
 
// You should have received a copy of the GNU General Public
 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
`define SIMPLY_RISC_SCANIN .si(0)
 
 
 
`else
 
 
 
`define SIMPLY_RISC_SCANIN .si()
 
 
 
`endif
 
///////////////////////////////////////////////////////////////////
 
///////////////////////////////////////////////////////////////////
 
/*
 
/*
 
//  Description:  Control for Unified STB CAM/DATA of LSU
 
//  Description:  Control for Unified STB CAM/DATA of LSU
 
*/
 
*/
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Global header file includes
 
// Global header file includes
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// system level definition file which contains the /*
 
`include  "sys.h" // system level definition file which contains the 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: sys.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
// -*- verilog -*-
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
// Description:         Global header file that contain definitions that
 
 
 
//                      are common/shared at the systme level
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
//
 
 
 
// Setting the time scale
 
 
 
// If the timescale changes, JP_TIMESCALE may also have to change.
 
 
 
`timescale      1ps/1ps
 
 
 
 
 
 
 
//
 
 
 
// JBUS clock
 
 
 
// =========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Defines
 
 
 
// ==================
 
 
 
 
 
 
 
// Reliable Link
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Objects
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Reliable Link
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Congestion
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Acknowledge
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Request
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Message
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Acknowledge Types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Request Types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Frame
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Packet Type
 
 
 
// ===============
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Data Packet Format
 
 
 
// ======================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Size encoding for the UCB_SIZE_HI/LO field
 
 
 
// 000 - byte
 
 
 
// 001 - half-word
 
 
 
// 010 - word
 
 
 
// 011 - double-word
 
 
 
// 111 - quad-word
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Interrupt Packet Format
 
 
 
// ===========================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define UCB_THR_HI             9      // (6) cpu/thread ID shared with
 
 
 
//`define UCB_THR_LO             4             data packet format
 
 
 
//`define UCB_PKT_HI             3      // (4) packet type shared with
 
 
 
//`define UCB_PKT_LO             0      //     data packet format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// FCRAM Bus Widths
 
 
 
// ================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// ENET clock periods
 
 
 
// ==================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBus Bridge defines
 
 
 
// =================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PCI Device Address Configuration
 
 
 
// ================================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
          // time scale definition
 
          // time scale definition
 
 
 
 
 
/*
 
`include "iop.h"
 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: iop.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
//-*- verilog -*-
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
//  Description:        Global header file that contain definitions that
 
 
 
//                      are common/shared at the IOP chip level
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
 
 
 
 
 
 
 
// Address Map Defines
 
 
 
// ===================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CMP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// IOP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                               //`define ENET_ING_CSR     8'h84
 
 
 
                               //`define ENET_EGR_CMD_CSR 8'h85
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2 space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// More IOP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//Cache Crossbar Width and Field Defines
 
 
 
//======================================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//bits 133:128 are shared by different fields
 
 
 
//for different packet types.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//End cache crossbar defines
 
 
 
 
 
 
 
 
 
 
 
// Number of COS supported by EECU 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// BSC bus sizes
 
 
 
// =============
 
 
 
//
 
 
 
 
 
 
 
// General
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CTags
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// reinstated temporarily
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CoS
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Bank
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Req
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Command Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// This is cleaved in between Egress Datapath Ack's
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Datapath
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: EEPU
 
 
 
// Tag is: TLEN, SOF, EOF, QID = 15
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Nack + Tag Info + CTag
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Req
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Ingress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Packet Unit Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: PCI
 
 
 
// Tag is: CTAG
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PCI-X Request
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PCI_X Acknowledge
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// BSC array sizes
 
 
 
//================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ECC syndrome bits per memory element
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// BSC Port Definitions
 
 
 
// ====================
 
 
 
//
 
 
 
// Bits 7 to 4 of curr_port_id
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Number of ports of each type
 
 
 
 
 
 
 
 
 
 
 
// Bits needed to represent above
 
 
 
 
 
 
 
 
 
 
 
// How wide the linked list pointers are
 
 
 
// 60b for no payload (2CoS)
 
 
 
// 80b for payload (2CoS)
 
 
 
 
 
 
 
//`define BSC_OBJ_PTR   80
 
 
 
//`define BSC_HD1_HI    69
 
 
 
//`define BSC_HD1_LO    60
 
 
 
//`define BSC_TL1_HI    59
 
 
 
//`define BSC_TL1_LO    50
 
 
 
//`define BSC_CT1_HI    49
 
 
 
//`define BSC_CT1_LO    40
 
 
 
//`define BSC_HD0_HI    29
 
 
 
//`define BSC_HD0_LO    20
 
 
 
//`define BSC_TL0_HI    19
 
 
 
//`define BSC_TL0_LO    10
 
 
 
//`define BSC_CT0_HI     9
 
 
 
//`define BSC_CT0_LO     0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// I2C STATES in DRAMctl
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// IOB defines
 
 
 
// ===========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_INT_STAT_WIDTH   32
 
 
 
//`define IOB_INT_STAT_HI      31
 
 
 
//`define IOB_INT_STAT_LO       0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// fixme - double check address mapping
 
 
 
// CREG in `IOB_INT_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CREG in `IOB_MAN_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Address map for TAP access of SPARC ASI
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CIOP UCB Bus Width
 
 
 
// ==================
 
 
 
//
 
 
 
//`define IOB_EECU_WIDTH       16  // ethernet egress command
 
 
 
//`define EECU_IOB_WIDTH       16
 
 
 
 
 
 
 
//`define IOB_NRAM_WIDTH       16  // NRAM (RLDRAM previously)
 
 
 
//`define NRAM_IOB_WIDTH        4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_ENET_ING_WIDTH   32  // ethernet ingress
 
 
 
//`define ENET_ING_IOB_WIDTH    8
 
 
 
 
 
 
 
//`define IOB_ENET_EGR_WIDTH    4  // ethernet egress
 
 
 
//`define ENET_EGR_IOB_WIDTH    4
 
 
 
 
 
 
 
//`define IOB_ENET_MAC_WIDTH    4  // ethernet MAC
 
 
 
//`define ENET_MAC_IOB_WIDTH    4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_BSC_WIDTH         4  // BSC
 
 
 
//`define BSC_IOB_WIDTH         4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_CLSP_WIDTH        4  // clk spine unit
 
 
 
//`define CLSP_IOB_WIDTH        4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CIOP UCB Buf ID Type
 
 
 
// ====================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Interrupt Device ID
 
 
 
// ===================
 
 
 
//
 
 
 
// Caution: DUMMY_DEV_ID has to be 9 bit wide
 
 
 
//          for fields to line up properly in the IOB.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Soft Error related definitions 
 
 
// ==============================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CMP clock
 
 
 
// =========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// NRAM/IO Interface
 
 
 
// =================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// NRAM/ENET Interface
 
 
 
// ===================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// IO/FCRAM Interface
 
 
 
// ==================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PCI Interface
 
 
 
// ==================
 
 
 
// Load/store size encodings
 
 
 
// -------------------------
 
 
 
// Size encoding
 
 
 
// 000 - byte
 
 
 
// 001 - half-word
 
 
 
// 010 - word
 
 
 
// 011 - double-word
 
 
 
// 100 - quad
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBI<->SCTAG Interface
 
 
 
// =======================
 
 
 
// Outbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Inbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBI->IOB Mondo Header Format
 
 
 
// ============================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// JBI->IOB Mondo Bus Width/Cycle
 
 
 
// ==============================
 
 
 
// Cycle  1 Header[15:8]
 
 
 
// Cycle  2 Header[ 7:0]
 
 
 
// Cycle  3 J_AD[127:120]
 
 
 
// Cycle  4 J_AD[119:112]
 
 
 
// .....
 
 
 
// Cycle 18 J_AD[  7:  0]
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Local header file includes / local defines
 
// Local header file includes / local defines
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
Line 1360... Line 250... 
 
 
 
 
/*AUTOWIRE*/
 
/*AUTOWIRE*/
 
// Beginning of automatic wires (for undeclared instantiated-module outputs)
 
// Beginning of automatic wires (for undeclared instantiated-module outputs)
 
// End of automatics
 
// End of automatics
 
// Beginning of automatic wires (for undeclared instantiated-module outputs)
 
// Beginning of automatic wires (for undeclared instantiated-module outputs)
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
wire bst_in_pipe_g;
 
 
 
`endif
 
// End of automatics
 
// End of automatics
 
//wire  [4:0] stb_dequeue_ptr ;
 
//wire  [4:0] stb_dequeue_ptr ;
 
wire  [2:0] stb_wptr_prev ;
 
wire  [2:0] stb_wptr_prev ;
 
wire  [1:0] st_thrid_m,st_thrid_g ;
 
wire  [1:0] st_thrid_m,st_thrid_g ;
 
wire  [7:0] ld_any_raw_vld ;
 
wire  [7:0] ld_any_raw_vld ;
Line 1428... Line 321... 
//   wire       rst_l;
 
//   wire       rst_l;
 
//   wire       stb_rwctl_rst_l;
 
//   wire       stb_rwctl_rst_l;
 
 
 
 
 
//   dffrl_async rstff(.din (grst_l),
 
//   dffrl_async rstff(.din (grst_l),
 
//                     .q   (stb_rwctl_rst_l),
 
//                     .q   (stb_rwctl_rst_l),
 
//                     .clk (clk), .se(se), .si(), .so(),
 
//                     .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so(),
 
//                     .rst_l (arst_l));
 
//                     .rst_l (arst_l));
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//  MISC
 
//  MISC
 
//=========================================================================================
 
//=========================================================================================
 
 
 
 
 
// Scan-only flops.
 
// Scan-only flops.
 
 
 
 
 
wire    [8:0]    stb_rdata_ramc_b8t0_so ;
 
wire    [8:0]    stb_rdata_ramc_b8t0_so ;
 
dff #(9)  scmscan_ff (
 
dff_s #(9)  scmscan_ff (
 
        .din    (stb_rdata_ramc_b8t0[8:0]),
 
        .din    (stb_rdata_ramc_b8t0[8:0]),
 
        .q      (stb_rdata_ramc_b8t0_so[8:0]),
 
        .q      (stb_rdata_ramc_b8t0_so[8:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se   (se),       .si (),          .so ()
 
        .se   (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//  INST_VLD_W GENERATION
 
//  INST_VLD_W GENERATION
 
//=========================================================================================
 
//=========================================================================================
Line 1467... Line 360... 
 
 
 
 
assign  flush_w_inst_vld_m =
 
assign  flush_w_inst_vld_m =
 
        ifu_tlu_inst_vld_m_bf0 &
 
        ifu_tlu_inst_vld_m_bf0 &
 
        ~(lsu_stbrwctl_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w
 
        ~(lsu_stbrwctl_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w
 
 
 
 
 
dff  stgw_ivld (
 
dff_s  stgw_ivld (
 
        .din    (flush_w_inst_vld_m),
 
        .din    (flush_w_inst_vld_m),
 
        .q      (lsu_inst_vld_w),
 
        .q      (lsu_inst_vld_w),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se   (se),       .si (),          .so ()
 
        .se   (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
   wire other_flush_pipe_w;
 
   wire other_flush_pipe_w;
 
   wire tlu_early_flush_pipe_w;
 
   wire tlu_early_flush_pipe_w;
 
   assign tlu_early_flush_pipe_w = tlu_exu_early_flush_pipe_w;
 
   assign tlu_early_flush_pipe_w = tlu_exu_early_flush_pipe_w;
Line 1507... Line 400... 
 
 
 
 
//dff  stq_stgm (
 
//dff  stq_stgm (
 
//  .din  (stdbl_e), 
//  .din  (stdbl_e), 
//  .q          (lsu_stdbl_inst_m),  
//  .q          (lsu_stdbl_inst_m),  
//  .clk  (clk), 
//  .clk  (clk), 
//  .se (se), .si (), .so ()
 
//  .se (se), `SIMPLY_RISC_SCANIN, .so ()
 
//  );
 
//  );
 
 
 
 
 
// This path can probably be eased.
 
// This path can probably be eased.
 
assign  lsu_stb_data_early_sel_e[0] = ldstub_e  & ~rst_tri_en;
 
assign  lsu_stb_data_early_sel_e[0] = ldstub_e  & ~rst_tri_en;
 
assign  lsu_stb_data_early_sel_e[1] = casa_e & ~rst_tri_en;
 
assign  lsu_stb_data_early_sel_e[1] = casa_e & ~rst_tri_en;
Line 1523... Line 416... 
 
 
 
 
/*dff  lsel_g (
 
/*dff  lsel_g (
 
  .din  (stb_data_final_sel_e),
 
  .din  (stb_data_final_sel_e),
 
  .q  (lsu_stb_data_final_sel_m),
 
  .q  (lsu_stb_data_final_sel_m),
 
  .clk  (clk),
 
  .clk  (clk),
 
  .se (se), .si (), .so ()
 
  .se (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );*/
 
  );*/
 
 
 
 
 
assign  lsu_stb_data_final_sel_m = ~(ldst_fp_m | blkst_m) ;
 
assign  lsu_stb_data_final_sel_m = ~(ldst_fp_m | blkst_m) ;
 
 
 
 
 
wire    real_st_m ;
 
wire    real_st_m ;
 
wire    flsh_inst_m, flsh_inst_g ;
 
wire    flsh_inst_m, flsh_inst_g ;
 
// !!! could qualify st_inst_vld_e with stxa_internal !!!
 
// !!! could qualify st_inst_vld_e with stxa_internal !!!
 
dff #(13) stgm_vld  (
 
dff_s #(13) stgm_vld  (
 
  .din  ({ld_inst_vld_e,st_inst_vld_e,ldst_sz_e[1:0],
 
  .din  ({ld_inst_vld_e,st_inst_vld_e,ldst_sz_e[1:0],
 
    ifu_lsu_swap_e, ifu_lsu_ldstub_e, ifu_lsu_casa_e,ifu_lsu_ldst_dbl_e,
 
    ifu_lsu_swap_e, ifu_lsu_ldstub_e, ifu_lsu_casa_e,ifu_lsu_ldst_dbl_e,
 
    ifu_tlu_thrid_e[1:0],ifu_lsu_ldst_fp_e,lsu_quad_asi_e,ifu_tlu_flsh_inst_e}),
 
    ifu_tlu_thrid_e[1:0],ifu_lsu_ldst_fp_e,lsu_quad_asi_e,ifu_tlu_flsh_inst_e}),
 
  .q  ({ld_inst_vld_m,real_st_m,pipe_ldst_sz_m[1:0],
 
  .q  ({ld_inst_vld_m,real_st_m,pipe_ldst_sz_m[1:0],
 
    swap_m,ldstub_m,casa_m,ldst_dbl_m,thrid_m[1:0],ldst_fp_m,quad_asi_m,flsh_inst_m}),
 
    swap_m,ldstub_m,casa_m,ldst_dbl_m,thrid_m[1:0],ldst_fp_m,quad_asi_m,flsh_inst_m}),
 
  .clk  (clk),
 
  .clk  (clk),
 
  .se   (se), .si (), .so ()
 
  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
assign  st_inst_vld_m = real_st_m | flsh_inst_m ;
 
assign  st_inst_vld_m = real_st_m | flsh_inst_m ;
 
 
 
 
 
// do we need ld/st unflushed ?
 
// do we need ld/st unflushed ?
 
   wire sta_internal_g;
 
   wire sta_internal_g;
 
 
 
 
 
dff #(7) stgw_vld  (
 
dff_s #(7) stgw_vld  (
 
  .din  ({sta_internal_m,
 
  .din  ({sta_internal_m,
 
    casa_m, thrid_m[1:0],ldst_sz_m[1:0], flsh_inst_m}),
 
    casa_m, thrid_m[1:0],ldst_sz_m[1:0], flsh_inst_m}),
 
  .q    ({sta_internal_g,
 
  .q    ({sta_internal_g,
 
    casa_g, thrid_g[1:0],ldst_sz_g[1:0], flsh_inst_g}),
 
    casa_g, thrid_g[1:0],ldst_sz_g[1:0], flsh_inst_g}),
 
  .clk  (clk),
 
  .clk  (clk),
 
  .se   (se), .si (), .so ()
 
  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
 
 
 
 
// stb-cam will be written by st at rising edge of g-stage.
 
// stb-cam will be written by st at rising edge of g-stage.
 
// However, st can be flushed after write. To keep, the stb state consistent,
 
// However, st can be flushed after write. To keep, the stb state consistent,
Line 1586... Line 479... 
assign  stb_cam_wptr_vld
 
assign  stb_cam_wptr_vld
 
  = (((st_inst_vld_m | atomic_m) & ifu_tlu_inst_vld_m_bf0) | blkst_m) & ~(flush_st_g & b2b_st_detect) ;
 
  = (((st_inst_vld_m | atomic_m) & ifu_tlu_inst_vld_m_bf0) | blkst_m) & ~(flush_st_g & b2b_st_detect) ;
 
  //= ((st_inst_vld_m | atomic_m) & ifu_tlu_inst_vld_m_bf0) | blkst_m ;  // bug3610
 
  //= ((st_inst_vld_m | atomic_m) & ifu_tlu_inst_vld_m_bf0) | blkst_m ;  // bug3610
 
  //= (st_inst_vld_m | atomic_m | (ldst_dbl_m & st_inst_vld_m) | blkst_m) ;
 
  //= (st_inst_vld_m | atomic_m | (ldst_dbl_m & st_inst_vld_m) | blkst_m) ;
 
 
 
 
 
dff  wptr_g (
 
dff_s  wptr_g (
 
  .din  (stb_cam_wptr_vld), .q  (cam_wptr_vld_g),
 
  .din  (stb_cam_wptr_vld), .q  (cam_wptr_vld_g),
 
  .clk  (clk),
 
  .clk  (clk),
 
  .se   (se), .si (), .so ()
 
  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
//flop move into mem cell (roll back)  
//flop move into mem cell (roll back)  
assign  stb_data_wptr_vld = cam_wptr_vld_g ;
 
assign  stb_data_wptr_vld = cam_wptr_vld_g ;
 
 
 
 
Line 1609... Line 502... 
assign  thread0_m = ~st_thrid_m[1] & ~st_thrid_m[0] ;
 
assign  thread0_m = ~st_thrid_m[1] & ~st_thrid_m[0] ;
 
assign  thread1_m = ~st_thrid_m[1] &  st_thrid_m[0] ;
 
assign  thread1_m = ~st_thrid_m[1] &  st_thrid_m[0] ;
 
assign  thread2_m =  st_thrid_m[1] & ~st_thrid_m[0] ;
 
assign  thread2_m =  st_thrid_m[1] & ~st_thrid_m[0] ;
 
assign  thread3_m =  st_thrid_m[1] &  st_thrid_m[0] ;
 
assign  thread3_m =  st_thrid_m[1] &  st_thrid_m[0] ;
 
 
 
 
 
dff #(4) stgg_thrd (
 
dff_s #(4) stgg_thrd (
 
  .din  ({thread0_m,thread1_m,thread2_m,thread3_m}),
 
  .din  ({thread0_m,thread1_m,thread2_m,thread3_m}),
 
  .q  ({thread0_g,thread1_g,thread2_g,thread3_g}),
 
  .q  ({thread0_g,thread1_g,thread2_g,thread3_g}),
 
  .clk  (clk),
 
  .clk  (clk),
 
  .se (se), .si (), .so ()
 
  .se (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
assign  stb_thrd_en_g[0] = thread0_g ;
 
assign  stb_thrd_en_g[0] = thread0_g ;
 
assign  stb_thrd_en_g[1] = thread1_g ;
 
assign  stb_thrd_en_g[1] = thread1_g ;
 
assign  stb_thrd_en_g[2] = thread2_g ;
 
assign  stb_thrd_en_g[2] = thread2_g ;
Line 1641... Line 534... 
  (thread2_m & thread2_g) |
 
  (thread2_m & thread2_g) |
 
  (thread3_m & thread3_g) ;
 
  (thread3_m & thread3_g) ;
 
 
 
 
 
assign  cam_wr_ptr[2:0] = (flush_st_g & b2b_st_detect) ? cam_wptr_d1[2:0] : stb_wptr[2:0] ;
 
assign  cam_wr_ptr[2:0] = (flush_st_g & b2b_st_detect) ? cam_wptr_d1[2:0] : stb_wptr[2:0] ;
 
 
 
 
 
dff #(3)  wptr_d1 (
 
dff_s #(3)  wptr_d1 (
 
  .din  (cam_wr_ptr[2:0]),  .q  (cam_wptr_d1[2:0]),
 
  .din  (cam_wr_ptr[2:0]),  .q  (cam_wptr_d1[2:0]),
 
  .clk  (clk),
 
  .clk  (clk),
 
  .se (se), .si (), .so ()
 
  .se (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
assign  stb_cam_wvld_m[0] = stb_cam_wptr_vld & thread0_m ;
 
assign  stb_cam_wvld_m[0] = stb_cam_wptr_vld & thread0_m ;
 
assign  stb_cam_wvld_m[1] = stb_cam_wptr_vld & thread1_m ;
 
assign  stb_cam_wvld_m[1] = stb_cam_wptr_vld & thread1_m ;
 
assign  stb_cam_wvld_m[2] = stb_cam_wptr_vld & thread2_m ;
 
assign  stb_cam_wvld_m[2] = stb_cam_wptr_vld & thread2_m ;
Line 1697... Line 590... 
   wire       stb_cam_hit_w;
 
   wire       stb_cam_hit_w;
 
 
 
 
 
   //bug3503
 
   //bug3503
 
   assign stb_cam_hit_w  =  stb_cam_hit & lsu_inst_vld_w & ~lsu_stbrwctl_flush_pipe_w;
 
   assign stb_cam_hit_w  =  stb_cam_hit & lsu_inst_vld_w & ~lsu_stbrwctl_flush_pipe_w;
 
 
 
 
 
dff #(6) stb_cam_hit_stg_w2 (
 
dff_s #(6) stb_cam_hit_stg_w2 (
 
  .din  ({thrid_g[1:0],  stb_cam_hit_ptr[2:0],    stb_cam_hit_w   }),
 
  .din  ({thrid_g[1:0],  stb_cam_hit_ptr[2:0],    stb_cam_hit_w   }),
 
  .q    ({thrid_w2[1:0], stb_cam_hit_ptr_w2[2:0], stb_cam_hit_w2}),
 
  .q    ({thrid_w2[1:0], stb_cam_hit_ptr_w2[2:0], stb_cam_hit_w2}),
 
  .clk  (clk),
 
  .clk  (clk),
 
  .se   (se), .si (), .so ()
 
  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
// logic moved to qctl1
 
// logic moved to qctl1
 
// pcx is making request for data in current cycle. Can be multi-hot.
 
// pcx is making request for data in current cycle. Can be multi-hot.
 
//assign  pcx_any_rq_for_stb = |pcx_rq_for_stb[3:0] ;
 
//assign  pcx_any_rq_for_stb = |pcx_rq_for_stb[3:0] ;
Line 1735... Line 628... 
//assign  stb_rd_tid[1] = pcx_rq_for_stb[2] | pcx_rq_for_stb[3] ;
 
//assign  stb_rd_tid[1] = pcx_rq_for_stb[2] | pcx_rq_for_stb[3] ;
 
//   
//   
//dff #(2) stbtid_stgd1 (
 
//dff #(2) stbtid_stgd1 (
 
//  .din    (stb_rd_tid[1:0]),  .q  (lsu_stb_rd_tid[1:0]),
 
//  .din    (stb_rd_tid[1:0]),  .q  (lsu_stb_rd_tid[1:0]),
 
//  .clk    (clk), 
//  .clk    (clk), 
//  .se   (se), .si (), .so ()
 
//  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
//  );
 
//  );
 
 
 
 
 
//assign  stb_dfq_rd_id[2:0] = stb_data_rd_ptr[2:0] ; // or cam rd ptr
 
//assign  stb_dfq_rd_id[2:0] = stb_data_rd_ptr[2:0] ; // or cam rd ptr
 
 
 
 
 
//timing fix:5/6/03
 
//timing fix:5/6/03
Line 1820... Line 713... 
        {thrid_w2[1:0],stb_cam_hit_ptr_w2[2:0]} :  // rd based on ld hit
 
        {thrid_w2[1:0],stb_cam_hit_ptr_w2[2:0]} :  // rd based on ld hit
 
        {stb_rd_thrid[1:0],~stb_rdptr_l[2:0]} ;       // rd for pcx or dfq
 
        {stb_rd_thrid[1:0],~stb_rdptr_l[2:0]} ;       // rd for pcx or dfq
 
 
 
 
 
// Blk-st modification for thread.
 
// Blk-st modification for thread.
 
assign  st_thrid_m[1:0] = blkst_m ? ffu_lsu_blk_st_tid_m[1:0] : thrid_m[1:0] ;
 
assign  st_thrid_m[1:0] = blkst_m ? ffu_lsu_blk_st_tid_m[1:0] : thrid_m[1:0] ;
 
dff #(2)  stid_stgg (
 
dff_s #(2)  stid_stgg (
 
  .din  (st_thrid_m[1:0]),
 
  .din  (st_thrid_m[1:0]),
 
  .q    (st_thrid_g[1:0]),
 
  .q    (st_thrid_g[1:0]),
 
  .clk  (clk),
 
  .clk  (clk),
 
  .se (se), .si (), .so ()
 
  .se (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
//timing fix: 5/6/03
 
//timing fix: 5/6/03
 
//assign  stb_cam_rw_ptr[4:0]  = stb_cam_wptr_vld ? 
//assign  stb_cam_rw_ptr[4:0]  = stb_cam_wptr_vld ? 
//        {st_thrid_m[1:0],cam_wr_ptr[2:0]} :  // write
 
//        {st_thrid_m[1:0],cam_wr_ptr[2:0]} :  // write
Line 1898... Line 791... 
 
 
 
 
// lsu_stb_rd_vld_d1 - not used
 
// lsu_stb_rd_vld_d1 - not used
 
//dff  stbrd_stgd1  (
 
//dff  stbrd_stgd1  (
 
//  .din    (stb_cam_rptr_vld), .q  (lsu_stb_rd_vld_d1),
 
//  .din    (stb_cam_rptr_vld), .q  (lsu_stb_rd_vld_d1),
 
//  .clk    (clk), 
//  .clk    (clk), 
//  .se   (se), .si (), .so ()
 
//  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
//  );
 
//  );
 
 
 
 
 
// logic moved to qctl1
 
// logic moved to qctl1
 
//dff #(1)  prvld_stgd1 (
 
//dff #(1)  prvld_stgd1 (
 
//  .din  (pcx_any_rq_for_stb), 
//  .din  (pcx_any_rq_for_stb), 
//  .q  (lsu_stb_pcx_rvld_d1),
 
//  .q  (lsu_stb_pcx_rvld_d1),
 
//  .clk  (clk), 
//  .clk  (clk), 
//  .se (se), .si (), .so ()
 
//  .se (se), `SIMPLY_RISC_SCANIN, .so ()
 
//  );
 
//  );
 
 
 
 
 
assign  stb_cam_cm_tid[1:0] = thrid_m[1:0] ;
 
assign  stb_cam_cm_tid[1:0] = thrid_m[1:0] ;
 
 
 
 
 
 
 
 
Line 1932... Line 825... 
 
 
 
 
 
 
 
 
//dff  #(11) va_m (
 
//dff  #(11) va_m (
 
//  .din    (exu_lsu_ldst_va_e[10:0]),  .q  (pipe_ldst_va_m[10:0]),
 
//  .din    (exu_lsu_ldst_va_e[10:0]),  .q  (pipe_ldst_va_m[10:0]),
 
//  .clk    (clk), 
//  .clk    (clk), 
//  .se   (se), .si (), .so ()
 
//  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
//  );
 
//  );
 
 
 
 
 
assign pipe_ldst_va_m[9:0] = lsu_ldst_va_m[9:0];
 
assign pipe_ldst_va_m[9:0] = lsu_ldst_va_m[9:0];
 
 
 
 
 
// ldst_byte may not be needed
 
// ldst_byte may not be needed
Line 2000... Line 893... 
//=========================================================================================
 
//=========================================================================================
 
//  BLK-ST HANDLING
 
//  BLK-ST HANDLING
 
//=========================================================================================
 
//=========================================================================================
 
 
 
 
 
wire    blkst_m_tmp ;
 
wire    blkst_m_tmp ;
 
dff  stgm_bst (
 
dff_s  stgm_bst (
 
  .din (ffu_lsu_blk_st_e),
 
  .din (ffu_lsu_blk_st_e),
 
  .q   (blkst_m_tmp),
 
  .q   (blkst_m_tmp),
 
  .clk (clk),
 
  .clk (clk),
 
  .se   (se),       .si (),          .so ()
 
  .se   (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
);
 
);
 
 
 
 
 
assign  blkst_m = blkst_m_tmp & ~(real_st_m  | flsh_inst_m |
 
assign  blkst_m = blkst_m_tmp & ~(real_st_m  | flsh_inst_m |
 
                ld_inst_vld_m) ; // Bug 3444
 
                ld_inst_vld_m) ; // Bug 3444
 
 
 
 
 
dff  stgg_bst (
 
dff_s  stgg_bst (
 
  .din (blkst_m),
 
  .din (blkst_m),
 
  .q   (blkst_g),
 
  .q   (blkst_g),
 
  .clk (clk),
 
  .clk (clk),
 
  .se   (se),       .si (),          .so ()
 
  .se   (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
);
 
);
 
 
 
 
 
wire    snap_blk_st_local_m ;
 
wire    snap_blk_st_local_m ;
 
assign  snap_blk_st_local_m = lsu_snap_blk_st_m & ifu_tlu_inst_vld_m_bf0 ;
 
assign  snap_blk_st_local_m = lsu_snap_blk_st_m & ifu_tlu_inst_vld_m_bf0 ;
 
 
 
 
 
wire    [1:0]    bst_sz_m ;
 
wire    [1:0]    bst_sz_m ;
 
wire    [9:0]    bst_va_m ;
 
wire    [9:0]    bst_va_m ;
 
// output to be used in m-stage.
 
// output to be used in m-stage.
 
dffe #(9) bst_state_m (
 
dffe_s #(9) bst_state_m (
 
        .din    ({ldst_sz_m[1:0],ldst_va_m[9:6],ldst_va_m[2:0]}),
 
        .din    ({ldst_sz_m[1:0],ldst_va_m[9:6],ldst_va_m[2:0]}),
 
        .q      ({bst_sz_m[1:0],bst_va_m[9:6],bst_va_m[2:0]}),
 
        .q      ({bst_sz_m[1:0],bst_va_m[9:6],bst_va_m[2:0]}),
 
        .en     (snap_blk_st_local_m),
 
        .en     (snap_blk_st_local_m),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se   (se),       .si (),          .so ()
 
        .se   (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
dff #(3)  bsva_stgm (
 
dff_s #(3)  bsva_stgm (
 
  .din    (ffu_lsu_blk_st_va_e[5:3]), .q (bst_va_m[5:3]),
 
  .din    (ffu_lsu_blk_st_va_e[5:3]), .q (bst_va_m[5:3]),
 
  .clk    (clk),
 
  .clk    (clk),
 
  .se   (se), .si (), .so ()
 
  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
//assign        bst_va_m[5:3]   = ffu_lsu_blk_st_va_e[5:3] ;
 
//assign        bst_va_m[5:3]   = ffu_lsu_blk_st_va_e[5:3] ;
 
 
 
 
 
//assign  ldst_va_m[10] =  pipe_ldst_va_m[10] ;
 
//assign  ldst_va_m[10] =  pipe_ldst_va_m[10] ;
Line 2077... Line 970... 
assign  lsu_stquad_inst_m = ldst_dbl_m & st_inst_vld_m & quad_asi_m ;
 
assign  lsu_stquad_inst_m = ldst_dbl_m & st_inst_vld_m & quad_asi_m ;
 
*/
 
*/
 
 
 
 
 
wire    st_rmo_m,st_rmo_g ;
 
wire    st_rmo_m,st_rmo_g ;
 
assign  st_rmo_m = lsu_st_rmo_m | blkst_m ; // binit and blk rmo stores.
 
assign  st_rmo_m = lsu_st_rmo_m | blkst_m ; // binit and blk rmo stores.
 
dff #(9)  stgg_etc  (
 
dff_s #(9)  stgg_etc  (
 
  .din    ({ldst_va_m[3:0],st_rq_type_m[2:0],st_rmo_m,lsu_bst_in_pipe_m}),
 
  .din    ({ldst_va_m[3:0],st_rq_type_m[2:0],st_rmo_m,lsu_bst_in_pipe_m}),
 
  .q      ({ldst_va_g[3:0],st_rq_type_g[2:0],st_rmo_g,bst_in_pipe_g}),
 
  .q      ({ldst_va_g[3:0],st_rq_type_g[2:0],st_rmo_g,bst_in_pipe_g}),
 
  .clk    (clk),
 
  .clk    (clk),
 
  .se   (se), .si (), .so ()
 
  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
wire    bst_any_helper ;
 
wire    bst_any_helper ;
 
assign  bst_any_helper = blkst_g | bst_in_pipe_g ; // Bug 3934
 
assign  bst_any_helper = blkst_g | bst_in_pipe_g ; // Bug 3934
 
 
 
 
Line 2142... Line 1035... 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//      LD QUAD HANDLING
 
//      LD QUAD HANDLING
 
//=========================================================================================
 
//=========================================================================================
 
 
 
 
 
dff  altsp_stgm (
 
dff_s  altsp_stgm (
 
  .din    (alt_space_e), .q (alt_space_m),
 
  .din    (alt_space_e), .q (alt_space_m),
 
  .clk    (clk),
 
  .clk    (clk),
 
  .se   (se), .si (), .so ()
 
  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
assign  lsu_ldquad_inst_m = ldst_dbl_m & ld_inst_vld_m & quad_asi_m & alt_space_m ;
 
assign  lsu_ldquad_inst_m = ldst_dbl_m & ld_inst_vld_m & quad_asi_m & alt_space_m ;
 
 
 
 
 
/*wire  ldquad_inst_g ;
 
/*wire  ldquad_inst_g ;
 
dff  ldq_stgg (
 
dff_s  ldq_stgg (
 
  .din    (lsu_ldquad_inst_m), .q (ldquad_inst_g),
 
  .din    (lsu_ldquad_inst_m), .q (ldquad_inst_g),
 
  .clk    (clk),
 
  .clk    (clk),
 
  .se   (se), .si (), .so ()
 
  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
wire    ldq_stb_cam_hit ;
 
wire    ldq_stb_cam_hit ;
 
assign  ldq_stb_cam_hit = stb_cam_hit & ldquad_inst_g ;
 
assign  ldq_stb_cam_hit = stb_cam_hit & ldquad_inst_g ;
 
// Terms can be made common.
 
// Terms can be made common.
Line 2177... Line 1070... 
// A version of stb_wptr is used instead because it is easily available. (Would this have
 
// A version of stb_wptr is used instead because it is easily available. (Would this have
 
// any significant performance impact ? - No)
 
// any significant performance impact ? - No)
 
 
 
 
 
assign  ld_any_raw_vld[7:0] = stb_ld_full_raw[7:0] | stb_ld_partial_raw[7:0] ;
 
assign  ld_any_raw_vld[7:0] = stb_ld_full_raw[7:0] | stb_ld_partial_raw[7:0] ;
 
 
 
 
 
dff #(16)  stgw2_rvld (
 
dff_s #(16)  stgw2_rvld (
 
        .din    ({ld_any_raw_vld[7:0],stb_state_ced[7:0]}),
 
        .din    ({ld_any_raw_vld[7:0],stb_state_ced[7:0]}),
 
        .q      ({ld_any_raw_vld_d1[7:0],stb_state_ced_d1[7:0]}),
 
        .q      ({ld_any_raw_vld_d1[7:0],stb_state_ced_d1[7:0]}),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se),       .si (),          .so ()
 
        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
 
        );
 
        );
 
 
 
 
 
 
 
 
 
// This equation can be optimized for the grape flow.
 
// This equation can be optimized for the grape flow.
 
// This can be obtained from stb.
 
// This can be obtained from stb.
Line 2224... Line 1117... 
assign  wptr_dcd[7] =  wptr_prev[2] &  wptr_prev[1] &  wptr_prev[0] ;
 
assign  wptr_dcd[7] =  wptr_prev[2] &  wptr_prev[1] &  wptr_prev[0] ;
 
 
 
 
 
wire iold_st_ced_g,iold_st_ced_w2 ;
 
wire iold_st_ced_g,iold_st_ced_w2 ;
 
assign  iold_st_ced_g = |(wptr_dcd[7:0] & stb_state_ced[7:0]) ;
 
assign  iold_st_ced_g = |(wptr_dcd[7:0] & stb_state_ced[7:0]) ;
 
 
 
 
 
dff #(2)   ioldced_stgw2  (
 
dff_s #(2)   ioldced_stgw2  (
 
  .din  ({iold_st_ced_g,io_ld}),
 
  .din  ({iold_st_ced_g,io_ld}),
 
  .q    ({iold_st_ced_w2,io_ld_w2}),
 
  .q    ({iold_st_ced_w2,io_ld_w2}),
 
  .clk  (clk),
 
  .clk  (clk),
 
  .se   (se), .si (), .so ()
 
  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
assign  ld_rawp_st_ced_w2 =
 
assign  ld_rawp_st_ced_w2 =
 
        io_ld_w2 ? iold_st_ced_w2 :
 
        io_ld_w2 ? iold_st_ced_w2 :
 
        (~(|(ld_any_raw_vld_d1[7:0] & ~stb_state_ced_d1[7:0]))) ;
 
        (~(|(ld_any_raw_vld_d1[7:0] & ~stb_state_ced_d1[7:0]))) ;
Line 2294... Line 1187... 
 
 
 
 
assign  ld_rawp_st_ackid_g[2:0] =
 
assign  ld_rawp_st_ackid_g[2:0] =
 
  (casa_g | stb_cam_mhit | (io_ld & stb_not_empty))?
 
  (casa_g | stb_cam_mhit | (io_ld & stb_not_empty))?
 
   stb_wptr_prev[2:0] : ld_rawp_stb_id[2:0] ;
 
   stb_wptr_prev[2:0] : ld_rawp_stb_id[2:0] ;
 
 
 
 
 
dff #(3)  rawpackid_w2 (
 
dff_s #(3)  rawpackid_w2 (
 
  .din  (ld_rawp_st_ackid_g[2:0]),
 
  .din  (ld_rawp_st_ackid_g[2:0]),
 
  .q    (ld_rawp_st_ackid_w2[2:0]),
 
  .q    (ld_rawp_st_ackid_w2[2:0]),
 
  .clk  (clk),
 
  .clk  (clk),
 
  .se   (se), .si (), .so ()
 
  .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
  );
 
  );
 
 
 
 
 
 
 
 
 
   assign lsu_ifu_stbcnt0[3:0] = lsu_stbcnt0[3:0] ;
 
   assign lsu_ifu_stbcnt0[3:0] = lsu_stbcnt0[3:0] ;
 
   assign lsu_ifu_stbcnt1[3:0] = lsu_stbcnt1[3:0] ;
 
   assign lsu_ifu_stbcnt1[3:0] = lsu_stbcnt1[3:0] ;

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