| Line 16... |
Line 16... |
// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_exu_byp
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// Module Name: sparc_exu_byp
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// Description: This block includes the muxes for the bypassing for all
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// Description: This block includes the muxes for the bypassing for all
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// 3 register outputs. It also includes the pipeline registers
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// 3 register outputs. It also includes the pipeline registers
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| Line 28... |
Line 33... |
// bypassing paths and the PC. Rs2_data chooses between the normal
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// bypassing paths and the PC. Rs2_data chooses between the normal
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// bypassing paths and the immediate.
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// bypassing paths and the immediate.
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*/
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*/
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_CLK_EN
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`define FPGA_SYN_CLK_DFF
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`endif
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module sparc_exu_byp
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module sparc_exu_byp
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( /*AUTOARG*/
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( /*AUTOARG*/
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// Outputs
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// Outputs
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so, byp_alu_rs1_data_e, byp_alu_rs2_data_e_l, byp_alu_rs2_data_e,
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so, byp_alu_rs1_data_e, byp_alu_rs2_data_e_l, byp_alu_rs2_data_e,
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| Line 231... |
Line 236... |
wire ecl_byp_std_e;
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wire ecl_byp_std_e;
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wire [7:0] rd_synd_w_l;
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wire [7:0] rd_synd_w_l;
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wire [7:0] rd_synd_w2_l;
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wire [7:0] rd_synd_w2_l;
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assign clk = rclk;
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assign clk = rclk;
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`ifdef FPGA_SYN_CLK_EN
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`else
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clken_buf irf_write_clkbuf (
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.rclk (clk),
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.enb_l (sehold),
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.tmb_l (~se),
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.clk (sehold_clk)
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) ;
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`endif
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assign byp_ecc_rs1_synd_d[7:0] = ~irf_byp_rs1_data_d_l[71:64];
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assign byp_ecc_rs1_synd_d[7:0] = ~irf_byp_rs1_data_d_l[71:64];
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assign byp_ecc_rs2_synd_d[7:0] = ~irf_byp_rs2_data_d_l[71:64];
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assign byp_ecc_rs2_synd_d[7:0] = ~irf_byp_rs2_data_d_l[71:64];
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assign byp_ecc_rs3_synd_d[7:0] = ~irf_byp_rs3_data_d_l[71:64];
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assign byp_ecc_rs3_synd_d[7:0] = ~irf_byp_rs3_data_d_l[71:64];
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| Line 252... |
Line 257... |
/////////////////////////////////////////
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/////////////////////////////////////////
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dp_mux2es #(64) dfill_data_mux (.dout(dfill_data_g[63:0]),
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dp_mux2es #(64) dfill_data_mux (.dout(dfill_data_g[63:0]),
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.in0(lsu_exu_dfill_data_g[63:0]),
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.in0(lsu_exu_dfill_data_g[63:0]),
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.in1(lsu_exu_ldxa_data_g[63:0]),
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.in1(lsu_exu_ldxa_data_g[63:0]),
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.sel(ecl_byp_ldxa_g));
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.sel(ecl_byp_ldxa_g));
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dff #(64) dfill_data_dff (.din(dfill_data_g[63:0]), .clk(clk),
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dff_s #(64) dfill_data_dff (.din(dfill_data_g[63:0]), .clk(clk),
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.q(dfill_data_g2[63:0]), .se(se), .si(), .so());
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.q(dfill_data_g2[63:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
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//////////////////////////////////////////////////
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//////////////////////////////////////////////////
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// RD of PR or SR
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// RD of PR or SR
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//////////////////////////////////////////////////
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//////////////////////////////////////////////////
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| Line 280... |
Line 285... |
.sel0(ecl_byp_sel_ifex_m),
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.sel0(ecl_byp_sel_ifex_m),
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.sel1(ecl_byp_sel_ffusr_m),
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.sel1(ecl_byp_sel_ffusr_m),
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.sel2(ecl_byp_sel_tlusr_m));
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.sel2(ecl_byp_sel_tlusr_m));
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// Pipeline registers for rd_data
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// Pipeline registers for rd_data
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dff #(64) dff_rd_data_e2m(.din(rd_data_e[63:0]), .clk(clk), .q(rd_data_m[63:0]),
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dff_s #(64) dff_rd_data_e2m(.din(rd_data_e[63:0]), .clk(clk), .q(rd_data_m[63:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dp_buffer #(64) wsr_data_buf(.dout(exu_tlu_wsr_data_m[63:0]), .in(rd_data_m[63:0]));
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dp_buffer #(64) wsr_data_buf(.dout(exu_tlu_wsr_data_m[63:0]), .in(rd_data_m[63:0]));
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// Flop for storing result from restore
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// Flop for storing result from restore
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dp_mux2es #(64) restore_buf_mux(.dout(restore_rd_data_next[63:0]),
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dp_mux2es #(64) restore_buf_mux(.dout(restore_rd_data_next[63:0]),
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.in0(restore_rd_data[63:0]),
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.in0(restore_rd_data[63:0]),
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.in1(rd_data_m[63:0]),
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.in1(rd_data_m[63:0]),
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.sel(ecl_byp_restore_m));
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.sel(ecl_byp_restore_m));
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dff #(64) dff_restore_buf(.din(restore_rd_data_next[63:0]),
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dff_s #(64) dff_restore_buf(.din(restore_rd_data_next[63:0]),
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.q(restore_rd_data[63:0]), .clk(clk),
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.q(restore_rd_data[63:0]), .clk(clk),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// Mux for rd_data_m between ALU and load data and ECC result and restore result
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// Mux for rd_data_m between ALU and load data and ECC result and restore result
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mux4ds #(64) rd_data_m_mux(.dout(byp_irf_rd_data_m[63:0]),
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mux4ds #(64) rd_data_m_mux(.dout(byp_irf_rd_data_m[63:0]),
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.in0(full_rd_data_m[63:0]),
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.in0(full_rd_data_m[63:0]),
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.in1(dfill_data_g2[63:0]),
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.in1(dfill_data_g2[63:0]),
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.in2(ecc_byp_ecc_result_m[63:0]),
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.in2(ecc_byp_ecc_result_m[63:0]),
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.in3(restore_rd_data[63:0]),
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.in3(restore_rd_data[63:0]),
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.sel0(ecl_byp_sel_pipe_m),
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.sel0(ecl_byp_sel_pipe_m),
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.sel1(ecl_byp_sel_load_m),
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.sel1(ecl_byp_sel_load_m),
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.sel2(ecl_byp_sel_ecc_m),
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.sel2(ecl_byp_sel_ecc_m),
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.sel3(ecl_byp_sel_restore_m));
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.sel3(ecl_byp_sel_restore_m));
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`ifdef FPGA_SYN_CLK_DFF
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dffe #(64) dff_rd_data_m2w(.din(byp_irf_rd_data_m[63:0]), .en (~(sehold)), .clk(clk), .q(byp_irf_rd_data_w[63:0]),
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dffe_s #(64) dff_rd_data_m2w(.din(byp_irf_rd_data_m[63:0]), .en (~(sehold)), .clk(clk), .q(byp_irf_rd_data_w[63:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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`else
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dff_s #(64) dff_rd_data_m2w(.din(byp_irf_rd_data_m[63:0]), .clk(sehold_clk), .q(byp_irf_rd_data_w[63:0]),
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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`endif
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// W2 flop
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// W2 flop
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`ifdef FPGA_SYN_CLK_DFF
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dffe #(64) dff_rd_data_g2w(.din(rd_data_g[63:0]), .en (~(sehold)), .clk(clk), .q(byp_irf_rd_data_w2[63:0]),
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dffe_s #(64) dff_rd_data_g2w(.din(rd_data_g[63:0]), .en (~(sehold)), .clk(clk), .q(byp_irf_rd_data_w2[63:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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`else
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dff_s #(64) dff_rd_data_g2w(.din(rd_data_g[63:0]), .clk(sehold_clk), .q(byp_irf_rd_data_w2[63:0]),
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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`endif
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// D-E pipeline registers for rs_data
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// D-E pipeline registers for rs_data
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dff #(64) rs1_data_dff(.din(byp_alu_rs1_data_d[63:0]), .clk(clk),
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dff_s #(64) rs1_data_dff(.din(byp_alu_rs1_data_d[63:0]), .clk(clk),
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.q(byp_alu_rs1_data_e[63:0]), .se(se),
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.q(byp_alu_rs1_data_e[63:0]), .se(se),
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.si(), .so());
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`SIMPLY_RISC_SCANIN, .so());
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dff #(64) rs2_data_dff(.din(byp_alu_rs2_data_d[63:0]), .clk(clk),
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dff_s #(64) rs2_data_dff(.din(byp_alu_rs2_data_d[63:0]), .clk(clk),
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.q(byp_alu_rs2_data_e[63:0]), .se(se),
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.q(byp_alu_rs2_data_e[63:0]), .se(se),
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.si(), .so());
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`SIMPLY_RISC_SCANIN, .so());
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assign byp_alu_rs2_data_e_l[63:0] = ~byp_alu_rs2_data_e[63:0];
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assign byp_alu_rs2_data_e_l[63:0] = ~byp_alu_rs2_data_e[63:0];
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assign byp_ecl_rs2_31_e = byp_alu_rs2_data_e[31];
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assign byp_ecl_rs2_31_e = byp_alu_rs2_data_e[31];
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assign byp_ecl_rs1_63_e = byp_alu_rs1_data_e[63];
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assign byp_ecl_rs1_63_e = byp_alu_rs1_data_e[63];
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assign byp_ecl_rs1_31_e = byp_alu_rs1_data_e[31];
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assign byp_ecl_rs1_31_e = byp_alu_rs1_data_e[31];
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assign byp_ecl_rs1_2_0_e[2:0] = byp_alu_rs1_data_e[2:0];
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assign byp_ecl_rs1_2_0_e[2:0] = byp_alu_rs1_data_e[2:0];
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assign byp_ecl_rs2_3_0_e[3:0] = byp_alu_rs2_data_e[3:0];
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assign byp_ecl_rs2_3_0_e[3:0] = byp_alu_rs2_data_e[3:0];
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|
|
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dff #(64) rs3_data_dff(.din(rs3_data_d[63:0]), .clk(clk),
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dff_s #(64) rs3_data_dff(.din(rs3_data_d[63:0]), .clk(clk),
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.q(rs3_data_e[63:0]), .se(se),
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.q(rs3_data_e[63:0]), .se(se),
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.si(), .so());
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`SIMPLY_RISC_SCANIN, .so());
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dff #(32) rs3h_data_dff(.din(rs3h_data_d[31:0]), .clk(clk),
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dff_s #(32) rs3h_data_dff(.din(rs3h_data_d[31:0]), .clk(clk),
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.q(rs3h_data_e[31:0]), .se(se),
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.q(rs3h_data_e[31:0]), .se(se),
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.si(), .so());
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`SIMPLY_RISC_SCANIN, .so());
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dff #(64) rcc_data_dff(.din(byp_alu_rcc_data_d[63:0]), .clk(clk),
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dff_s #(64) rcc_data_dff(.din(byp_alu_rcc_data_d[63:0]), .clk(clk),
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.q(byp_alu_rcc_data_e[63:0]), .se(se),
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.q(byp_alu_rcc_data_e[63:0]), .se(se),
|
.si(), .so());
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`SIMPLY_RISC_SCANIN, .so());
|
|
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assign ecl_byp_std_e = ~ecl_byp_std_e_l;
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assign ecl_byp_std_e = ~ecl_byp_std_e_l;
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dp_mux2es #(64) rs2_data_out_mux(.dout(exu_lsu_rs2_data_e[63:0]),
|
dp_mux2es #(64) rs2_data_out_mux(.dout(exu_lsu_rs2_data_e[63:0]),
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.in0(byp_alu_rs2_data_e[63:0]),
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.in0(byp_alu_rs2_data_e[63:0]),
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.in1(rs3_data_e[63:0]),
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.in1(rs3_data_e[63:0]),
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| Line 507... |
Line 512... |
.sel1(ecl_byp_rs3h_mux2_sel_rf),
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.sel1(ecl_byp_rs3h_mux2_sel_rf),
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.sel2(ecl_byp_rs3h_mux2_sel_e),
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.sel2(ecl_byp_rs3h_mux2_sel_e),
|
.sel3(ecl_byp_rs3h_mux2_sel_ld));
|
.sel3(ecl_byp_rs3h_mux2_sel_ld));
|
|
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// ECC for W1
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// ECC for W1
|
|
`ifdef FPGA_SYN_CLK_DFF
|
sparc_exu_byp_eccgen w1_eccgen(.d(byp_irf_rd_data_m[63:0]),
|
sparc_exu_byp_eccgen w1_eccgen(.d(byp_irf_rd_data_m[63:0]),
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.msk(ecl_byp_ecc_mask_m_l[7:0]),
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.msk(ecl_byp_ecc_mask_m_l[7:0]),
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.p(rd_synd_w_l[7:0]),
|
.p(rd_synd_w_l[7:0]),
|
.clk(clk), .se(se));
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.clk(clk), .se(se));
|
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`else
|
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sparc_exu_byp_eccgen w1_eccgen(.d(byp_irf_rd_data_m[63:0]),
|
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.msk(ecl_byp_ecc_mask_m_l[7:0]),
|
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.p(rd_synd_w_l[7:0]),
|
|
.clk(sehold_clk), .se(se));
|
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`endif
|
assign byp_irf_rd_data_w[71:64] = ~rd_synd_w_l[7:0];
|
assign byp_irf_rd_data_w[71:64] = ~rd_synd_w_l[7:0];
|
|
|
////////////////////////
|
////////////////////////
|
// G arbitration muxes and W2 ECC
|
// G arbitration muxes and W2 ECC
|
////////////////////////
|
////////////////////////
|
| Line 530... |
Line 535... |
.in1(dfill_data_g2[63:0]),
|
.in1(dfill_data_g2[63:0]),
|
.in2(restore_rd_data[63:0]),
|
.in2(restore_rd_data[63:0]),
|
.sel0(ecl_byp_sel_muldiv_g),
|
.sel0(ecl_byp_sel_muldiv_g),
|
.sel1(ecl_byp_sel_load_g),
|
.sel1(ecl_byp_sel_load_g),
|
.sel2(ecl_byp_sel_restore_g));
|
.sel2(ecl_byp_sel_restore_g));
|
|
`ifdef FPGA_SYN_CLK_DFF
|
sparc_exu_byp_eccgen w2_eccgen(.d(rd_data_g[63:0]),
|
sparc_exu_byp_eccgen w2_eccgen(.d(rd_data_g[63:0]),
|
.msk(ecl_byp_ecc_mask_m_l[7:0]),
|
.msk(ecl_byp_ecc_mask_m_l[7:0]),
|
.p(rd_synd_w2_l[7:0]),
|
.p(rd_synd_w2_l[7:0]),
|
.clk(clk), .se(se));
|
.clk(clk), .se(se));
|
|
`else
|
|
sparc_exu_byp_eccgen w2_eccgen(.d(rd_data_g[63:0]),
|
|
.msk(ecl_byp_ecc_mask_m_l[7:0]),
|
|
.p(rd_synd_w2_l[7:0]),
|
|
.clk(sehold_clk), .se(se));
|
|
`endif
|
assign byp_irf_rd_data_w2[71:64] = ~rd_synd_w2_l[7:0];
|
assign byp_irf_rd_data_w2[71:64] = ~rd_synd_w2_l[7:0];
|
|
|
endmodule // sparc_exu_byp
|
endmodule // sparc_exu_byp
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|
|
|
|
