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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_exu_div
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// Module Name: sparc_exu_div
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*/
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*/
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module sparc_exu_div (/*AUTOARG*/
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module sparc_exu_div (/*AUTOARG*/
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.sel1(ecl_div_sel_adder),
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.sel1(ecl_div_sel_adder),
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.sel2(ecl_div_ld_inputs));
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.sel2(ecl_div_ld_inputs));
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assign div_ecl_d_62 = d[62];
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assign div_ecl_d_62 = d[62];
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// FF for d
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// FF for d
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dff #(128) d_dff(.din(dnext[127:0]), .clk(clk), .q(d[127:0]), .se(se), .si(), .so());
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dff_s #(128) d_dff(.din(dnext[127:0]), .clk(clk), .q(d[127:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
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////////////////////////////
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////////////////////////////
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// Logic for X (divisor)
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// Logic for X (divisor)
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////////////////////////////
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////////////////////////////
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// if signed div and 32 bits sign extend to upper 32 bits
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// if signed div and 32 bits sign extend to upper 32 bits
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.sel0(ecl_div_keepx),
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.sel0(ecl_div_keepx),
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.sel1(ecl_div_ld_inputs),
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.sel1(ecl_div_ld_inputs),
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.sel2(ecl_div_almostlast_cycle));
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.sel2(ecl_div_almostlast_cycle));
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// FF for x
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// FF for x
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dff #(64) x_dff(.din(xnext[63:0]), .clk(clk), .q(x[63:0]), .se(se), .si(), .so());
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dff_s #(64) x_dff(.din(xnext[63:0]), .clk(clk), .q(x[63:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
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///////////////////////////
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///////////////////////////
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// Logic for inputs to adder
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// Logic for inputs to adder
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//////////////////////////
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//////////////////////////
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.in1(mul32_input_data_e[127:0]),
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.in1(mul32_input_data_e[127:0]),
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.in2(mul_data_out[127:0]),
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.in2(mul_data_out[127:0]),
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.sel0(ecl_div_mul_get_new_data),
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.sel0(ecl_div_mul_get_new_data),
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.sel1(ecl_div_mul_get_32bit_data),
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.sel1(ecl_div_mul_get_32bit_data),
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.sel2(ecl_div_mul_keep_data));
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.sel2(ecl_div_mul_keep_data));
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dff #(128) mul_data_dff(.din(next_mul_data[127:0]), .clk(clk), .q(mul_data_out[127:0]),
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dff_s #(128) mul_data_dff(.din(next_mul_data[127:0]), .clk(clk), .q(mul_data_out[127:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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assign exu_mul_rs1_data = mul_data_out[63:0];
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assign exu_mul_rs1_data = mul_data_out[63:0];
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assign exu_mul_rs2_data = mul_data_out[127:64];
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assign exu_mul_rs2_data = mul_data_out[127:64];
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///////////////////////////////////
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///////////////////////////////////
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// Store output from mul
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// Store output from mul
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//////////////////////////////////
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//////////////////////////////////
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dp_mux2es #(64) mul_result_mux(.dout(mul_result_next[63:0]), .in0(mul_result[63:0]),
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dp_mux2es #(64) mul_result_mux(.dout(mul_result_next[63:0]), .in0(mul_result[63:0]),
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.in1(mul_exu_data_g[63:0]),
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.in1(mul_exu_data_g[63:0]),
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.sel(ecl_div_mul_wen));
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.sel(ecl_div_mul_wen));
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dff #(64) mul_result_dff(.din(mul_result_next[63:0]), .clk(clk), .q(mul_result[63:0]),
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dff_s #(64) mul_result_dff(.din(mul_result_next[63:0]), .clk(clk), .q(mul_result[63:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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endmodule // sparc_exu_div
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endmodule // sparc_exu_div
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