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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_exu_div_yreg
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// Module Name: sparc_exu_div_yreg
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// Description: The 4 32 bit y registers. It can be written to
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// Description: The 4 32 bit y registers. It can be written to
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// twice each cycle because by definition the writes must come
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// twice each cycle because by definition the writes must come
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//////////////////////////////////
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//////////////////////////////////
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// output the LSB of all 4 regs
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// output the LSB of all 4 regs
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assign div_ecl_yreg_0[3:0] = {yreg_thr3[0],yreg_thr2[0],yreg_thr1[0],yreg_thr0[0]};
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assign div_ecl_yreg_0[3:0] = {yreg_thr3[0],yreg_thr2[0],yreg_thr1[0],yreg_thr0[0]};
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assign div_ecl_yreg_0_l[3:0] = ~div_ecl_yreg_0[3:0];
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assign div_ecl_yreg_0_l[3:0] = ~div_ecl_yreg_0[3:0];
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`ifdef FPGA_SYN_1THREAD
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assign yreg_mdq_y_e[31:0] = yreg_thr0[31:0];
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`else
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// mux between the 4 yregs
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// mux between the 4 yregs
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mux4ds #(32) mux_yreg_out(.dout(yreg_mdq_y_e[31:0]), .sel0(ecl_div_thr_e[0]),
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mux4ds #(32) mux_yreg_out(.dout(yreg_mdq_y_e[31:0]), .sel0(ecl_div_thr_e[0]),
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.sel1(ecl_div_thr_e[1]), .sel2(ecl_div_thr_e[2]),
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.sel1(ecl_div_thr_e[1]), .sel2(ecl_div_thr_e[2]),
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.sel3(ecl_div_thr_e[3]), .in0(yreg_thr0[31:0]),
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.sel3(ecl_div_thr_e[3]), .in0(yreg_thr0[31:0]),
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.in1(yreg_thr1[31:0]), .in2(yreg_thr2[31:0]),
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.in1(yreg_thr1[31:0]), .in2(yreg_thr2[31:0]),
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.in3(yreg_thr3[31:0]));
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.in3(yreg_thr3[31:0]));
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`endif
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//////////////////////////////////////
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//////////////////////////////////////
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// Storage of yreg
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// Storage of yreg
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//////////////////////////////////////
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//////////////////////////////////////
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// pass along yreg w to w2 (for control signal timing)
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// pass along yreg w to w2 (for control signal timing)
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dff #(32) yreg_dff_w2w2(.din(byp_div_yreg_data_w[31:0]), .clk(clk), .q(yreg_data_w1[31:0]),
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dff_s #(32) yreg_dff_w2w2(.din(byp_div_yreg_data_w[31:0]), .clk(clk), .q(yreg_data_w1[31:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// mux between yreg_w, yreg_g, old value
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// mux between yreg_w, yreg_g, old value
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mux4ds #(32) mux_yregin0(.dout(next_yreg_thr0[31:0]),
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mux4ds #(32) mux_yregin0(.dout(next_yreg_thr0[31:0]),
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.sel0(ecl_div_yreg_wen_w[0]),
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.sel0(ecl_div_yreg_wen_w[0]),
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.sel3(ecl_div_yreg_shift_g[0]),
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.sel3(ecl_div_yreg_shift_g[0]),
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.in0(yreg_data_w1[31:0]),
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.in0(yreg_data_w1[31:0]),
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.in1(mul_div_yreg_data_g[31:0]),
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.in1(mul_div_yreg_data_g[31:0]),
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.in2(yreg_thr0[31:0]),
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.in2(yreg_thr0[31:0]),
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.in3({ecl_div_yreg_data_31_g, yreg_thr0[31:1]}));
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.in3({ecl_div_yreg_data_31_g, yreg_thr0[31:1]}));
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`ifdef FPGA_SYN_1THREAD
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assign next_yreg_thr1[31:0] = yreg_data_w1[31:0];
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assign next_yreg_thr2[31:0] = yreg_data_w1[31:0];
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assign next_yreg_thr3[31:0] = yreg_data_w1[31:0];
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`else
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mux4ds #(32) mux_yregin1(.dout(next_yreg_thr1[31:0]),
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mux4ds #(32) mux_yregin1(.dout(next_yreg_thr1[31:0]),
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.sel0(ecl_div_yreg_wen_w[1]),
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.sel0(ecl_div_yreg_wen_w[1]),
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.sel1(ecl_div_yreg_wen_g[1]),
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.sel1(ecl_div_yreg_wen_g[1]),
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.sel2(ecl_div_yreg_wen_l[1]),
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.sel2(ecl_div_yreg_wen_l[1]),
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.sel3(ecl_div_yreg_shift_g[3]),
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.sel3(ecl_div_yreg_shift_g[3]),
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.in0(yreg_data_w1[31:0]),
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.in0(yreg_data_w1[31:0]),
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.in1(mul_div_yreg_data_g[31:0]),
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.in1(mul_div_yreg_data_g[31:0]),
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.in2(yreg_thr3[31:0]),
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.in2(yreg_thr3[31:0]),
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.in3({ecl_div_yreg_data_31_g, yreg_thr3[31:1]}));
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.in3({ecl_div_yreg_data_31_g, yreg_thr3[31:1]}));
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// !`ifdef FPGA_SYN_1THREAD
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`endif // !`ifdef FPGA_SYN_1THREAD
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// store new value
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// store new value
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dff #(32) dff_yreg_thr0(.din(next_yreg_thr0[31:0]), .clk(clk), .q(yreg_thr0[31:0]),
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dff_s #(32) dff_yreg_thr0(.din(next_yreg_thr0[31:0]), .clk(clk), .q(yreg_thr0[31:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(32) dff_yreg_thr1(.din(next_yreg_thr1[31:0]), .clk(clk), .q(yreg_thr1[31:0]),
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dff_s #(32) dff_yreg_thr1(.din(next_yreg_thr1[31:0]), .clk(clk), .q(yreg_thr1[31:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(32) dff_yreg_thr2(.din(next_yreg_thr2[31:0]), .clk(clk), .q(yreg_thr2[31:0]),
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dff_s #(32) dff_yreg_thr2(.din(next_yreg_thr2[31:0]), .clk(clk), .q(yreg_thr2[31:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(32) dff_yreg_thr3(.din(next_yreg_thr3[31:0]), .clk(clk), .q(yreg_thr3[31:0]),
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dff_s #(32) dff_yreg_thr3(.din(next_yreg_thr3[31:0]), .clk(clk), .q(yreg_thr3[31:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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endmodule // sparc_exu_div_yreg
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endmodule // sparc_exu_div_yreg
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