| Line 16... |
Line 16... |
// You should have received a copy of the GNU General Public
|
// You should have received a copy of the GNU General Public
|
// License along with this work; if not, write to the Free Software
|
// License along with this work; if not, write to the Free Software
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
//
|
//
|
// ========== Copyright Header End ============================================
|
// ========== Copyright Header End ============================================
|
|
`ifdef SIMPLY_RISC_TWEAKS
|
|
`define SIMPLY_RISC_SCANIN .si(0)
|
|
`else
|
|
`define SIMPLY_RISC_SCANIN .si()
|
|
`endif
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
/*
|
/*
|
// Module Name: sparc_exu_ecl
|
// Module Name: sparc_exu_ecl
|
// Description: Implements all the control logic for the exu.
|
// Description: Implements all the control logic for the exu.
|
// This includes: bypass logic, ccr control and ccr bypassing,
|
// This includes: bypass logic, ccr control and ccr bypassing,
|
| Line 619... |
Line 624... |
assign clk = rclk;
|
assign clk = rclk;
|
// Reset flop
|
// Reset flop
|
dffrl_async rstff(.din (grst_l),
|
dffrl_async rstff(.din (grst_l),
|
.q (ecl_reset_l),
|
.q (ecl_reset_l),
|
.clk (clk),
|
.clk (clk),
|
.rst_l (arst_l), .se(se), .si(), .so());
|
.rst_l (arst_l), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign reset = ~ecl_reset_l;
|
assign reset = ~ecl_reset_l;
|
|
|
// Pipeline flops for irf control signals
|
// Pipeline flops for irf control signals
|
dff #(5) dff_rs1_s2d(.din(ifu_exu_rs1_s[4:0]), .clk(clk), .q(ifu_exu_rs1_d[4:0]), .se(se),
|
dff_s #(5) dff_rs1_s2d(.din(ifu_exu_rs1_s[4:0]), .clk(clk), .q(ifu_exu_rs1_d[4:0]), .se(se),
|
.si(),.so());
|
`SIMPLY_RISC_SCANIN,.so());
|
dff #(5) dff_rs2_s2d(.din(ifu_exu_rs2_s[4:0]), .clk(clk), .q(ifu_exu_rs2_d[4:0]), .se(se),
|
dff_s #(5) dff_rs2_s2d(.din(ifu_exu_rs2_s[4:0]), .clk(clk), .q(ifu_exu_rs2_d[4:0]), .se(se),
|
.si(),.so());
|
`SIMPLY_RISC_SCANIN,.so());
|
dff #(5) dff_rs3_s2d(.din(ifu_exu_rs3_s[4:0]), .clk(clk), .q(ifu_exu_rs3_d[4:0]), .se(se),
|
dff_s #(5) dff_rs3_s2d(.din(ifu_exu_rs3_s[4:0]), .clk(clk), .q(ifu_exu_rs3_d[4:0]), .se(se),
|
.si(),.so());
|
`SIMPLY_RISC_SCANIN,.so());
|
dff #(5) dff_rs1_d2e(.din(ifu_exu_rs1_d[4:0]), .clk(clk), .q(ifu_exu_rs1_e[4:0]), .se(se),
|
dff_s #(5) dff_rs1_d2e(.din(ifu_exu_rs1_d[4:0]), .clk(clk), .q(ifu_exu_rs1_e[4:0]), .se(se),
|
.si(),.so());
|
`SIMPLY_RISC_SCANIN,.so());
|
dff #(5) dff_rs2_d2e(.din(ifu_exu_rs2_d[4:0]), .clk(clk), .q(ifu_exu_rs2_e[4:0]), .se(se),
|
dff_s #(5) dff_rs2_d2e(.din(ifu_exu_rs2_d[4:0]), .clk(clk), .q(ifu_exu_rs2_e[4:0]), .se(se),
|
.si(),.so());
|
`SIMPLY_RISC_SCANIN,.so());
|
dff #(5) dff_rs3_d2e(.din(ifu_exu_rs3_d[4:0]), .clk(clk), .q(ifu_exu_rs3_e[4:0]), .se(se),
|
dff_s #(5) dff_rs3_d2e(.din(ifu_exu_rs3_d[4:0]), .clk(clk), .q(ifu_exu_rs3_e[4:0]), .se(se),
|
.si(),.so());
|
`SIMPLY_RISC_SCANIN,.so());
|
dff #(5) dff_rs1_e2m(.din(ifu_exu_rs1_e[4:0]), .clk(clk), .q(ifu_exu_rs1_m[4:0]), .se(se),
|
dff_s #(5) dff_rs1_e2m(.din(ifu_exu_rs1_e[4:0]), .clk(clk), .q(ifu_exu_rs1_m[4:0]), .se(se),
|
.si(),.so());
|
`SIMPLY_RISC_SCANIN,.so());
|
dff #(5) dff_rs2_e2m(.din(ifu_exu_rs2_e[4:0]), .clk(clk), .q(ifu_exu_rs2_m[4:0]), .se(se),
|
dff_s #(5) dff_rs2_e2m(.din(ifu_exu_rs2_e[4:0]), .clk(clk), .q(ifu_exu_rs2_m[4:0]), .se(se),
|
.si(),.so());
|
`SIMPLY_RISC_SCANIN,.so());
|
dff #(5) dff_rs3_e2m(.din(ifu_exu_rs3_e[4:0]), .clk(clk), .q(ifu_exu_rs3_m[4:0]), .se(se),
|
dff_s #(5) dff_rs3_e2m(.din(ifu_exu_rs3_e[4:0]), .clk(clk), .q(ifu_exu_rs3_m[4:0]), .se(se),
|
.si(),.so());
|
`SIMPLY_RISC_SCANIN,.so());
|
dff #(5) dff_ld_rd_m2g(.din(lsu_exu_rd_m[4:0]), .clk(clk), .q(ld_rd_g[4:0]), .se(se), .si(), .so());
|
dff_s #(5) dff_ld_rd_m2g(.din(lsu_exu_rd_m[4:0]), .clk(clk), .q(ld_rd_g[4:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(2) dff_ld_tid_m2g(.din(lsu_exu_thr_m[1:0]), .clk(clk), .q(ld_tid_g[1:0]), .se(se), .si(), .so());
|
dff_s #(2) dff_ld_tid_m2g(.din(lsu_exu_thr_m[1:0]), .clk(clk), .q(ld_tid_g[1:0]), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// Pipeline flops for control signals
|
// Pipeline flops for control signals
|
dff #(3) dff_aluop_d2e(.din(ifu_exu_aluop_d[2:0]), .clk(clk), .q(ifu_exu_aluop_e[2:0]),
|
dff_s #(3) dff_aluop_d2e(.din(ifu_exu_aluop_d[2:0]), .clk(clk), .q(ifu_exu_aluop_e[2:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(3) dff_shiftop_d2e(.din(shiftop_d[2:0]), .clk(clk),
|
dff_s #(3) dff_shiftop_d2e(.din(shiftop_d[2:0]), .clk(clk),
|
.q(shiftop_e[2:0]), .se(se),
|
.q(shiftop_e[2:0]), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff dff_enshift_d2e(.din(ifu_exu_enshift_d), .clk(clk), .q(enshift_e),
|
dff_s dff_enshift_d2e(.din(ifu_exu_enshift_d), .clk(clk), .q(enshift_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff dff_sel_sum_d2e(.din(sel_sum_d), .clk(clk), .q(sel_sum_e),
|
dff_s dff_sel_sum_d2e(.din(sel_sum_d), .clk(clk), .q(sel_sum_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff dff_tv_d2e(.din(ifu_exu_tv_d), .clk(clk), .q(ifu_exu_tv_e),
|
dff_s dff_tv_d2e(.din(ifu_exu_tv_d), .clk(clk), .q(ifu_exu_tv_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff dff_tagop_d2e(.din(ifu_exu_tagop_d), .clk(clk), .q(ifu_exu_tagop_e),
|
dff_s dff_tagop_d2e(.din(ifu_exu_tagop_d), .clk(clk), .q(ifu_exu_tagop_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff dff_ialign_d2e(.din(ifu_exu_ialign_d), .clk(clk), .q(ialign_e),
|
dff_s dff_ialign_d2e(.din(ifu_exu_ialign_d), .clk(clk), .q(ialign_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff dff_ialign_e2m(.din(ialign_e), .clk(clk), .q(ialign_m),
|
dff_s dff_ialign_e2m(.din(ialign_e), .clk(clk), .q(ialign_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff ldxa_dff(.din(lsu_exu_ldxa_m), .clk(clk), .q(ldxa_g), .se(se), .si(), .so());
|
dff_s ldxa_dff(.din(lsu_exu_ldxa_m), .clk(clk), .q(ldxa_g), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff sethi_d2e(.din(ifu_exu_sethi_inst_d), .clk(clk), .q(sethi_e), .se(se), .si(), .so());
|
dff_s sethi_d2e(.din(ifu_exu_sethi_inst_d), .clk(clk), .q(sethi_e), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff rs1_vld_d2e(.din(ifu_exu_rs1_vld_d), .clk(clk), .q(rs1_vld_e), .se(se), .si(), .so());
|
dff_s rs1_vld_d2e(.din(ifu_exu_rs1_vld_d), .clk(clk), .q(rs1_vld_e), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff rs2_vld_d2e(.din(ifu_exu_rs2_vld_d), .clk(clk), .q(rs2_vld_e), .se(se), .si(), .so());
|
dff_s rs2_vld_d2e(.din(ifu_exu_rs2_vld_d), .clk(clk), .q(rs2_vld_e), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign rs3_vld_d = ifu_exu_rs3e_vld_d | ifu_exu_rs3o_vld_d;
|
assign rs3_vld_d = ifu_exu_rs3e_vld_d | ifu_exu_rs3o_vld_d;
|
dff rs3_vld_d2e(.din(rs3_vld_d), .q(rs3_vld_e), .clk(clk), .se(se), .si(), .so());
|
dff_s rs3_vld_d2e(.din(rs3_vld_d), .q(rs3_vld_e), .clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff casa_d2e(.din(ifu_exu_casa_d), .q(ecl_alu_casa_e), .clk(clk), .se(se), .si(), .so());
|
dff_s casa_d2e(.din(ifu_exu_casa_d), .q(ecl_alu_casa_e), .clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
///////////////////////////////
|
///////////////////////////////
|
// ALU Control
|
// ALU Control
|
///////////////////////////////
|
///////////////////////////////
|
// Decode opcode for ALU
|
// Decode opcode for ALU
|
| Line 711... |
Line 716... |
assign read_tlusr_e = ~ifu_exu_use_rsr_e_l & ~ifu_exu_rd_ffusr_e & ~ifu_exu_rd_ifusr_e & ~ifu_exu_rd_exusr_e;
|
assign read_tlusr_e = ~ifu_exu_use_rsr_e_l & ~ifu_exu_rd_ffusr_e & ~ifu_exu_rd_ifusr_e & ~ifu_exu_rd_exusr_e;
|
assign ecl_byp_sel_ffusr_m = read_ffusr_m;
|
assign ecl_byp_sel_ffusr_m = read_ffusr_m;
|
assign ecl_byp_sel_tlusr_m = read_tlusr_m & ~read_ffusr_m;
|
assign ecl_byp_sel_tlusr_m = read_tlusr_m & ~read_ffusr_m;
|
assign ecl_byp_sel_ifex_m = ~read_tlusr_m & ~read_ffusr_m;
|
assign ecl_byp_sel_ifex_m = ~read_tlusr_m & ~read_ffusr_m;
|
|
|
dff #(2) rsr_e2m(.din({read_ffusr_e, read_tlusr_e}), .clk(clk),
|
dff_s #(2) rsr_e2m(.din({read_ffusr_e, read_tlusr_e}), .clk(clk),
|
.q({read_ffusr_m, read_tlusr_m}), .se(se), .si(), .so());
|
.q({read_ffusr_m, read_tlusr_m}), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// ecc checking on rs3 will be cancelled if mov happens
|
// ecc checking on rs3 will be cancelled if mov happens
|
assign cancel_rs3_ecc_e = ~dont_move_e & is_logic_e;
|
assign cancel_rs3_ecc_e = ~dont_move_e & is_logic_e;
|
|
|
// compute xor for write to cwp
|
// compute xor for write to cwp
|
| Line 736... |
Line 741... |
.sel3(thr_d[3]));
|
.sel3(thr_d[3]));
|
|
|
assign zero_rs2_d = ifu_exu_muls_d & ~div_ecl_yreg_0_d;
|
assign zero_rs2_d = ifu_exu_muls_d & ~div_ecl_yreg_0_d;
|
|
|
assign next_yreg_data_31 = (muls_e)? byp_ecl_rs1_2_0_e[0]:ecl_div_yreg_data_31_g;
|
assign next_yreg_data_31 = (muls_e)? byp_ecl_rs1_2_0_e[0]:ecl_div_yreg_data_31_g;
|
dff dff_rs1_b0_m2w(.din(next_yreg_data_31), .clk(clk), .q(ecl_div_yreg_data_31_g),
|
dff_s dff_rs1_b0_m2w(.din(next_yreg_data_31), .clk(clk), .q(ecl_div_yreg_data_31_g),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// Logic for carryin and subtract
|
// Logic for carryin and subtract
|
assign c_used_d = ~(ifu_exu_invert_d ^ ~(exu_ifu_cc_d[0] & ifu_exu_usecin_d));
|
assign c_used_d = ~(ifu_exu_invert_d ^ ~(exu_ifu_cc_d[0] & ifu_exu_usecin_d));
|
// Pipeline flops
|
// Pipeline flops
|
dff sub_dff(.din(ifu_exu_invert_d), .clk(clk), .q(sub_e), .se(se),
|
dff_s sub_dff(.din(ifu_exu_invert_d), .clk(clk), .q(sub_e), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff c_used_dff(.din(c_used_d), .clk(clk), .q(ecl_alu_cin_e), .se(se),
|
dff_s c_used_dff(.din(c_used_d), .clk(clk), .q(ecl_alu_cin_e), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff dff_muls_d2e(.din(ifu_exu_muls_d), .clk(clk), .q(muls_e),
|
dff_s dff_muls_d2e(.din(ifu_exu_muls_d), .clk(clk), .q(muls_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff zero_rs2_dff(.din(zero_rs2_d), .clk(clk), .q(ecl_div_zero_rs2_e),
|
dff_s zero_rs2_dff(.din(zero_rs2_d), .clk(clk), .q(ecl_div_zero_rs2_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(2) cc_d2e(.din({exu_ifu_cc_d[3],exu_ifu_cc_d[1]}), .clk(clk), .q({cc_e_3,cc_e_1}),
|
dff_s #(2) cc_d2e(.din({exu_ifu_cc_d[3],exu_ifu_cc_d[1]}), .clk(clk), .q({cc_e_3,cc_e_1}),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff mulsrs131_e2m(.din(ecl_div_muls_rs1_31_e_l), .clk(clk),
|
dff_s mulsrs131_e2m(.din(ecl_div_muls_rs1_31_e_l), .clk(clk),
|
.q(muls_rs1_31_m_l),
|
.q(muls_rs1_31_m_l),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff rs2_31_e2m(.din(byp_ecl_rs2_31_e), .clk(clk),
|
dff_s rs2_31_e2m(.din(byp_ecl_rs2_31_e), .clk(clk),
|
.q(rs2_data_31_m), .se(se), .si(), .so());
|
.q(rs2_data_31_m), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff save_dff(.din(ifu_exu_save_d), .clk(clk), .q(save_e), .se(se),
|
dff_s save_dff(.din(ifu_exu_save_d), .clk(clk), .q(save_e), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff restore_dff(.din(ifu_exu_restore_d), .clk(clk), .q(restore_e), .se(se),
|
dff_s restore_dff(.din(ifu_exu_restore_d), .clk(clk), .q(restore_e), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
|
|
// Condition code generation
|
// Condition code generation
|
assign adder_xcc[0] = (~alu_ecl_cout64_e_l ^ sub_e) & sel_sum_e;
|
assign adder_xcc[0] = (~alu_ecl_cout64_e_l ^ sub_e) & sel_sum_e;
|
assign adder_icc[0] = (alu_ecl_cout32_e ^ sub_e) & sel_sum_e;
|
assign adder_icc[0] = (alu_ecl_cout32_e ^ sub_e) & sel_sum_e;
|
/* -----\/----- EXCLUDED -----\/-----
|
/* -----\/----- EXCLUDED -----\/-----
|
| Line 808... |
Line 813... |
assign exu_ifu_va_oor_m = ~alu_ecl_mem_addr_invalid_m_l;
|
assign exu_ifu_va_oor_m = ~alu_ecl_mem_addr_invalid_m_l;
|
assign exu_tlu_va_oor_m = (~alu_ecl_mem_addr_invalid_m_l &
|
assign exu_tlu_va_oor_m = (~alu_ecl_mem_addr_invalid_m_l &
|
ifu_exu_range_check_other_m);
|
ifu_exu_range_check_other_m);
|
assign exu_tlu_va_oor_jl_ret_m = (~alu_ecl_mem_addr_invalid_m_l &
|
assign exu_tlu_va_oor_jl_ret_m = (~alu_ecl_mem_addr_invalid_m_l &
|
ifu_exu_range_check_jlret_m);
|
ifu_exu_range_check_jlret_m);
|
dff dff_addr_mask_d2e (.din(ifu_exu_addr_mask_d), .clk(clk), .q(addr_mask_e),
|
dff_s dff_addr_mask_d2e (.din(ifu_exu_addr_mask_d), .clk(clk), .q(addr_mask_e),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff dff_mem_invalid_e2m(.din(alu_ecl_mem_addr_invalid_e_l), .clk(clk),
|
dff_s dff_mem_invalid_e2m(.din(alu_ecl_mem_addr_invalid_e_l), .clk(clk),
|
.q(alu_ecl_mem_addr_invalid_m_l), .se(se),
|
.q(alu_ecl_mem_addr_invalid_m_l), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff dff_misalign_addr_e2m(.din(misalign_addr_e), .clk(clk),
|
dff_s dff_misalign_addr_e2m(.din(misalign_addr_e), .clk(clk),
|
.q(exu_tlu_misalign_addr_jmpl_rtn_m), .se(se),
|
.q(exu_tlu_misalign_addr_jmpl_rtn_m), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff dff_range_check_jlret_d2e(.din(ifu_exu_range_check_jlret_d), .clk(clk),
|
dff_s dff_range_check_jlret_d2e(.din(ifu_exu_range_check_jlret_d), .clk(clk),
|
.q(ifu_exu_range_check_jlret_e), .se(se),
|
.q(ifu_exu_range_check_jlret_e), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff dff_range_check_jlret_e2m(.din(valid_range_check_jlret_e), .clk(clk),
|
dff_s dff_range_check_jlret_e2m(.din(valid_range_check_jlret_e), .clk(clk),
|
.q(ifu_exu_range_check_jlret_m), .se(se),
|
.q(ifu_exu_range_check_jlret_m), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff dff_range_check_other_d2e(.din(ifu_exu_range_check_other_d), .clk(clk),
|
dff_s dff_range_check_other_d2e(.din(ifu_exu_range_check_other_d), .clk(clk),
|
.q(ifu_exu_range_check_other_e), .se(se),
|
.q(ifu_exu_range_check_other_e), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff dff_range_check_other_e2m(.din(ifu_exu_range_check_other_e), .clk(clk),
|
dff_s dff_range_check_other_e2m(.din(ifu_exu_range_check_other_e), .clk(clk),
|
.q(ifu_exu_range_check_other_m), .se(se),
|
.q(ifu_exu_range_check_other_m), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
|
|
// 3lsbs can be zeroes for ialign
|
// 3lsbs can be zeroes for ialign
|
assign ecl_byp_3lsb_m[2:0] = (ialign_m)? 3'b0: byp_ecl_rd_data_3lsb_m[2:0];
|
assign ecl_byp_3lsb_m[2:0] = (ialign_m)? 3'b0: byp_ecl_rd_data_3lsb_m[2:0];
|
|
|
/////////////////////////////
|
/////////////////////////////
|
| Line 872... |
Line 877... |
assign ecl_shft_shift1_e[2] = (byp_ecl_rs2_3_0_e[1] & ~byp_ecl_rs2_3_0_e[0]);
|
assign ecl_shft_shift1_e[2] = (byp_ecl_rs2_3_0_e[1] & ~byp_ecl_rs2_3_0_e[0]);
|
assign ecl_shft_shift1_e[3] = (byp_ecl_rs2_3_0_e[1] & byp_ecl_rs2_3_0_e[0]);
|
assign ecl_shft_shift1_e[3] = (byp_ecl_rs2_3_0_e[1] & byp_ecl_rs2_3_0_e[0]);
|
|
|
|
|
// pipeline flops for bypass data
|
// pipeline flops for bypass data
|
dff #(5) dff_rd_d2e(.din(ifu_exu_rd_d[4:0]), .clk(clk), .q(rd_e[4:0]), .se(se),
|
dff_s #(5) dff_rd_d2e(.din(ifu_exu_rd_d[4:0]), .clk(clk), .q(rd_e[4:0]), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
// account for switch of ins outs on save/restore
|
// account for switch of ins outs on save/restore
|
assign real_rd_e[4] = rd_e[4] ^ (rd_e[3] & (save_e | restore_e));
|
assign real_rd_e[4] = rd_e[4] ^ (rd_e[3] & (save_e | restore_e));
|
assign real_rd_e[3:0] = rd_e[3:0];
|
assign real_rd_e[3:0] = rd_e[3:0];
|
dff #(5) dff_rd_e2m(.din(real_rd_e[4:0]), .clk(clk), .q(rd_m[4:0]), .se(se),
|
dff_s #(5) dff_rd_e2m(.din(real_rd_e[4:0]), .clk(clk), .q(rd_m[4:0]), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff #(5) dff_rd_m2w(.din(ecl_irf_rd_m[4:0]), .clk(clk), .q(ecl_irf_rd_w[4:0]), .se(se),
|
dff_s #(5) dff_rd_m2w(.din(ecl_irf_rd_m[4:0]), .clk(clk), .q(ecl_irf_rd_w[4:0]), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff #(2) dff_thr_s2d(.din(ifu_exu_tid_s2[1:0]), .clk(clk), .q(tid_d[1:0]), .se(se),
|
dff_s #(2) dff_thr_s2d(.din(ifu_exu_tid_s2[1:0]), .clk(clk), .q(tid_d[1:0]), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff #(2) dff_tid_d2e(.din(tid_d[1:0]), .clk(clk), .q(tid_e[1:0]), .se(se),
|
dff_s #(2) dff_tid_d2e(.din(tid_d[1:0]), .clk(clk), .q(tid_e[1:0]), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff #(2) dff_thr_e2m(.din(tid_e[1:0]), .clk(clk), .q(tid_m[1:0]), .se(se),
|
dff_s #(2) dff_thr_e2m(.din(tid_e[1:0]), .clk(clk), .q(tid_m[1:0]), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
// Need the original thr and the one with ld thr muxed in
|
// Need the original thr and the one with ld thr muxed in
|
dff #(2) dff_tid_m2w(.din(tid_m[1:0]), .clk(clk), .q(tid_w[1:0]), .se(se),
|
dff_s #(2) dff_tid_m2w(.din(tid_m[1:0]), .clk(clk), .q(tid_w[1:0]), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff #(2) dff_tid_w2w1(.din(tid_w[1:0]), .clk(clk), .q(tid_w1[1:0]), .se(se),
|
dff_s #(2) dff_tid_w2w1(.din(tid_w[1:0]), .clk(clk), .q(tid_w1[1:0]), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
dff #(2) dff_irf_thr_m2w(.din(ecl_irf_tid_m[1:0]), .clk(clk), .q(ecl_irf_tid_w[1:0]), .se(se),
|
dff_s #(2) dff_irf_thr_m2w(.din(ecl_irf_tid_m[1:0]), .clk(clk), .q(ecl_irf_tid_w[1:0]), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
|
|
// Thread decode
|
// Thread decode
|
// decode tid_d
|
// decode tid_d
|
assign thr_d[0] = ~tid_d[1] & ~tid_d[0];
|
assign thr_d[0] = ~tid_d[1] & ~tid_d[0];
|
assign thr_d[1] = ~tid_d[1] & tid_d[0];
|
assign thr_d[1] = ~tid_d[1] & tid_d[0];
|
| Line 950... |
Line 955... |
assign perr_clear_w[3] = tid_w[1] & tid_w[0] & perr_store[3] & ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
|
assign perr_clear_w[3] = tid_w[1] & tid_w[0] & perr_store[3] & ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
|
assign perr_clear_w[2] = tid_w[1] & ~tid_w[0] & perr_store[2] & ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
|
assign perr_clear_w[2] = tid_w[1] & ~tid_w[0] & perr_store[2] & ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
|
assign perr_clear_w[1] = ~tid_w[1] & tid_w[0] & perr_store[1] & ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
|
assign perr_clear_w[1] = ~tid_w[1] & tid_w[0] & perr_store[1] & ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
|
assign perr_clear_w[0] = ~tid_w[1] & ~tid_w[0] & perr_store[0] & ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
|
assign perr_clear_w[0] = ~tid_w[1] & ~tid_w[0] & perr_store[0] & ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
|
|
|
dffr #(4) perr_dff(.din(perr_store_next[3:0]), .clk(clk), .q(perr_store[3:0]), .si(), .so(), .se(se), .rst(reset));
|
dffr_s #(4) perr_dff(.din(perr_store_next[3:0]), .clk(clk), .q(perr_store[3:0]), `SIMPLY_RISC_SCANIN, .so(), .se(se), .rst(reset));
|
|
|
// calculate an early flush for killing writes in W
|
// calculate an early flush for killing writes in W
|
// the pic trap occurs if there are too many instructions on a given thread.
|
// the pic trap occurs if there are too many instructions on a given thread.
|
dff inst_vld_ww1(.din(ifu_exu_inst_vld_w), .clk(clk), .q(inst_vld_w1), .se(se), .si(), .so());
|
dff_s inst_vld_ww1(.din(ifu_exu_inst_vld_w), .clk(clk), .q(inst_vld_w1), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign pic_trap_m = ((tlu_exu_pic_onebelow_m & (thr_match_mw & ifu_exu_inst_vld_w |
|
assign pic_trap_m = ((tlu_exu_pic_onebelow_m & (thr_match_mw & ifu_exu_inst_vld_w |
|
thr_match_mw1 & inst_vld_w1)) |
|
thr_match_mw1 & inst_vld_w1)) |
|
(tlu_exu_pic_twobelow_m & thr_match_mw & ifu_exu_inst_vld_w &
|
(tlu_exu_pic_twobelow_m & thr_match_mw & ifu_exu_inst_vld_w &
|
thr_match_mw1 & inst_vld_w1));
|
thr_match_mw1 & inst_vld_w1));
|
assign part_early_flush_m = (exu_tlu_ttype_vld_m | ifu_exu_ttype_vld_m | exu_tlu_va_oor_jl_ret_m |
|
assign part_early_flush_m = (exu_tlu_ttype_vld_m | ifu_exu_ttype_vld_m | exu_tlu_va_oor_jl_ret_m |
|
perr_kill_m | pic_trap_m);
|
perr_kill_m | pic_trap_m);
|
dff priv_trap_dff(.din(tlu_exu_priv_trap_m), .clk(clk), .q(tlu_priv_trap_w), .se(se), .si(), .so());
|
dff_s priv_trap_dff(.din(tlu_exu_priv_trap_m), .clk(clk), .q(tlu_priv_trap_w), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff early_flush_dff(.din(part_early_flush_m), .clk(clk), .q(part_early_flush_w), .se(se), .si(), .so());
|
dff_s early_flush_dff(.din(part_early_flush_m), .clk(clk), .q(part_early_flush_w), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign early_flush_w = part_early_flush_w | tlu_priv_trap_w;
|
assign early_flush_w = part_early_flush_w | tlu_priv_trap_w;
|
assign ecl_rml_early_flush_w = early_flush_w;
|
assign ecl_rml_early_flush_w = early_flush_w;
|
|
|
// buffer this off so it only sees one load from the ifu
|
// buffer this off so it only sees one load from the ifu
|
assign ecl_rml_inst_vld_w = ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
|
assign ecl_rml_inst_vld_w = ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
|
|
|
dff flush_m2w(.din(ifu_tlu_flush_m), .clk(clk), .q(ifu_tlu_flush_w), .se(se), .si(), .so());
|
dff_s flush_m2w(.din(ifu_tlu_flush_m), .clk(clk), .q(ifu_tlu_flush_w), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign flush_w = ifu_tlu_flush_w | lsu_exu_flush_pipe_w;
|
assign flush_w = ifu_tlu_flush_w | lsu_exu_flush_pipe_w;
|
dff flush_w_dff(.din(flush_w), .clk(clk), .q(flush_w1), .se(se), .si(), .so());
|
dff_s flush_w_dff(.din(flush_w), .clk(clk), .q(flush_w1), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// allow misalign address on returns to kill the cwp switch
|
// allow misalign address on returns to kill the cwp switch
|
// ttype[7] is a fill_trap so the return misalign should be ignored
|
// ttype[7] is a fill_trap so the return misalign should be ignored
|
// UE trap should kill window ops. This check is needed here because the
|
// UE trap should kill window ops. This check is needed here because the
|
// window traps will override the flush_W signals.
|
// window traps will override the flush_W signals.
|
assign kill_rml_m = (ue_trap_m | ifu_exu_ttype_vld_m | perr_kill_m | pic_trap_m |
|
assign kill_rml_m = (ue_trap_m | ifu_exu_ttype_vld_m | perr_kill_m | pic_trap_m |
|
(exu_tlu_misalign_addr_jmpl_rtn_m & ~exu_tlu_ttype_m[7]));
|
(exu_tlu_misalign_addr_jmpl_rtn_m & ~exu_tlu_ttype_m[7]));
|
dff kill_rml_mw(.din(kill_rml_m), .clk(clk) , .q(kill_rml_w), .se(se), .si(), .so());
|
dff_s kill_rml_mw(.din(kill_rml_m), .clk(clk) , .q(kill_rml_w), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// include tlu_priv_trap to cancel window traps
|
// include tlu_priv_trap to cancel window traps
|
assign ecl_rml_kill_w = tlu_priv_trap_w | kill_rml_w;
|
assign ecl_rml_kill_w = tlu_priv_trap_w | kill_rml_w;
|
|
|
// pass kill_e through to the rml
|
// pass kill_e through to the rml
|
assign ecl_rml_kill_e = ifu_exu_kill_e;
|
assign ecl_rml_kill_e = ifu_exu_kill_e;
|
| Line 990... |
Line 995... |
assign ecl_exu_kill_m = thr_match_mw1 & flush_w1;
|
assign ecl_exu_kill_m = thr_match_mw1 & flush_w1;
|
assign thr_match_mw = ~((tid_w[1] ^ tid_m[1]) |
|
assign thr_match_mw = ~((tid_w[1] ^ tid_m[1]) |
|
(tid_w[0] ^ tid_m[0]));
|
(tid_w[0] ^ tid_m[0]));
|
assign thr_match_ew = ~((tid_e[1] ^ tid_w[1]) |
|
assign thr_match_ew = ~((tid_e[1] ^ tid_w[1]) |
|
(tid_e[0] ^ tid_w[0]));
|
(tid_e[0] ^ tid_w[0]));
|
dff thr_match_ew_dff(.din(thr_match_ew), .clk(clk), .q(thr_match_mw1), .se(se), .si(), .so());
|
dff_s thr_match_ew_dff(.din(thr_match_ew), .clk(clk), .q(thr_match_mw1), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// ldxa needs to check inst_vld and prior flushes
|
// ldxa needs to check inst_vld and prior flushes
|
assign ecl_byp_ldxa_g = ldxa_g & ifu_exu_inst_vld_w;
|
assign ecl_byp_ldxa_g = ldxa_g & ifu_exu_inst_vld_w;
|
|
|
// controls for outputs to lsu
|
// controls for outputs to lsu
|
assign std_d = ifu_exu_rs3e_vld_d & ifu_exu_rs3o_vld_d;
|
assign std_d = ifu_exu_rs3e_vld_d & ifu_exu_rs3o_vld_d;
|
dff std_d2e (.din(std_d), .q(std_e), .clk(clk), .se(se), .si(), .so());
|
dff_s std_d2e (.din(std_d), .q(std_e), .clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ecl_byp_std_e_l = ~std_e;
|
assign ecl_byp_std_e_l = ~std_e;
|
|
|
|
|
//////////////////////////////////////
|
//////////////////////////////////////
|
// Trap output logic
|
// Trap output logic
|
| Line 1053... |
Line 1058... |
.sel2(pick_not_aligned));
|
.sel2(pick_not_aligned));
|
assign exu_tlu_ttype_m[8:0] = (ue_trap_m)? 9'h029: early_ttype_m[8:0];
|
assign exu_tlu_ttype_m[8:0] = (ue_trap_m)? 9'h029: early_ttype_m[8:0];
|
assign exu_tlu_ttype_vld_m = early_ttype_vld_m | ue_trap_m | div_zero_m;
|
assign exu_tlu_ttype_vld_m = early_ttype_vld_m | ue_trap_m | div_zero_m;
|
assign exu_tlu_ue_trap_m = ue_trap_m;
|
assign exu_tlu_ue_trap_m = ue_trap_m;
|
|
|
dff ttype_vld_e2m(.din(early_ttype_vld_e), .clk(clk), .q(early_ttype_vld_m),
|
dff_s ttype_vld_e2m(.din(early_ttype_vld_e), .clk(clk), .q(early_ttype_vld_m),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(9) ttype_e2m(.din(early2_ttype_e[8:0]), .clk(clk), .q(early_ttype_m[8:0]),
|
dff_s #(9) ttype_e2m(.din(early2_ttype_e[8:0]), .clk(clk), .q(early_ttype_m[8:0]),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
// lsu needs to know about spill and ue traps for squashing sfsr writes
|
// lsu needs to know about spill and ue traps for squashing sfsr writes
|
dff fill_e2m(.din(fill_trap_e), .clk(clk), .q(fill_trap_m), .se(se), .si(), .so());
|
dff_s fill_e2m(.din(fill_trap_e), .clk(clk), .q(fill_trap_m), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign exu_lsu_priority_trap_m = fill_trap_m | ue_trap_m;
|
assign exu_lsu_priority_trap_m = fill_trap_m | ue_trap_m;
|
|
|
// Condition code Register
|
// Condition code Register
|
sparc_exu_eclccr ccr(.wb_ccr_thr_g(ecl_irf_tid_g[1:0]),
|
sparc_exu_eclccr ccr(.wb_ccr_thr_g(ecl_irf_tid_g[1:0]),
|
.thrdec_d (thr_d[3:0]),
|
.thrdec_d (thr_d[3:0]),
|
| Line 1242... |
Line 1247... |
.cancel_rs3_ecc_e(cancel_rs3_ecc_e));
|
.cancel_rs3_ecc_e(cancel_rs3_ecc_e));
|
// Bypass logic
|
// Bypass logic
|
// Precalculate some of the matching logic to help timing
|
// Precalculate some of the matching logic to help timing
|
assign thr_match_sd = ~((ifu_exu_tid_s2[1] ^ tid_d[1]) |
|
assign thr_match_sd = ~((ifu_exu_tid_s2[1] ^ tid_d[1]) |
|
(ifu_exu_tid_s2[0] ^ tid_d[0]));
|
(ifu_exu_tid_s2[0] ^ tid_d[0]));
|
dff thr_match_sd_dff(.din(thr_match_sd), .clk(clk), .q(thr_match_de),
|
dff_s thr_match_sd_dff(.din(thr_match_sd), .clk(clk), .q(thr_match_de),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign thr_match_se = ~((ifu_exu_tid_s2[1] ^ tid_e[1]) |
|
assign thr_match_se = ~((ifu_exu_tid_s2[1] ^ tid_e[1]) |
|
(ifu_exu_tid_s2[0] ^ tid_e[0]));
|
(ifu_exu_tid_s2[0] ^ tid_e[0]));
|
dff thr_match_se_dff(.din(thr_match_se), .clk(clk), .q(thr_match_dm),
|
dff_s thr_match_se_dff(.din(thr_match_se), .clk(clk), .q(thr_match_dm),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign ld_thr_match_sm = ~((ifu_exu_tid_s2[1] ^ lsu_exu_thr_m[1]) |
|
assign ld_thr_match_sm = ~((ifu_exu_tid_s2[1] ^ lsu_exu_thr_m[1]) |
|
(ifu_exu_tid_s2[0] ^ lsu_exu_thr_m[0]));
|
(ifu_exu_tid_s2[0] ^ lsu_exu_thr_m[0]));
|
dff ld_thr_match_sm_dff(.din(ld_thr_match_sm), .clk(clk), .q(ld_thr_match_dg), .se(se),
|
dff_s ld_thr_match_sm_dff(.din(ld_thr_match_sm), .clk(clk), .q(ld_thr_match_dg), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
assign ld_thr_match_sg = ~((ifu_exu_tid_s2[1] ^ ld_tid_g[1]) |
|
assign ld_thr_match_sg = ~((ifu_exu_tid_s2[1] ^ ld_tid_g[1]) |
|
(ifu_exu_tid_s2[0] ^ ld_tid_g[0]));
|
(ifu_exu_tid_s2[0] ^ ld_tid_g[0]));
|
dff ld_thr_match_sg_dff(.din(ld_thr_match_sg), .clk(clk), .q(ld_thr_match_dg2), .se(se),
|
dff_s ld_thr_match_sg_dff(.din(ld_thr_match_sg), .clk(clk), .q(ld_thr_match_dg2), .se(se),
|
.si(), .so());
|
`SIMPLY_RISC_SCANIN, .so());
|
sparc_exu_eclbyplog_rs1 byplog_rs1(.rs_sel_mux1_m(ecl_byp_rs1_mux1_sel_m),
|
sparc_exu_eclbyplog_rs1 byplog_rs1(.rs_sel_mux1_m(ecl_byp_rs1_mux1_sel_m),
|
.rs_sel_mux1_w(ecl_byp_rs1_mux1_sel_w),
|
.rs_sel_mux1_w(ecl_byp_rs1_mux1_sel_w),
|
.rs_sel_mux1_w2(ecl_byp_rs1_mux1_sel_w2),
|
.rs_sel_mux1_w2(ecl_byp_rs1_mux1_sel_w2),
|
.rs_sel_mux1_other(ecl_byp_rs1_mux1_sel_other),
|
.rs_sel_mux1_other(ecl_byp_rs1_mux1_sel_other),
|
.rs_sel_mux2_e(ecl_byp_rs1_mux2_sel_e),
|
.rs_sel_mux2_e(ecl_byp_rs1_mux2_sel_e),
|
