| Line 16... |
Line 16... |
// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_exu_divcntl
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// Module Name: sparc_exu_divcntl
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// Description: Control block for div. Division takes 1 cycle to load
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// Description: Control block for div. Division takes 1 cycle to load
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// the values, 65 cycles to calculate the result, and 1 cycle to
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// the values, 65 cycles to calculate the result, and 1 cycle to
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// calculate the ccs and check for overflow.
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// calculate the ccs and check for overflow.
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// Controlled by a one hot state machine and a 6 bit counter.
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// Controlled by a one hot state machine and a 6 bit counter.
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*/
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*/
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`define IDLE 0
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`define RUN 1
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`define LAST_CALC 2
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`define CHK_OVFL 3
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`define FIX_OVFL 4
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`define DONE 5
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module sparc_exu_ecl_divcntl (/*AUTOARG*/
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module sparc_exu_ecl_divcntl (/*AUTOARG*/
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// Outputs
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// Outputs
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ecl_div_xinmask, ecl_div_keep_d, ecl_div_ld_inputs,
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ecl_div_xinmask, ecl_div_keep_d, ecl_div_ld_inputs,
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ecl_div_sel_adder, ecl_div_last_cycle, ecl_div_almostlast_cycle,
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ecl_div_sel_adder, ecl_div_last_cycle, ecl_div_almostlast_cycle,
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| Line 169... |
Line 174... |
wire cntris63;
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wire cntris63;
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/////////////////////////////////
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/////////////////////////////////
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// G arbitration between MUL/DIV
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// G arbitration between MUL/DIV
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/////////////////////////////////
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/////////////////////////////////
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assign divcntl_wb_req_g = div_state[5] |
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assign divcntl_wb_req_g = div_state[`DONE] |
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(~(div_state[5] | div_state[3] | div_state[4]) &mdqctl_divcntl_muldone);
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(~(div_state[`DONE] | div_state[`CHK_OVFL] | div_state[`FIX_OVFL]) &mdqctl_divcntl_muldone);
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assign ecl_div_sel_div = ~(~(div_state[5] | div_state[3] | div_state[4]) &
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assign ecl_div_sel_div = ~(~(div_state[`DONE] | div_state[`CHK_OVFL] | div_state[`FIX_OVFL]) &
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mdqctl_divcntl_muldone);
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mdqctl_divcntl_muldone);
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// state flop
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// state flop
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dff #(6) divstate_dff(.din(next_state[5:0]), .clk(clk), .q(div_state[5:0]), .se(se), .si(),
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dff_s #(6) divstate_dff(.din(next_state[5:0]), .clk(clk), .q(div_state[5:0]), .se(se), `SIMPLY_RISC_SCANIN,
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.so());
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.so());
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// output logic and state decode
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// output logic and state decode
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assign ecl_div_almostlast_cycle = go_last_calc & ~ecl_div_ld_inputs;
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assign ecl_div_almostlast_cycle = go_last_calc & ~ecl_div_ld_inputs;
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assign ecl_div_sel_adder = (div_state[1] | div_state[2]) & ~ecl_div_ld_inputs;
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assign ecl_div_sel_adder = (div_state[`RUN] | div_state[`LAST_CALC]) & ~ecl_div_ld_inputs;
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assign ecl_div_last_cycle = div_state[2];
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assign ecl_div_last_cycle = div_state[`LAST_CALC];
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assign ecl_div_ld_inputs = mdqctl_divcntl_input_vld;
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assign ecl_div_ld_inputs = mdqctl_divcntl_input_vld;
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assign ecl_div_keep_d = ~(ecl_div_sel_adder | ecl_div_ld_inputs);
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assign ecl_div_keep_d = ~(ecl_div_sel_adder | ecl_div_ld_inputs);
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assign reset_cnt = ~div_state[1];
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assign reset_cnt = ~div_state[`RUN];
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// next state logic
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// next state logic
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assign stay_idle = div_state[0] & ~mdqctl_divcntl_input_vld;
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assign stay_idle = div_state[`IDLE] & ~mdqctl_divcntl_input_vld;
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assign go_idle = div_state[5] & wb_divcntl_ack_g;
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assign go_idle = div_state[`DONE] & wb_divcntl_ack_g;
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assign next_state[0] = go_idle | stay_idle | mdqctl_divcntl_reset_div | reset;
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assign next_state[`IDLE] = go_idle | stay_idle | mdqctl_divcntl_reset_div | reset;
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assign stay_run = div_state[1] & ~cntris63 & ~ecl_div_muls;
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assign stay_run = div_state[`RUN] & ~cntris63 & ~ecl_div_muls;
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assign go_run = (div_state[0] & mdqctl_divcntl_input_vld);
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assign go_run = (div_state[`IDLE] & mdqctl_divcntl_input_vld);
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assign next_state[1] = (go_run | stay_run) &
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assign next_state[`RUN] = (go_run | stay_run) &
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~mdqctl_divcntl_reset_div & ~reset;
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~mdqctl_divcntl_reset_div & ~reset;
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assign go_last_calc = div_state[1] & (cntris63);
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assign go_last_calc = div_state[`RUN] & (cntris63);
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assign next_state[2] = go_last_calc & ~mdqctl_divcntl_reset_div & ~reset;
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assign next_state[`LAST_CALC] = go_last_calc & ~mdqctl_divcntl_reset_div & ~reset;
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// chk_ovfl and fix_ovfl are place holders to guarantee that the overflow checking
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// chk_ovfl and fix_ovfl are place holders to guarantee that the overflow checking
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// takes place on the result. No special logic occurs in them compared to the done state.
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// takes place on the result. No special logic occurs in them compared to the done state.
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assign go_chk_ovfl = div_state[2];
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assign go_chk_ovfl = div_state[`LAST_CALC];
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assign next_state[3] = go_chk_ovfl & ~mdqctl_divcntl_reset_div & ~reset;
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assign next_state[`CHK_OVFL] = go_chk_ovfl & ~mdqctl_divcntl_reset_div & ~reset;
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assign go_fix_ovfl = div_state[3] | (div_state[1] & ecl_div_muls);
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assign go_fix_ovfl = div_state[`CHK_OVFL] | (div_state[`RUN] & ecl_div_muls);
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assign next_state[4] = go_fix_ovfl & ~mdqctl_divcntl_reset_div & ~reset;
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assign next_state[`FIX_OVFL] = go_fix_ovfl & ~mdqctl_divcntl_reset_div & ~reset;
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assign go_done = div_state[4];
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assign go_done = div_state[`FIX_OVFL];
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assign stay_done = div_state[5] & ~wb_divcntl_ack_g;
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assign stay_done = div_state[`DONE] & ~wb_divcntl_ack_g;
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assign next_state[5] = (go_done | stay_done) & ~mdqctl_divcntl_reset_div & ~reset;
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assign next_state[`DONE] = (go_done | stay_done) & ~mdqctl_divcntl_reset_div & ~reset;
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// counter
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// counter
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sparc_exu_ecl_cnt6 cnt6(.reset (reset_cnt),
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sparc_exu_ecl_cnt6 cnt6(.reset (reset_cnt),
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/*AUTOINST*/
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/*AUTOINST*/
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// Outputs
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// Outputs
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| Line 258... |
Line 263... |
dp_mux2es qnext_cout_mux(.dout(q_next),
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dp_mux2es qnext_cout_mux(.dout(q_next),
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.in0(q_next_nocout[1]),
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.in0(q_next_nocout[1]),
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.in1(q_next_nocout[0]),
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.in1(q_next_nocout[0]),
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.sel(div_ecl_cout64));
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.sel(div_ecl_cout64));
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dff q_dff(.din(q_next), .clk(clk), .q(ecl_div_newq), .se(se), .si(),
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dff_s q_dff(.din(q_next), .clk(clk), .q(ecl_div_newq), .se(se), `SIMPLY_RISC_SCANIN,
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.so());
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.so());
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////////////////////////////
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////////////////////////////
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// Subtraction logic and subtract flop
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// Subtraction logic and subtract flop
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| Line 285... |
Line 290... |
dp_mux2es subtract_cout_mux(.dout(sub_next),
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dp_mux2es subtract_cout_mux(.dout(sub_next),
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.in0(sub_next_nocout[1]),
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.in0(sub_next_nocout[1]),
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.in1(sub_next_nocout[0]),
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.in1(sub_next_nocout[0]),
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.sel(div_ecl_cout64));
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.sel(div_ecl_cout64));
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dff sub_dff(.din(sub_next), .clk(clk), .q(subtract), .se(se), .si(),
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dff_s sub_dff(.din(sub_next), .clk(clk), .q(subtract), .se(se), `SIMPLY_RISC_SCANIN,
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.so());
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.so());
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assign ecl_div_subtract_l = ~subtract;
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assign ecl_div_subtract_l = ~subtract;
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| Line 310... |
Line 315... |
(~div_ecl_d_62 | ecl_div_almostlast_cycle);
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(~div_ecl_d_62 | ecl_div_almostlast_cycle);
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-----/\----- EXCLUDED -----/\----- */
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-----/\----- EXCLUDED -----/\----- */
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assign new_zero_rem_with_zero = ~ecl_div_ld_inputs & (~div_ecl_d_62 | ecl_div_almostlast_cycle);
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assign new_zero_rem_with_zero = ~ecl_div_ld_inputs & (~div_ecl_d_62 | ecl_div_almostlast_cycle);
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assign new_zero_rem_no_zero = zero_rem_q & new_zero_rem_with_zero;
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assign new_zero_rem_no_zero = zero_rem_q & new_zero_rem_with_zero;
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assign zero_rem_d = (detect_zero)? new_zero_rem_with_zero: new_zero_rem_no_zero;
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assign zero_rem_d = (detect_zero)? new_zero_rem_with_zero: new_zero_rem_no_zero;
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dff zero_rem_dff(.din(zero_rem_d), .clk(clk), .q(zero_rem_q),
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dff_s zero_rem_dff(.din(zero_rem_d), .clk(clk), .q(zero_rem_q),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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/* -----\/----- EXCLUDED -----\/-----
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/* -----\/----- EXCLUDED -----\/-----
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// changed for timing
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// changed for timing
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assign last_cin_next = ecl_div_signed_div & (divisor_sign & ~div_ecl_d_62 |
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assign last_cin_next = ecl_div_signed_div & (divisor_sign & ~div_ecl_d_62 |
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~divisor_sign &div_ecl_d_62&~zero_rem_d |
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~divisor_sign &div_ecl_d_62&~zero_rem_d |
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| Line 326... |
Line 331... |
divisor_sign &div_ecl_d_62&new_zero_rem_with_zero);
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divisor_sign &div_ecl_d_62&new_zero_rem_with_zero);
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assign last_cin_no_zero = ecl_div_signed_div & (divisor_sign & ~div_ecl_d_62 |
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assign last_cin_no_zero = ecl_div_signed_div & (divisor_sign & ~div_ecl_d_62 |
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~divisor_sign &div_ecl_d_62&~new_zero_rem_no_zero |
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~divisor_sign &div_ecl_d_62&~new_zero_rem_no_zero |
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divisor_sign &div_ecl_d_62&new_zero_rem_no_zero);
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divisor_sign &div_ecl_d_62&new_zero_rem_no_zero);
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assign last_cin_next = (detect_zero)? last_cin_with_zero: last_cin_no_zero;
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assign last_cin_next = (detect_zero)? last_cin_with_zero: last_cin_no_zero;
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dff last_cin_dff(.din(last_cin_next), .clk(clk), .q(last_cin),
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dff_s last_cin_dff(.din(last_cin_next), .clk(clk), .q(last_cin),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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///////////////////////////////
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///////////////////////////////
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// Condition code generation
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// Condition code generation
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///////////////////////////////
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///////////////////////////////
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// There is a special case:
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// There is a special case:
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| Line 341... |
Line 346... |
wire inputs_neg_d;
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wire inputs_neg_d;
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wire inputs_neg_q;
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wire inputs_neg_q;
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wire large_neg_ovfl;
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wire large_neg_ovfl;
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assign inputs_neg_d = div_ecl_dividend_msb & div_ecl_divisorin_31;
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assign inputs_neg_d = div_ecl_dividend_msb & div_ecl_divisorin_31;
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assign large_neg_ovfl = inputs_neg_q & ~gencc_in_msb_l_d1;
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assign large_neg_ovfl = inputs_neg_q & ~gencc_in_msb_l_d1;
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dffe inputs_neg_dff(.din(inputs_neg_d), .clk(clk), .q(inputs_neg_q),
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dffe_s inputs_neg_dff(.din(inputs_neg_d), .clk(clk), .q(inputs_neg_q),
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.en(ecl_div_ld_inputs), .se(se), .si(), .so());
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.en(ecl_div_ld_inputs), .se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(5) cc_sig_dff(.din({div_ecl_upper32_equal, div_ecl_gencc_in_msb_l,
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dff_s #(5) cc_sig_dff(.din({div_ecl_upper32_equal, div_ecl_gencc_in_msb_l,
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div_ecl_gencc_in_31, ecl_div_sel_div, div_ecl_low32_nonzero}),
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div_ecl_gencc_in_31, ecl_div_sel_div, div_ecl_low32_nonzero}),
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.q({upper32_equal_d1, gencc_in_msb_l_d1,
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.q({upper32_equal_d1, gencc_in_msb_l_d1,
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gencc_in_31_d1, sel_div_d1, low32_nonzero_d1}),
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gencc_in_31_d1, sel_div_d1, low32_nonzero_d1}),
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.clk(clk), .se(se), .si(), .so());
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.clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
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// selects for correcting divide overflow
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// selects for correcting divide overflow
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assign ecl_div_sel_64b = ecl_div_div64 | ecl_div_muls;
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assign ecl_div_sel_64b = ecl_div_div64 | ecl_div_muls;
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assign ecl_div_sel_u32 = ~ecl_div_sel_64b & ~ecl_div_signed_div;
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assign ecl_div_sel_u32 = ~ecl_div_sel_64b & ~ecl_div_signed_div;
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assign ecl_div_sel_pos32 = (~ecl_div_sel_64b & ecl_div_signed_div &
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assign ecl_div_sel_pos32 = (~ecl_div_sel_64b & ecl_div_signed_div &
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(gencc_in_msb_l_d1 | large_neg_ovfl));
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(gencc_in_msb_l_d1 | large_neg_ovfl));
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| Line 371... |
Line 376... |
assign pos_ovfl = ecl_div_sel_pos32 & ~ecl_div_upper33_zero & sel_div_d1;
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assign pos_ovfl = ecl_div_sel_pos32 & ~ecl_div_upper33_zero & sel_div_d1;
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assign neg_ovfl = ecl_div_sel_neg32 & ~ecl_div_upper33_one & sel_div_d1;
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assign neg_ovfl = ecl_div_sel_neg32 & ~ecl_div_upper33_one & sel_div_d1;
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assign div_v = pos_ovfl | unsign_ovfl | neg_ovfl;
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assign div_v = pos_ovfl | unsign_ovfl | neg_ovfl;
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// muls carry and overflow
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// muls carry and overflow
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assign next_muls_c = (div_state[1]) ? div_ecl_cout32: muls_c;
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assign next_muls_c = (div_state[`RUN]) ? div_ecl_cout32: muls_c;
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assign muls_rs1_data_31_m = ~muls_rs1_31_m_l;
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assign muls_rs1_data_31_m = ~muls_rs1_31_m_l;
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dff #(3) muls_overlow_dff(.din({muls_rs1_data_31_m, rs2_data_31_m, div_ecl_adder_out_31}),
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dff_s #(3) muls_overlow_dff(.din({muls_rs1_data_31_m, rs2_data_31_m, div_ecl_adder_out_31}),
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.q({muls_rs1_data_31_w, rs2_data_31_w, div_adder_out_31_w}),
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.q({muls_rs1_data_31_w, rs2_data_31_w, div_adder_out_31_w}),
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.clk(clk), .se(se), .si(), .so());
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.clk(clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
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assign ovfl_32 = ((muls_rs1_data_31_w & rs2_data_31_w & ~div_adder_out_31_w) |
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assign ovfl_32 = ((muls_rs1_data_31_w & rs2_data_31_w & ~div_adder_out_31_w) |
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(~muls_rs1_data_31_w & ~rs2_data_31_w & div_adder_out_31_w));
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(~muls_rs1_data_31_w & ~rs2_data_31_w & div_adder_out_31_w));
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assign next_muls_v = (div_state[4]) ? ovfl_32: muls_v;
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assign next_muls_v = (div_state[`FIX_OVFL]) ? ovfl_32: muls_v;
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dff muls_c_dff(.din(next_muls_c), .clk(clk), .q(muls_c),
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dff_s muls_c_dff(.din(next_muls_c), .clk(clk), .q(muls_c),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff muls_v_dff(.din(next_muls_v), .clk(clk), .q(muls_v),
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dff_s muls_v_dff(.din(next_muls_v), .clk(clk), .q(muls_v),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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|
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// negative
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// negative
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assign xcc[3] = ~gencc_in_msb_l_d1 & ~unsign_ovfl & ~pos_ovfl;
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assign xcc[3] = ~gencc_in_msb_l_d1 & ~unsign_ovfl & ~pos_ovfl;
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assign icc[3] = (gencc_in_31_d1 & ~pos_ovfl) | neg_ovfl | unsign_ovfl;
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assign icc[3] = (gencc_in_31_d1 & ~pos_ovfl) | neg_ovfl | unsign_ovfl;
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// zero
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// zero
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